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types_arm_unix.go
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// Code generated by github.com/go-darwin/tools/cmd/mkgodef; DO NOT EDIT.
// Input to cgo -godefs.
//go:build ignore
// +build ignore
package capstone
// +godefs map cs_shift CsShift
// +godefs map cs_arm_op CsArm64Op
/*
#include <capstone/arm.h>
typedef struct cs_shift {
arm_shifter type;
unsigned int value;
} cs_shift;
typedef struct CsArmOp {
int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant)
cs_shift shift;
arm_op_type type; ///< operand type
int reg; ///< register value for REG/SYSREG operand
int32_t imm; ///< immediate value for C-IMM, P-IMM or IMM operand
double fp; ///< floating point value for FP operand
arm_op_mem mem; ///< base/index/scale/disp value for MEM operand
arm_setend_type setend; ///< SETEND instruction's operand type
/// in some instructions, an operand can be subtracted or added to
/// the base register,
/// if TRUE, this operand is subtracted. otherwise, it is added.
bool subtracted;
/// How is this operand accessed? (READ, WRITE or READ|WRITE)
/// This field is combined of cs_ac_type.
/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
uint8_t access;
/// Neon lane index for NEON instructions (or -1 if irrelevant)
int8_t neon_lane;
} CsArmOp;
*/
import "C"
type ArmCc C.enum_arm_cc
const (
ARM_CC_INVALID ArmCc = C.ARM_CC_INVALID
ARM_CC_EQ ArmCc = C.ARM_CC_EQ
ARM_CC_NE ArmCc = C.ARM_CC_NE
ARM_CC_HS ArmCc = C.ARM_CC_HS
ARM_CC_LO ArmCc = C.ARM_CC_LO
ARM_CC_MI ArmCc = C.ARM_CC_MI
ARM_CC_PL ArmCc = C.ARM_CC_PL
ARM_CC_VS ArmCc = C.ARM_CC_VS
ARM_CC_VC ArmCc = C.ARM_CC_VC
ARM_CC_HI ArmCc = C.ARM_CC_HI
ARM_CC_LS ArmCc = C.ARM_CC_LS
ARM_CC_GE ArmCc = C.ARM_CC_GE
ARM_CC_LT ArmCc = C.ARM_CC_LT
ARM_CC_GT ArmCc = C.ARM_CC_GT
ARM_CC_LE ArmCc = C.ARM_CC_LE
ARM_CC_AL ArmCc = C.ARM_CC_AL
)
type ArmCpsflagType C.enum_arm_cpsflag_type
const (
ARM_CPSFLAG_INVALID ArmCpsflagType = C.ARM_CPSFLAG_INVALID
ARM_CPSFLAG_F ArmCpsflagType = C.ARM_CPSFLAG_F
ARM_CPSFLAG_I ArmCpsflagType = C.ARM_CPSFLAG_I
ARM_CPSFLAG_A ArmCpsflagType = C.ARM_CPSFLAG_A
ARM_CPSFLAG_NONE ArmCpsflagType = C.ARM_CPSFLAG_NONE
)
type ArmCpsmodeType C.enum_arm_cpsmode_type
const (
ARM_CPSMODE_INVALID ArmCpsmodeType = C.ARM_CPSMODE_INVALID
ARM_CPSMODE_IE ArmCpsmodeType = C.ARM_CPSMODE_IE
ARM_CPSMODE_ID ArmCpsmodeType = C.ARM_CPSMODE_ID
)
type ArmInsn C.enum_arm_insn
const (
ARM_INS_INVALID ArmInsn = C.ARM_INS_INVALID
ARM_INS_ADC ArmInsn = C.ARM_INS_ADC
ARM_INS_ADD ArmInsn = C.ARM_INS_ADD
ARM_INS_ADDW ArmInsn = C.ARM_INS_ADDW
ARM_INS_ADR ArmInsn = C.ARM_INS_ADR
ARM_INS_AESD ArmInsn = C.ARM_INS_AESD
ARM_INS_AESE ArmInsn = C.ARM_INS_AESE
ARM_INS_AESIMC ArmInsn = C.ARM_INS_AESIMC
ARM_INS_AESMC ArmInsn = C.ARM_INS_AESMC
ARM_INS_AND ArmInsn = C.ARM_INS_AND
ARM_INS_ASR ArmInsn = C.ARM_INS_ASR
ARM_INS_B ArmInsn = C.ARM_INS_B
ARM_INS_BFC ArmInsn = C.ARM_INS_BFC
ARM_INS_BFI ArmInsn = C.ARM_INS_BFI
ARM_INS_BIC ArmInsn = C.ARM_INS_BIC
ARM_INS_BKPT ArmInsn = C.ARM_INS_BKPT
ARM_INS_BL ArmInsn = C.ARM_INS_BL
ARM_INS_BLX ArmInsn = C.ARM_INS_BLX
ARM_INS_BLXNS ArmInsn = C.ARM_INS_BLXNS
ARM_INS_BX ArmInsn = C.ARM_INS_BX
ARM_INS_BXJ ArmInsn = C.ARM_INS_BXJ
ARM_INS_BXNS ArmInsn = C.ARM_INS_BXNS
ARM_INS_CBNZ ArmInsn = C.ARM_INS_CBNZ
ARM_INS_CBZ ArmInsn = C.ARM_INS_CBZ
ARM_INS_CDP ArmInsn = C.ARM_INS_CDP
ARM_INS_CDP2 ArmInsn = C.ARM_INS_CDP2
ARM_INS_CLREX ArmInsn = C.ARM_INS_CLREX
ARM_INS_CLZ ArmInsn = C.ARM_INS_CLZ
ARM_INS_CMN ArmInsn = C.ARM_INS_CMN
ARM_INS_CMP ArmInsn = C.ARM_INS_CMP
ARM_INS_CPS ArmInsn = C.ARM_INS_CPS
ARM_INS_CRC32B ArmInsn = C.ARM_INS_CRC32B
ARM_INS_CRC32CB ArmInsn = C.ARM_INS_CRC32CB
ARM_INS_CRC32CH ArmInsn = C.ARM_INS_CRC32CH
ARM_INS_CRC32CW ArmInsn = C.ARM_INS_CRC32CW
ARM_INS_CRC32H ArmInsn = C.ARM_INS_CRC32H
ARM_INS_CRC32W ArmInsn = C.ARM_INS_CRC32W
ARM_INS_CSDB ArmInsn = C.ARM_INS_CSDB
ARM_INS_DBG ArmInsn = C.ARM_INS_DBG
ARM_INS_DCPS1 ArmInsn = C.ARM_INS_DCPS1
ARM_INS_DCPS2 ArmInsn = C.ARM_INS_DCPS2
ARM_INS_DCPS3 ArmInsn = C.ARM_INS_DCPS3
ARM_INS_DFB ArmInsn = C.ARM_INS_DFB
ARM_INS_DMB ArmInsn = C.ARM_INS_DMB
ARM_INS_DSB ArmInsn = C.ARM_INS_DSB
ARM_INS_EOR ArmInsn = C.ARM_INS_EOR
ARM_INS_ERET ArmInsn = C.ARM_INS_ERET
ARM_INS_ESB ArmInsn = C.ARM_INS_ESB
ARM_INS_FADDD ArmInsn = C.ARM_INS_FADDD
ARM_INS_FADDS ArmInsn = C.ARM_INS_FADDS
ARM_INS_FCMPZD ArmInsn = C.ARM_INS_FCMPZD
ARM_INS_FCMPZS ArmInsn = C.ARM_INS_FCMPZS
ARM_INS_FCONSTD ArmInsn = C.ARM_INS_FCONSTD
ARM_INS_FCONSTS ArmInsn = C.ARM_INS_FCONSTS
ARM_INS_FLDMDBX ArmInsn = C.ARM_INS_FLDMDBX
ARM_INS_FLDMIAX ArmInsn = C.ARM_INS_FLDMIAX
ARM_INS_FMDHR ArmInsn = C.ARM_INS_FMDHR
ARM_INS_FMDLR ArmInsn = C.ARM_INS_FMDLR
ARM_INS_FMSTAT ArmInsn = C.ARM_INS_FMSTAT
ARM_INS_FSTMDBX ArmInsn = C.ARM_INS_FSTMDBX
ARM_INS_FSTMIAX ArmInsn = C.ARM_INS_FSTMIAX
ARM_INS_FSUBD ArmInsn = C.ARM_INS_FSUBD
ARM_INS_FSUBS ArmInsn = C.ARM_INS_FSUBS
ARM_INS_HINT ArmInsn = C.ARM_INS_HINT
ARM_INS_HLT ArmInsn = C.ARM_INS_HLT
ARM_INS_HVC ArmInsn = C.ARM_INS_HVC
ARM_INS_ISB ArmInsn = C.ARM_INS_ISB
ARM_INS_IT ArmInsn = C.ARM_INS_IT
ARM_INS_LDA ArmInsn = C.ARM_INS_LDA
ARM_INS_LDAB ArmInsn = C.ARM_INS_LDAB
ARM_INS_LDAEX ArmInsn = C.ARM_INS_LDAEX
ARM_INS_LDAEXB ArmInsn = C.ARM_INS_LDAEXB
ARM_INS_LDAEXD ArmInsn = C.ARM_INS_LDAEXD
ARM_INS_LDAEXH ArmInsn = C.ARM_INS_LDAEXH
ARM_INS_LDAH ArmInsn = C.ARM_INS_LDAH
ARM_INS_LDC ArmInsn = C.ARM_INS_LDC
ARM_INS_LDC2 ArmInsn = C.ARM_INS_LDC2
ARM_INS_LDC2L ArmInsn = C.ARM_INS_LDC2L
ARM_INS_LDCL ArmInsn = C.ARM_INS_LDCL
ARM_INS_LDM ArmInsn = C.ARM_INS_LDM
ARM_INS_LDMDA ArmInsn = C.ARM_INS_LDMDA
ARM_INS_LDMDB ArmInsn = C.ARM_INS_LDMDB
ARM_INS_LDMIB ArmInsn = C.ARM_INS_LDMIB
ARM_INS_LDR ArmInsn = C.ARM_INS_LDR
ARM_INS_LDRB ArmInsn = C.ARM_INS_LDRB
ARM_INS_LDRBT ArmInsn = C.ARM_INS_LDRBT
ARM_INS_LDRD ArmInsn = C.ARM_INS_LDRD
ARM_INS_LDREX ArmInsn = C.ARM_INS_LDREX
ARM_INS_LDREXB ArmInsn = C.ARM_INS_LDREXB
ARM_INS_LDREXD ArmInsn = C.ARM_INS_LDREXD
ARM_INS_LDREXH ArmInsn = C.ARM_INS_LDREXH
ARM_INS_LDRH ArmInsn = C.ARM_INS_LDRH
ARM_INS_LDRHT ArmInsn = C.ARM_INS_LDRHT
ARM_INS_LDRSB ArmInsn = C.ARM_INS_LDRSB
ARM_INS_LDRSBT ArmInsn = C.ARM_INS_LDRSBT
ARM_INS_LDRSH ArmInsn = C.ARM_INS_LDRSH
ARM_INS_LDRSHT ArmInsn = C.ARM_INS_LDRSHT
ARM_INS_LDRT ArmInsn = C.ARM_INS_LDRT
ARM_INS_LSL ArmInsn = C.ARM_INS_LSL
ARM_INS_LSR ArmInsn = C.ARM_INS_LSR
ARM_INS_MCR ArmInsn = C.ARM_INS_MCR
ARM_INS_MCR2 ArmInsn = C.ARM_INS_MCR2
ARM_INS_MCRR ArmInsn = C.ARM_INS_MCRR
ARM_INS_MCRR2 ArmInsn = C.ARM_INS_MCRR2
ARM_INS_MLA ArmInsn = C.ARM_INS_MLA
ARM_INS_MLS ArmInsn = C.ARM_INS_MLS
ARM_INS_MOV ArmInsn = C.ARM_INS_MOV
ARM_INS_MOVS ArmInsn = C.ARM_INS_MOVS
ARM_INS_MOVT ArmInsn = C.ARM_INS_MOVT
ARM_INS_MOVW ArmInsn = C.ARM_INS_MOVW
ARM_INS_MRC ArmInsn = C.ARM_INS_MRC
ARM_INS_MRC2 ArmInsn = C.ARM_INS_MRC2
ARM_INS_MRRC ArmInsn = C.ARM_INS_MRRC
ARM_INS_MRRC2 ArmInsn = C.ARM_INS_MRRC2
ARM_INS_MRS ArmInsn = C.ARM_INS_MRS
ARM_INS_MSR ArmInsn = C.ARM_INS_MSR
ARM_INS_MUL ArmInsn = C.ARM_INS_MUL
ARM_INS_MVN ArmInsn = C.ARM_INS_MVN
ARM_INS_NEG ArmInsn = C.ARM_INS_NEG
ARM_INS_NOP ArmInsn = C.ARM_INS_NOP
ARM_INS_ORN ArmInsn = C.ARM_INS_ORN
ARM_INS_ORR ArmInsn = C.ARM_INS_ORR
ARM_INS_PKHBT ArmInsn = C.ARM_INS_PKHBT
ARM_INS_PKHTB ArmInsn = C.ARM_INS_PKHTB
ARM_INS_PLD ArmInsn = C.ARM_INS_PLD
ARM_INS_PLDW ArmInsn = C.ARM_INS_PLDW
ARM_INS_PLI ArmInsn = C.ARM_INS_PLI
ARM_INS_POP ArmInsn = C.ARM_INS_POP
ARM_INS_PUSH ArmInsn = C.ARM_INS_PUSH
ARM_INS_QADD ArmInsn = C.ARM_INS_QADD
ARM_INS_QADD16 ArmInsn = C.ARM_INS_QADD16
ARM_INS_QADD8 ArmInsn = C.ARM_INS_QADD8
ARM_INS_QASX ArmInsn = C.ARM_INS_QASX
ARM_INS_QDADD ArmInsn = C.ARM_INS_QDADD
ARM_INS_QDSUB ArmInsn = C.ARM_INS_QDSUB
ARM_INS_QSAX ArmInsn = C.ARM_INS_QSAX
ARM_INS_QSUB ArmInsn = C.ARM_INS_QSUB
ARM_INS_QSUB16 ArmInsn = C.ARM_INS_QSUB16
ARM_INS_QSUB8 ArmInsn = C.ARM_INS_QSUB8
ARM_INS_RBIT ArmInsn = C.ARM_INS_RBIT
ARM_INS_REV ArmInsn = C.ARM_INS_REV
ARM_INS_REV16 ArmInsn = C.ARM_INS_REV16
ARM_INS_REVSH ArmInsn = C.ARM_INS_REVSH
ARM_INS_RFEDA ArmInsn = C.ARM_INS_RFEDA
ARM_INS_RFEDB ArmInsn = C.ARM_INS_RFEDB
ARM_INS_RFEIA ArmInsn = C.ARM_INS_RFEIA
ARM_INS_RFEIB ArmInsn = C.ARM_INS_RFEIB
ARM_INS_ROR ArmInsn = C.ARM_INS_ROR
ARM_INS_RRX ArmInsn = C.ARM_INS_RRX
ARM_INS_RSB ArmInsn = C.ARM_INS_RSB
ARM_INS_RSC ArmInsn = C.ARM_INS_RSC
ARM_INS_SADD16 ArmInsn = C.ARM_INS_SADD16
ARM_INS_SADD8 ArmInsn = C.ARM_INS_SADD8
ARM_INS_SASX ArmInsn = C.ARM_INS_SASX
ARM_INS_SBC ArmInsn = C.ARM_INS_SBC
ARM_INS_SBFX ArmInsn = C.ARM_INS_SBFX
ARM_INS_SDIV ArmInsn = C.ARM_INS_SDIV
ARM_INS_SEL ArmInsn = C.ARM_INS_SEL
ARM_INS_SETEND ArmInsn = C.ARM_INS_SETEND
ARM_INS_SETPAN ArmInsn = C.ARM_INS_SETPAN
ARM_INS_SEV ArmInsn = C.ARM_INS_SEV
ARM_INS_SEVL ArmInsn = C.ARM_INS_SEVL
ARM_INS_SG ArmInsn = C.ARM_INS_SG
ARM_INS_SHA1C ArmInsn = C.ARM_INS_SHA1C
ARM_INS_SHA1H ArmInsn = C.ARM_INS_SHA1H
ARM_INS_SHA1M ArmInsn = C.ARM_INS_SHA1M
ARM_INS_SHA1P ArmInsn = C.ARM_INS_SHA1P
ARM_INS_SHA1SU0 ArmInsn = C.ARM_INS_SHA1SU0
ARM_INS_SHA1SU1 ArmInsn = C.ARM_INS_SHA1SU1
ARM_INS_SHA256H ArmInsn = C.ARM_INS_SHA256H
ARM_INS_SHA256H2 ArmInsn = C.ARM_INS_SHA256H2
ARM_INS_SHA256SU0 ArmInsn = C.ARM_INS_SHA256SU0
ARM_INS_SHA256SU1 ArmInsn = C.ARM_INS_SHA256SU1
ARM_INS_SHADD16 ArmInsn = C.ARM_INS_SHADD16
ARM_INS_SHADD8 ArmInsn = C.ARM_INS_SHADD8
ARM_INS_SHASX ArmInsn = C.ARM_INS_SHASX
ARM_INS_SHSAX ArmInsn = C.ARM_INS_SHSAX
ARM_INS_SHSUB16 ArmInsn = C.ARM_INS_SHSUB16
ARM_INS_SHSUB8 ArmInsn = C.ARM_INS_SHSUB8
ARM_INS_SMC ArmInsn = C.ARM_INS_SMC
ARM_INS_SMLABB ArmInsn = C.ARM_INS_SMLABB
ARM_INS_SMLABT ArmInsn = C.ARM_INS_SMLABT
ARM_INS_SMLAD ArmInsn = C.ARM_INS_SMLAD
ARM_INS_SMLADX ArmInsn = C.ARM_INS_SMLADX
ARM_INS_SMLAL ArmInsn = C.ARM_INS_SMLAL
ARM_INS_SMLALBB ArmInsn = C.ARM_INS_SMLALBB
ARM_INS_SMLALBT ArmInsn = C.ARM_INS_SMLALBT
ARM_INS_SMLALD ArmInsn = C.ARM_INS_SMLALD
ARM_INS_SMLALDX ArmInsn = C.ARM_INS_SMLALDX
ARM_INS_SMLALTB ArmInsn = C.ARM_INS_SMLALTB
ARM_INS_SMLALTT ArmInsn = C.ARM_INS_SMLALTT
ARM_INS_SMLATB ArmInsn = C.ARM_INS_SMLATB
ARM_INS_SMLATT ArmInsn = C.ARM_INS_SMLATT
ARM_INS_SMLAWB ArmInsn = C.ARM_INS_SMLAWB
ARM_INS_SMLAWT ArmInsn = C.ARM_INS_SMLAWT
ARM_INS_SMLSD ArmInsn = C.ARM_INS_SMLSD
ARM_INS_SMLSDX ArmInsn = C.ARM_INS_SMLSDX
ARM_INS_SMLSLD ArmInsn = C.ARM_INS_SMLSLD
ARM_INS_SMLSLDX ArmInsn = C.ARM_INS_SMLSLDX
ARM_INS_SMMLA ArmInsn = C.ARM_INS_SMMLA
ARM_INS_SMMLAR ArmInsn = C.ARM_INS_SMMLAR
ARM_INS_SMMLS ArmInsn = C.ARM_INS_SMMLS
ARM_INS_SMMLSR ArmInsn = C.ARM_INS_SMMLSR
ARM_INS_SMMUL ArmInsn = C.ARM_INS_SMMUL
ARM_INS_SMMULR ArmInsn = C.ARM_INS_SMMULR
ARM_INS_SMUAD ArmInsn = C.ARM_INS_SMUAD
ARM_INS_SMUADX ArmInsn = C.ARM_INS_SMUADX
ARM_INS_SMULBB ArmInsn = C.ARM_INS_SMULBB
ARM_INS_SMULBT ArmInsn = C.ARM_INS_SMULBT
ARM_INS_SMULL ArmInsn = C.ARM_INS_SMULL
ARM_INS_SMULTB ArmInsn = C.ARM_INS_SMULTB
ARM_INS_SMULTT ArmInsn = C.ARM_INS_SMULTT
ARM_INS_SMULWB ArmInsn = C.ARM_INS_SMULWB
ARM_INS_SMULWT ArmInsn = C.ARM_INS_SMULWT
ARM_INS_SMUSD ArmInsn = C.ARM_INS_SMUSD
ARM_INS_SMUSDX ArmInsn = C.ARM_INS_SMUSDX
ARM_INS_SRSDA ArmInsn = C.ARM_INS_SRSDA
ARM_INS_SRSDB ArmInsn = C.ARM_INS_SRSDB
ARM_INS_SRSIA ArmInsn = C.ARM_INS_SRSIA
ARM_INS_SRSIB ArmInsn = C.ARM_INS_SRSIB
ARM_INS_SSAT ArmInsn = C.ARM_INS_SSAT
ARM_INS_SSAT16 ArmInsn = C.ARM_INS_SSAT16
ARM_INS_SSAX ArmInsn = C.ARM_INS_SSAX
ARM_INS_SSUB16 ArmInsn = C.ARM_INS_SSUB16
ARM_INS_SSUB8 ArmInsn = C.ARM_INS_SSUB8
ARM_INS_STC ArmInsn = C.ARM_INS_STC
ARM_INS_STC2 ArmInsn = C.ARM_INS_STC2
ARM_INS_STC2L ArmInsn = C.ARM_INS_STC2L
ARM_INS_STCL ArmInsn = C.ARM_INS_STCL
ARM_INS_STL ArmInsn = C.ARM_INS_STL
ARM_INS_STLB ArmInsn = C.ARM_INS_STLB
ARM_INS_STLEX ArmInsn = C.ARM_INS_STLEX
ARM_INS_STLEXB ArmInsn = C.ARM_INS_STLEXB
ARM_INS_STLEXD ArmInsn = C.ARM_INS_STLEXD
ARM_INS_STLEXH ArmInsn = C.ARM_INS_STLEXH
ARM_INS_STLH ArmInsn = C.ARM_INS_STLH
ARM_INS_STM ArmInsn = C.ARM_INS_STM
ARM_INS_STMDA ArmInsn = C.ARM_INS_STMDA
ARM_INS_STMDB ArmInsn = C.ARM_INS_STMDB
ARM_INS_STMIB ArmInsn = C.ARM_INS_STMIB
ARM_INS_STR ArmInsn = C.ARM_INS_STR
ARM_INS_STRB ArmInsn = C.ARM_INS_STRB
ARM_INS_STRBT ArmInsn = C.ARM_INS_STRBT
ARM_INS_STRD ArmInsn = C.ARM_INS_STRD
ARM_INS_STREX ArmInsn = C.ARM_INS_STREX
ARM_INS_STREXB ArmInsn = C.ARM_INS_STREXB
ARM_INS_STREXD ArmInsn = C.ARM_INS_STREXD
ARM_INS_STREXH ArmInsn = C.ARM_INS_STREXH
ARM_INS_STRH ArmInsn = C.ARM_INS_STRH
ARM_INS_STRHT ArmInsn = C.ARM_INS_STRHT
ARM_INS_STRT ArmInsn = C.ARM_INS_STRT
ARM_INS_SUB ArmInsn = C.ARM_INS_SUB
ARM_INS_SUBS ArmInsn = C.ARM_INS_SUBS
ARM_INS_SUBW ArmInsn = C.ARM_INS_SUBW
ARM_INS_SVC ArmInsn = C.ARM_INS_SVC
ARM_INS_SWP ArmInsn = C.ARM_INS_SWP
ARM_INS_SWPB ArmInsn = C.ARM_INS_SWPB
ARM_INS_SXTAB ArmInsn = C.ARM_INS_SXTAB
ARM_INS_SXTAB16 ArmInsn = C.ARM_INS_SXTAB16
ARM_INS_SXTAH ArmInsn = C.ARM_INS_SXTAH
ARM_INS_SXTB ArmInsn = C.ARM_INS_SXTB
ARM_INS_SXTB16 ArmInsn = C.ARM_INS_SXTB16
ARM_INS_SXTH ArmInsn = C.ARM_INS_SXTH
ARM_INS_TBB ArmInsn = C.ARM_INS_TBB
ARM_INS_TBH ArmInsn = C.ARM_INS_TBH
ARM_INS_TEQ ArmInsn = C.ARM_INS_TEQ
ARM_INS_TRAP ArmInsn = C.ARM_INS_TRAP
ARM_INS_TSB ArmInsn = C.ARM_INS_TSB
ARM_INS_TST ArmInsn = C.ARM_INS_TST
ARM_INS_TT ArmInsn = C.ARM_INS_TT
ARM_INS_TTA ArmInsn = C.ARM_INS_TTA
ARM_INS_TTAT ArmInsn = C.ARM_INS_TTAT
ARM_INS_TTT ArmInsn = C.ARM_INS_TTT
ARM_INS_UADD16 ArmInsn = C.ARM_INS_UADD16
ARM_INS_UADD8 ArmInsn = C.ARM_INS_UADD8
ARM_INS_UASX ArmInsn = C.ARM_INS_UASX
ARM_INS_UBFX ArmInsn = C.ARM_INS_UBFX
ARM_INS_UDF ArmInsn = C.ARM_INS_UDF
ARM_INS_UDIV ArmInsn = C.ARM_INS_UDIV
ARM_INS_UHADD16 ArmInsn = C.ARM_INS_UHADD16
ARM_INS_UHADD8 ArmInsn = C.ARM_INS_UHADD8
ARM_INS_UHASX ArmInsn = C.ARM_INS_UHASX
ARM_INS_UHSAX ArmInsn = C.ARM_INS_UHSAX
ARM_INS_UHSUB16 ArmInsn = C.ARM_INS_UHSUB16
ARM_INS_UHSUB8 ArmInsn = C.ARM_INS_UHSUB8
ARM_INS_UMAAL ArmInsn = C.ARM_INS_UMAAL
ARM_INS_UMLAL ArmInsn = C.ARM_INS_UMLAL
ARM_INS_UMULL ArmInsn = C.ARM_INS_UMULL
ARM_INS_UQADD16 ArmInsn = C.ARM_INS_UQADD16
ARM_INS_UQADD8 ArmInsn = C.ARM_INS_UQADD8
ARM_INS_UQASX ArmInsn = C.ARM_INS_UQASX
ARM_INS_UQSAX ArmInsn = C.ARM_INS_UQSAX
ARM_INS_UQSUB16 ArmInsn = C.ARM_INS_UQSUB16
ARM_INS_UQSUB8 ArmInsn = C.ARM_INS_UQSUB8
ARM_INS_USAD8 ArmInsn = C.ARM_INS_USAD8
ARM_INS_USADA8 ArmInsn = C.ARM_INS_USADA8
ARM_INS_USAT ArmInsn = C.ARM_INS_USAT
ARM_INS_USAT16 ArmInsn = C.ARM_INS_USAT16
ARM_INS_USAX ArmInsn = C.ARM_INS_USAX
ARM_INS_USUB16 ArmInsn = C.ARM_INS_USUB16
ARM_INS_USUB8 ArmInsn = C.ARM_INS_USUB8
ARM_INS_UXTAB ArmInsn = C.ARM_INS_UXTAB
ARM_INS_UXTAB16 ArmInsn = C.ARM_INS_UXTAB16
ARM_INS_UXTAH ArmInsn = C.ARM_INS_UXTAH
ARM_INS_UXTB ArmInsn = C.ARM_INS_UXTB
ARM_INS_UXTB16 ArmInsn = C.ARM_INS_UXTB16
ARM_INS_UXTH ArmInsn = C.ARM_INS_UXTH
ARM_INS_VABA ArmInsn = C.ARM_INS_VABA
ARM_INS_VABAL ArmInsn = C.ARM_INS_VABAL
ARM_INS_VABD ArmInsn = C.ARM_INS_VABD
ARM_INS_VABDL ArmInsn = C.ARM_INS_VABDL
ARM_INS_VABS ArmInsn = C.ARM_INS_VABS
ARM_INS_VACGE ArmInsn = C.ARM_INS_VACGE
ARM_INS_VACGT ArmInsn = C.ARM_INS_VACGT
ARM_INS_VACLE ArmInsn = C.ARM_INS_VACLE
ARM_INS_VACLT ArmInsn = C.ARM_INS_VACLT
ARM_INS_VADD ArmInsn = C.ARM_INS_VADD
ARM_INS_VADDHN ArmInsn = C.ARM_INS_VADDHN
ARM_INS_VADDL ArmInsn = C.ARM_INS_VADDL
ARM_INS_VADDW ArmInsn = C.ARM_INS_VADDW
ARM_INS_VAND ArmInsn = C.ARM_INS_VAND
ARM_INS_VBIC ArmInsn = C.ARM_INS_VBIC
ARM_INS_VBIF ArmInsn = C.ARM_INS_VBIF
ARM_INS_VBIT ArmInsn = C.ARM_INS_VBIT
ARM_INS_VBSL ArmInsn = C.ARM_INS_VBSL
ARM_INS_VCADD ArmInsn = C.ARM_INS_VCADD
ARM_INS_VCEQ ArmInsn = C.ARM_INS_VCEQ
ARM_INS_VCGE ArmInsn = C.ARM_INS_VCGE
ARM_INS_VCGT ArmInsn = C.ARM_INS_VCGT
ARM_INS_VCLE ArmInsn = C.ARM_INS_VCLE
ARM_INS_VCLS ArmInsn = C.ARM_INS_VCLS
ARM_INS_VCLT ArmInsn = C.ARM_INS_VCLT
ARM_INS_VCLZ ArmInsn = C.ARM_INS_VCLZ
ARM_INS_VCMLA ArmInsn = C.ARM_INS_VCMLA
ARM_INS_VCMP ArmInsn = C.ARM_INS_VCMP
ARM_INS_VCMPE ArmInsn = C.ARM_INS_VCMPE
ARM_INS_VCNT ArmInsn = C.ARM_INS_VCNT
ARM_INS_VCVT ArmInsn = C.ARM_INS_VCVT
ARM_INS_VCVTA ArmInsn = C.ARM_INS_VCVTA
ARM_INS_VCVTB ArmInsn = C.ARM_INS_VCVTB
ARM_INS_VCVTM ArmInsn = C.ARM_INS_VCVTM
ARM_INS_VCVTN ArmInsn = C.ARM_INS_VCVTN
ARM_INS_VCVTP ArmInsn = C.ARM_INS_VCVTP
ARM_INS_VCVTR ArmInsn = C.ARM_INS_VCVTR
ARM_INS_VCVTT ArmInsn = C.ARM_INS_VCVTT
ARM_INS_VDIV ArmInsn = C.ARM_INS_VDIV
ARM_INS_VDUP ArmInsn = C.ARM_INS_VDUP
ARM_INS_VEOR ArmInsn = C.ARM_INS_VEOR
ARM_INS_VEXT ArmInsn = C.ARM_INS_VEXT
ARM_INS_VFMA ArmInsn = C.ARM_INS_VFMA
ARM_INS_VFMS ArmInsn = C.ARM_INS_VFMS
ARM_INS_VFNMA ArmInsn = C.ARM_INS_VFNMA
ARM_INS_VFNMS ArmInsn = C.ARM_INS_VFNMS
ARM_INS_VHADD ArmInsn = C.ARM_INS_VHADD
ARM_INS_VHSUB ArmInsn = C.ARM_INS_VHSUB
ARM_INS_VINS ArmInsn = C.ARM_INS_VINS
ARM_INS_VJCVT ArmInsn = C.ARM_INS_VJCVT
ARM_INS_VLD1 ArmInsn = C.ARM_INS_VLD1
ARM_INS_VLD2 ArmInsn = C.ARM_INS_VLD2
ARM_INS_VLD3 ArmInsn = C.ARM_INS_VLD3
ARM_INS_VLD4 ArmInsn = C.ARM_INS_VLD4
ARM_INS_VLDMDB ArmInsn = C.ARM_INS_VLDMDB
ARM_INS_VLDMIA ArmInsn = C.ARM_INS_VLDMIA
ARM_INS_VLDR ArmInsn = C.ARM_INS_VLDR
ARM_INS_VLLDM ArmInsn = C.ARM_INS_VLLDM
ARM_INS_VLSTM ArmInsn = C.ARM_INS_VLSTM
ARM_INS_VMAX ArmInsn = C.ARM_INS_VMAX
ARM_INS_VMAXNM ArmInsn = C.ARM_INS_VMAXNM
ARM_INS_VMIN ArmInsn = C.ARM_INS_VMIN
ARM_INS_VMINNM ArmInsn = C.ARM_INS_VMINNM
ARM_INS_VMLA ArmInsn = C.ARM_INS_VMLA
ARM_INS_VMLAL ArmInsn = C.ARM_INS_VMLAL
ARM_INS_VMLS ArmInsn = C.ARM_INS_VMLS
ARM_INS_VMLSL ArmInsn = C.ARM_INS_VMLSL
ARM_INS_VMOV ArmInsn = C.ARM_INS_VMOV
ARM_INS_VMOVL ArmInsn = C.ARM_INS_VMOVL
ARM_INS_VMOVN ArmInsn = C.ARM_INS_VMOVN
ARM_INS_VMOVX ArmInsn = C.ARM_INS_VMOVX
ARM_INS_VMRS ArmInsn = C.ARM_INS_VMRS
ARM_INS_VMSR ArmInsn = C.ARM_INS_VMSR
ARM_INS_VMUL ArmInsn = C.ARM_INS_VMUL
ARM_INS_VMULL ArmInsn = C.ARM_INS_VMULL
ARM_INS_VMVN ArmInsn = C.ARM_INS_VMVN
ARM_INS_VNEG ArmInsn = C.ARM_INS_VNEG
ARM_INS_VNMLA ArmInsn = C.ARM_INS_VNMLA
ARM_INS_VNMLS ArmInsn = C.ARM_INS_VNMLS
ARM_INS_VNMUL ArmInsn = C.ARM_INS_VNMUL
ARM_INS_VORN ArmInsn = C.ARM_INS_VORN
ARM_INS_VORR ArmInsn = C.ARM_INS_VORR
ARM_INS_VPADAL ArmInsn = C.ARM_INS_VPADAL
ARM_INS_VPADD ArmInsn = C.ARM_INS_VPADD
ARM_INS_VPADDL ArmInsn = C.ARM_INS_VPADDL
ARM_INS_VPMAX ArmInsn = C.ARM_INS_VPMAX
ARM_INS_VPMIN ArmInsn = C.ARM_INS_VPMIN
ARM_INS_VPOP ArmInsn = C.ARM_INS_VPOP
ARM_INS_VPUSH ArmInsn = C.ARM_INS_VPUSH
ARM_INS_VQABS ArmInsn = C.ARM_INS_VQABS
ARM_INS_VQADD ArmInsn = C.ARM_INS_VQADD
ARM_INS_VQDMLAL ArmInsn = C.ARM_INS_VQDMLAL
ARM_INS_VQDMLSL ArmInsn = C.ARM_INS_VQDMLSL
ARM_INS_VQDMULH ArmInsn = C.ARM_INS_VQDMULH
ARM_INS_VQDMULL ArmInsn = C.ARM_INS_VQDMULL
ARM_INS_VQMOVN ArmInsn = C.ARM_INS_VQMOVN
ARM_INS_VQMOVUN ArmInsn = C.ARM_INS_VQMOVUN
ARM_INS_VQNEG ArmInsn = C.ARM_INS_VQNEG
ARM_INS_VQRDMLAH ArmInsn = C.ARM_INS_VQRDMLAH
ARM_INS_VQRDMLSH ArmInsn = C.ARM_INS_VQRDMLSH
ARM_INS_VQRDMULH ArmInsn = C.ARM_INS_VQRDMULH
ARM_INS_VQRSHL ArmInsn = C.ARM_INS_VQRSHL
ARM_INS_VQRSHRN ArmInsn = C.ARM_INS_VQRSHRN
ARM_INS_VQRSHRUN ArmInsn = C.ARM_INS_VQRSHRUN
ARM_INS_VQSHL ArmInsn = C.ARM_INS_VQSHL
ARM_INS_VQSHLU ArmInsn = C.ARM_INS_VQSHLU
ARM_INS_VQSHRN ArmInsn = C.ARM_INS_VQSHRN
ARM_INS_VQSHRUN ArmInsn = C.ARM_INS_VQSHRUN
ARM_INS_VQSUB ArmInsn = C.ARM_INS_VQSUB
ARM_INS_VRADDHN ArmInsn = C.ARM_INS_VRADDHN
ARM_INS_VRECPE ArmInsn = C.ARM_INS_VRECPE
ARM_INS_VRECPS ArmInsn = C.ARM_INS_VRECPS
ARM_INS_VREV16 ArmInsn = C.ARM_INS_VREV16
ARM_INS_VREV32 ArmInsn = C.ARM_INS_VREV32
ARM_INS_VREV64 ArmInsn = C.ARM_INS_VREV64
ARM_INS_VRHADD ArmInsn = C.ARM_INS_VRHADD
ARM_INS_VRINTA ArmInsn = C.ARM_INS_VRINTA
ARM_INS_VRINTM ArmInsn = C.ARM_INS_VRINTM
ARM_INS_VRINTN ArmInsn = C.ARM_INS_VRINTN
ARM_INS_VRINTP ArmInsn = C.ARM_INS_VRINTP
ARM_INS_VRINTR ArmInsn = C.ARM_INS_VRINTR
ARM_INS_VRINTX ArmInsn = C.ARM_INS_VRINTX
ARM_INS_VRINTZ ArmInsn = C.ARM_INS_VRINTZ
ARM_INS_VRSHL ArmInsn = C.ARM_INS_VRSHL
ARM_INS_VRSHR ArmInsn = C.ARM_INS_VRSHR
ARM_INS_VRSHRN ArmInsn = C.ARM_INS_VRSHRN
ARM_INS_VRSQRTE ArmInsn = C.ARM_INS_VRSQRTE
ARM_INS_VRSQRTS ArmInsn = C.ARM_INS_VRSQRTS
ARM_INS_VRSRA ArmInsn = C.ARM_INS_VRSRA
ARM_INS_VRSUBHN ArmInsn = C.ARM_INS_VRSUBHN
ARM_INS_VSDOT ArmInsn = C.ARM_INS_VSDOT
ARM_INS_VSELEQ ArmInsn = C.ARM_INS_VSELEQ
ARM_INS_VSELGE ArmInsn = C.ARM_INS_VSELGE
ARM_INS_VSELGT ArmInsn = C.ARM_INS_VSELGT
ARM_INS_VSELVS ArmInsn = C.ARM_INS_VSELVS
ARM_INS_VSHL ArmInsn = C.ARM_INS_VSHL
ARM_INS_VSHLL ArmInsn = C.ARM_INS_VSHLL
ARM_INS_VSHR ArmInsn = C.ARM_INS_VSHR
ARM_INS_VSHRN ArmInsn = C.ARM_INS_VSHRN
ARM_INS_VSLI ArmInsn = C.ARM_INS_VSLI
ARM_INS_VSQRT ArmInsn = C.ARM_INS_VSQRT
ARM_INS_VSRA ArmInsn = C.ARM_INS_VSRA
ARM_INS_VSRI ArmInsn = C.ARM_INS_VSRI
ARM_INS_VST1 ArmInsn = C.ARM_INS_VST1
ARM_INS_VST2 ArmInsn = C.ARM_INS_VST2
ARM_INS_VST3 ArmInsn = C.ARM_INS_VST3
ARM_INS_VST4 ArmInsn = C.ARM_INS_VST4
ARM_INS_VSTMDB ArmInsn = C.ARM_INS_VSTMDB
ARM_INS_VSTMIA ArmInsn = C.ARM_INS_VSTMIA
ARM_INS_VSTR ArmInsn = C.ARM_INS_VSTR
ARM_INS_VSUB ArmInsn = C.ARM_INS_VSUB
ARM_INS_VSUBHN ArmInsn = C.ARM_INS_VSUBHN
ARM_INS_VSUBL ArmInsn = C.ARM_INS_VSUBL
ARM_INS_VSUBW ArmInsn = C.ARM_INS_VSUBW
ARM_INS_VSWP ArmInsn = C.ARM_INS_VSWP
ARM_INS_VTBL ArmInsn = C.ARM_INS_VTBL
ARM_INS_VTBX ArmInsn = C.ARM_INS_VTBX
ARM_INS_VTRN ArmInsn = C.ARM_INS_VTRN
ARM_INS_VTST ArmInsn = C.ARM_INS_VTST
ARM_INS_VUDOT ArmInsn = C.ARM_INS_VUDOT
ARM_INS_VUZP ArmInsn = C.ARM_INS_VUZP
ARM_INS_VZIP ArmInsn = C.ARM_INS_VZIP
ARM_INS_WFE ArmInsn = C.ARM_INS_WFE
ARM_INS_WFI ArmInsn = C.ARM_INS_WFI
ARM_INS_YIELD ArmInsn = C.ARM_INS_YIELD
ARM_INS_ENDING ArmInsn = C.ARM_INS_ENDING
)
type ArmInsnGroup C.enum_arm_insn_group
const (
ARM_GRP_INVALID ArmInsnGroup = C.ARM_GRP_INVALID
ARM_GRP_JUMP ArmInsnGroup = C.ARM_GRP_JUMP
ARM_GRP_CALL ArmInsnGroup = C.ARM_GRP_CALL
ARM_GRP_INT ArmInsnGroup = C.ARM_GRP_INT
ARM_GRP_PRIVILEGE ArmInsnGroup = C.ARM_GRP_PRIVILEGE
ARM_GRP_BRANCH_RELATIVE ArmInsnGroup = C.ARM_GRP_BRANCH_RELATIVE
ARM_GRP_CRYPTO ArmInsnGroup = C.ARM_GRP_CRYPTO
ARM_GRP_DATABARRIER ArmInsnGroup = C.ARM_GRP_DATABARRIER
ARM_GRP_DIVIDE ArmInsnGroup = C.ARM_GRP_DIVIDE
ARM_GRP_FPARMV8 ArmInsnGroup = C.ARM_GRP_FPARMV8
ARM_GRP_MULTPRO ArmInsnGroup = C.ARM_GRP_MULTPRO
ARM_GRP_NEON ArmInsnGroup = C.ARM_GRP_NEON
ARM_GRP_T2EXTRACTPACK ArmInsnGroup = C.ARM_GRP_T2EXTRACTPACK
ARM_GRP_THUMB2DSP ArmInsnGroup = C.ARM_GRP_THUMB2DSP
ARM_GRP_TRUSTZONE ArmInsnGroup = C.ARM_GRP_TRUSTZONE
ARM_GRP_V4T ArmInsnGroup = C.ARM_GRP_V4T
ARM_GRP_V5T ArmInsnGroup = C.ARM_GRP_V5T
ARM_GRP_V5TE ArmInsnGroup = C.ARM_GRP_V5TE
ARM_GRP_V6 ArmInsnGroup = C.ARM_GRP_V6
ARM_GRP_V6T2 ArmInsnGroup = C.ARM_GRP_V6T2
ARM_GRP_V7 ArmInsnGroup = C.ARM_GRP_V7
ARM_GRP_V8 ArmInsnGroup = C.ARM_GRP_V8
ARM_GRP_VFP2 ArmInsnGroup = C.ARM_GRP_VFP2
ARM_GRP_VFP3 ArmInsnGroup = C.ARM_GRP_VFP3
ARM_GRP_VFP4 ArmInsnGroup = C.ARM_GRP_VFP4
ARM_GRP_ARM ArmInsnGroup = C.ARM_GRP_ARM
ARM_GRP_MCLASS ArmInsnGroup = C.ARM_GRP_MCLASS
ARM_GRP_NOTMCLASS ArmInsnGroup = C.ARM_GRP_NOTMCLASS
ARM_GRP_THUMB ArmInsnGroup = C.ARM_GRP_THUMB
ARM_GRP_THUMB1ONLY ArmInsnGroup = C.ARM_GRP_THUMB1ONLY
ARM_GRP_THUMB2 ArmInsnGroup = C.ARM_GRP_THUMB2
ARM_GRP_PREV8 ArmInsnGroup = C.ARM_GRP_PREV8
ARM_GRP_FPVMLX ArmInsnGroup = C.ARM_GRP_FPVMLX
ARM_GRP_MULOPS ArmInsnGroup = C.ARM_GRP_MULOPS
ARM_GRP_CRC ArmInsnGroup = C.ARM_GRP_CRC
ARM_GRP_DPVFP ArmInsnGroup = C.ARM_GRP_DPVFP
ARM_GRP_V6M ArmInsnGroup = C.ARM_GRP_V6M
ARM_GRP_VIRTUALIZATION ArmInsnGroup = C.ARM_GRP_VIRTUALIZATION
ARM_GRP_ENDING ArmInsnGroup = C.ARM_GRP_ENDING
)
type ArmMemBarrier C.enum_arm_mem_barrier
const (
ARM_MB_INVALID ArmMemBarrier = C.ARM_MB_INVALID
ARM_MB_RESERVED_0 ArmMemBarrier = C.ARM_MB_RESERVED_0
ARM_MB_OSHLD ArmMemBarrier = C.ARM_MB_OSHLD
ARM_MB_OSHST ArmMemBarrier = C.ARM_MB_OSHST
ARM_MB_OSH ArmMemBarrier = C.ARM_MB_OSH
ARM_MB_RESERVED_4 ArmMemBarrier = C.ARM_MB_RESERVED_4
ARM_MB_NSHLD ArmMemBarrier = C.ARM_MB_NSHLD
ARM_MB_NSHST ArmMemBarrier = C.ARM_MB_NSHST
ARM_MB_NSH ArmMemBarrier = C.ARM_MB_NSH
ARM_MB_RESERVED_8 ArmMemBarrier = C.ARM_MB_RESERVED_8
ARM_MB_ISHLD ArmMemBarrier = C.ARM_MB_ISHLD
ARM_MB_ISHST ArmMemBarrier = C.ARM_MB_ISHST
ARM_MB_ISH ArmMemBarrier = C.ARM_MB_ISH
ARM_MB_RESERVED_12 ArmMemBarrier = C.ARM_MB_RESERVED_12
ARM_MB_LD ArmMemBarrier = C.ARM_MB_LD
ARM_MB_ST ArmMemBarrier = C.ARM_MB_ST
ARM_MB_SY ArmMemBarrier = C.ARM_MB_SY
)
type ArmOpType C.enum_arm_op_type
const (
ARM_OP_INVALID ArmOpType = C.ARM_OP_INVALID
ARM_OP_REG ArmOpType = C.ARM_OP_REG
ARM_OP_IMM ArmOpType = C.ARM_OP_IMM
ARM_OP_MEM ArmOpType = C.ARM_OP_MEM
ARM_OP_FP ArmOpType = C.ARM_OP_FP
ARM_OP_CIMM ArmOpType = C.ARM_OP_CIMM
ARM_OP_PIMM ArmOpType = C.ARM_OP_PIMM
ARM_OP_SETEND ArmOpType = C.ARM_OP_SETEND
ARM_OP_SYSREG ArmOpType = C.ARM_OP_SYSREG
)
type ArmReg C.enum_arm_reg
const (
ARM_REG_INVALID ArmReg = C.ARM_REG_INVALID
ARM_REG_APSR ArmReg = C.ARM_REG_APSR
ARM_REG_APSR_NZCV ArmReg = C.ARM_REG_APSR_NZCV
ARM_REG_CPSR ArmReg = C.ARM_REG_CPSR
ARM_REG_FPEXC ArmReg = C.ARM_REG_FPEXC
ARM_REG_FPINST ArmReg = C.ARM_REG_FPINST
ARM_REG_FPSCR ArmReg = C.ARM_REG_FPSCR
ARM_REG_FPSCR_NZCV ArmReg = C.ARM_REG_FPSCR_NZCV
ARM_REG_FPSID ArmReg = C.ARM_REG_FPSID
ARM_REG_ITSTATE ArmReg = C.ARM_REG_ITSTATE
ARM_REG_LR ArmReg = C.ARM_REG_LR
ARM_REG_PC ArmReg = C.ARM_REG_PC
ARM_REG_SP ArmReg = C.ARM_REG_SP
ARM_REG_SPSR ArmReg = C.ARM_REG_SPSR
ARM_REG_D0 ArmReg = C.ARM_REG_D0
ARM_REG_D1 ArmReg = C.ARM_REG_D1
ARM_REG_D2 ArmReg = C.ARM_REG_D2
ARM_REG_D3 ArmReg = C.ARM_REG_D3
ARM_REG_D4 ArmReg = C.ARM_REG_D4
ARM_REG_D5 ArmReg = C.ARM_REG_D5
ARM_REG_D6 ArmReg = C.ARM_REG_D6
ARM_REG_D7 ArmReg = C.ARM_REG_D7
ARM_REG_D8 ArmReg = C.ARM_REG_D8
ARM_REG_D9 ArmReg = C.ARM_REG_D9
ARM_REG_D10 ArmReg = C.ARM_REG_D10
ARM_REG_D11 ArmReg = C.ARM_REG_D11
ARM_REG_D12 ArmReg = C.ARM_REG_D12
ARM_REG_D13 ArmReg = C.ARM_REG_D13
ARM_REG_D14 ArmReg = C.ARM_REG_D14
ARM_REG_D15 ArmReg = C.ARM_REG_D15
ARM_REG_D16 ArmReg = C.ARM_REG_D16
ARM_REG_D17 ArmReg = C.ARM_REG_D17
ARM_REG_D18 ArmReg = C.ARM_REG_D18
ARM_REG_D19 ArmReg = C.ARM_REG_D19
ARM_REG_D20 ArmReg = C.ARM_REG_D20
ARM_REG_D21 ArmReg = C.ARM_REG_D21
ARM_REG_D22 ArmReg = C.ARM_REG_D22
ARM_REG_D23 ArmReg = C.ARM_REG_D23
ARM_REG_D24 ArmReg = C.ARM_REG_D24
ARM_REG_D25 ArmReg = C.ARM_REG_D25
ARM_REG_D26 ArmReg = C.ARM_REG_D26
ARM_REG_D27 ArmReg = C.ARM_REG_D27
ARM_REG_D28 ArmReg = C.ARM_REG_D28
ARM_REG_D29 ArmReg = C.ARM_REG_D29
ARM_REG_D30 ArmReg = C.ARM_REG_D30
ARM_REG_D31 ArmReg = C.ARM_REG_D31
ARM_REG_FPINST2 ArmReg = C.ARM_REG_FPINST2
ARM_REG_MVFR0 ArmReg = C.ARM_REG_MVFR0
ARM_REG_MVFR1 ArmReg = C.ARM_REG_MVFR1
ARM_REG_MVFR2 ArmReg = C.ARM_REG_MVFR2
ARM_REG_Q0 ArmReg = C.ARM_REG_Q0
ARM_REG_Q1 ArmReg = C.ARM_REG_Q1
ARM_REG_Q2 ArmReg = C.ARM_REG_Q2
ARM_REG_Q3 ArmReg = C.ARM_REG_Q3
ARM_REG_Q4 ArmReg = C.ARM_REG_Q4
ARM_REG_Q5 ArmReg = C.ARM_REG_Q5
ARM_REG_Q6 ArmReg = C.ARM_REG_Q6
ARM_REG_Q7 ArmReg = C.ARM_REG_Q7
ARM_REG_Q8 ArmReg = C.ARM_REG_Q8
ARM_REG_Q9 ArmReg = C.ARM_REG_Q9
ARM_REG_Q10 ArmReg = C.ARM_REG_Q10
ARM_REG_Q11 ArmReg = C.ARM_REG_Q11
ARM_REG_Q12 ArmReg = C.ARM_REG_Q12
ARM_REG_Q13 ArmReg = C.ARM_REG_Q13
ARM_REG_Q14 ArmReg = C.ARM_REG_Q14
ARM_REG_Q15 ArmReg = C.ARM_REG_Q15
ARM_REG_R0 ArmReg = C.ARM_REG_R0
ARM_REG_R1 ArmReg = C.ARM_REG_R1
ARM_REG_R2 ArmReg = C.ARM_REG_R2
ARM_REG_R3 ArmReg = C.ARM_REG_R3
ARM_REG_R4 ArmReg = C.ARM_REG_R4
ARM_REG_R5 ArmReg = C.ARM_REG_R5
ARM_REG_R6 ArmReg = C.ARM_REG_R6
ARM_REG_R7 ArmReg = C.ARM_REG_R7
ARM_REG_R8 ArmReg = C.ARM_REG_R8
ARM_REG_R9 ArmReg = C.ARM_REG_R9
ARM_REG_R10 ArmReg = C.ARM_REG_R10
ARM_REG_R11 ArmReg = C.ARM_REG_R11
ARM_REG_R12 ArmReg = C.ARM_REG_R12
ARM_REG_S0 ArmReg = C.ARM_REG_S0
ARM_REG_S1 ArmReg = C.ARM_REG_S1
ARM_REG_S2 ArmReg = C.ARM_REG_S2
ARM_REG_S3 ArmReg = C.ARM_REG_S3
ARM_REG_S4 ArmReg = C.ARM_REG_S4
ARM_REG_S5 ArmReg = C.ARM_REG_S5
ARM_REG_S6 ArmReg = C.ARM_REG_S6
ARM_REG_S7 ArmReg = C.ARM_REG_S7
ARM_REG_S8 ArmReg = C.ARM_REG_S8
ARM_REG_S9 ArmReg = C.ARM_REG_S9
ARM_REG_S10 ArmReg = C.ARM_REG_S10
ARM_REG_S11 ArmReg = C.ARM_REG_S11
ARM_REG_S12 ArmReg = C.ARM_REG_S12
ARM_REG_S13 ArmReg = C.ARM_REG_S13
ARM_REG_S14 ArmReg = C.ARM_REG_S14
ARM_REG_S15 ArmReg = C.ARM_REG_S15
ARM_REG_S16 ArmReg = C.ARM_REG_S16
ARM_REG_S17 ArmReg = C.ARM_REG_S17
ARM_REG_S18 ArmReg = C.ARM_REG_S18
ARM_REG_S19 ArmReg = C.ARM_REG_S19
ARM_REG_S20 ArmReg = C.ARM_REG_S20
ARM_REG_S21 ArmReg = C.ARM_REG_S21
ARM_REG_S22 ArmReg = C.ARM_REG_S22
ARM_REG_S23 ArmReg = C.ARM_REG_S23
ARM_REG_S24 ArmReg = C.ARM_REG_S24
ARM_REG_S25 ArmReg = C.ARM_REG_S25
ARM_REG_S26 ArmReg = C.ARM_REG_S26
ARM_REG_S27 ArmReg = C.ARM_REG_S27
ARM_REG_S28 ArmReg = C.ARM_REG_S28
ARM_REG_S29 ArmReg = C.ARM_REG_S29
ARM_REG_S30 ArmReg = C.ARM_REG_S30
ARM_REG_S31 ArmReg = C.ARM_REG_S31
ARM_REG_ENDING ArmReg = C.ARM_REG_ENDING
ARM_REG_R13 ArmReg = C.ARM_REG_R13
ARM_REG_R14 ArmReg = C.ARM_REG_R14
ARM_REG_R15 ArmReg = C.ARM_REG_R15
ARM_REG_SB ArmReg = C.ARM_REG_SB
ARM_REG_SL ArmReg = C.ARM_REG_SL
ARM_REG_FP ArmReg = C.ARM_REG_FP
ARM_REG_IP ArmReg = C.ARM_REG_IP
)
type ArmSetendType C.enum_arm_setend_type
const (
ARM_SETEND_INVALID ArmSetendType = C.ARM_SETEND_INVALID
ARM_SETEND_BE ArmSetendType = C.ARM_SETEND_BE
ARM_SETEND_LE ArmSetendType = C.ARM_SETEND_LE
)
type ArmShifter C.enum_arm_shifter
const (
ARM_SFT_INVALID ArmShifter = C.ARM_SFT_INVALID
ARM_SFT_ASR ArmShifter = C.ARM_SFT_ASR
ARM_SFT_LSL ArmShifter = C.ARM_SFT_LSL
ARM_SFT_LSR ArmShifter = C.ARM_SFT_LSR
ARM_SFT_ROR ArmShifter = C.ARM_SFT_ROR
ARM_SFT_RRX ArmShifter = C.ARM_SFT_RRX
ARM_SFT_ASR_REG ArmShifter = C.ARM_SFT_ASR_REG
ARM_SFT_LSL_REG ArmShifter = C.ARM_SFT_LSL_REG
ARM_SFT_LSR_REG ArmShifter = C.ARM_SFT_LSR_REG
ARM_SFT_ROR_REG ArmShifter = C.ARM_SFT_ROR_REG
ARM_SFT_RRX_REG ArmShifter = C.ARM_SFT_RRX_REG
)
type ArmSysreg C.enum_arm_sysreg
const (
ARM_SYSREG_INVALID ArmSysreg = C.ARM_SYSREG_INVALID
ARM_SYSREG_SPSR_C ArmSysreg = C.ARM_SYSREG_SPSR_C
ARM_SYSREG_SPSR_X ArmSysreg = C.ARM_SYSREG_SPSR_X
ARM_SYSREG_SPSR_S ArmSysreg = C.ARM_SYSREG_SPSR_S
ARM_SYSREG_SPSR_F ArmSysreg = C.ARM_SYSREG_SPSR_F
ARM_SYSREG_CPSR_C ArmSysreg = C.ARM_SYSREG_CPSR_C
ARM_SYSREG_CPSR_X ArmSysreg = C.ARM_SYSREG_CPSR_X
ARM_SYSREG_CPSR_S ArmSysreg = C.ARM_SYSREG_CPSR_S
ARM_SYSREG_CPSR_F ArmSysreg = C.ARM_SYSREG_CPSR_F
ARM_SYSREG_APSR ArmSysreg = C.ARM_SYSREG_APSR
ARM_SYSREG_APSR_G ArmSysreg = C.ARM_SYSREG_APSR_G
ARM_SYSREG_APSR_NZCVQ ArmSysreg = C.ARM_SYSREG_APSR_NZCVQ
ARM_SYSREG_APSR_NZCVQG ArmSysreg = C.ARM_SYSREG_APSR_NZCVQG
ARM_SYSREG_IAPSR ArmSysreg = C.ARM_SYSREG_IAPSR
ARM_SYSREG_IAPSR_G ArmSysreg = C.ARM_SYSREG_IAPSR_G
ARM_SYSREG_IAPSR_NZCVQG ArmSysreg = C.ARM_SYSREG_IAPSR_NZCVQG
ARM_SYSREG_IAPSR_NZCVQ ArmSysreg = C.ARM_SYSREG_IAPSR_NZCVQ
ARM_SYSREG_EAPSR ArmSysreg = C.ARM_SYSREG_EAPSR
ARM_SYSREG_EAPSR_G ArmSysreg = C.ARM_SYSREG_EAPSR_G
ARM_SYSREG_EAPSR_NZCVQG ArmSysreg = C.ARM_SYSREG_EAPSR_NZCVQG
ARM_SYSREG_EAPSR_NZCVQ ArmSysreg = C.ARM_SYSREG_EAPSR_NZCVQ
ARM_SYSREG_XPSR ArmSysreg = C.ARM_SYSREG_XPSR
ARM_SYSREG_XPSR_G ArmSysreg = C.ARM_SYSREG_XPSR_G
ARM_SYSREG_XPSR_NZCVQG ArmSysreg = C.ARM_SYSREG_XPSR_NZCVQG
ARM_SYSREG_XPSR_NZCVQ ArmSysreg = C.ARM_SYSREG_XPSR_NZCVQ
ARM_SYSREG_IPSR ArmSysreg = C.ARM_SYSREG_IPSR
ARM_SYSREG_EPSR ArmSysreg = C.ARM_SYSREG_EPSR
ARM_SYSREG_IEPSR ArmSysreg = C.ARM_SYSREG_IEPSR
ARM_SYSREG_MSP ArmSysreg = C.ARM_SYSREG_MSP
ARM_SYSREG_PSP ArmSysreg = C.ARM_SYSREG_PSP
ARM_SYSREG_PRIMASK ArmSysreg = C.ARM_SYSREG_PRIMASK
ARM_SYSREG_BASEPRI ArmSysreg = C.ARM_SYSREG_BASEPRI
ARM_SYSREG_BASEPRI_MAX ArmSysreg = C.ARM_SYSREG_BASEPRI_MAX
ARM_SYSREG_FAULTMASK ArmSysreg = C.ARM_SYSREG_FAULTMASK
ARM_SYSREG_CONTROL ArmSysreg = C.ARM_SYSREG_CONTROL
ARM_SYSREG_MSPLIM ArmSysreg = C.ARM_SYSREG_MSPLIM
ARM_SYSREG_PSPLIM ArmSysreg = C.ARM_SYSREG_PSPLIM
ARM_SYSREG_MSP_NS ArmSysreg = C.ARM_SYSREG_MSP_NS
ARM_SYSREG_PSP_NS ArmSysreg = C.ARM_SYSREG_PSP_NS
ARM_SYSREG_MSPLIM_NS ArmSysreg = C.ARM_SYSREG_MSPLIM_NS
ARM_SYSREG_PSPLIM_NS ArmSysreg = C.ARM_SYSREG_PSPLIM_NS
ARM_SYSREG_PRIMASK_NS ArmSysreg = C.ARM_SYSREG_PRIMASK_NS
ARM_SYSREG_BASEPRI_NS ArmSysreg = C.ARM_SYSREG_BASEPRI_NS
ARM_SYSREG_FAULTMASK_NS ArmSysreg = C.ARM_SYSREG_FAULTMASK_NS
ARM_SYSREG_CONTROL_NS ArmSysreg = C.ARM_SYSREG_CONTROL_NS
ARM_SYSREG_SP_NS ArmSysreg = C.ARM_SYSREG_SP_NS
ARM_SYSREG_R8_USR ArmSysreg = C.ARM_SYSREG_R8_USR
ARM_SYSREG_R9_USR ArmSysreg = C.ARM_SYSREG_R9_USR
ARM_SYSREG_R10_USR ArmSysreg = C.ARM_SYSREG_R10_USR
ARM_SYSREG_R11_USR ArmSysreg = C.ARM_SYSREG_R11_USR
ARM_SYSREG_R12_USR ArmSysreg = C.ARM_SYSREG_R12_USR
ARM_SYSREG_SP_USR ArmSysreg = C.ARM_SYSREG_SP_USR
ARM_SYSREG_LR_USR ArmSysreg = C.ARM_SYSREG_LR_USR
ARM_SYSREG_R8_FIQ ArmSysreg = C.ARM_SYSREG_R8_FIQ
ARM_SYSREG_R9_FIQ ArmSysreg = C.ARM_SYSREG_R9_FIQ
ARM_SYSREG_R10_FIQ ArmSysreg = C.ARM_SYSREG_R10_FIQ
ARM_SYSREG_R11_FIQ ArmSysreg = C.ARM_SYSREG_R11_FIQ
ARM_SYSREG_R12_FIQ ArmSysreg = C.ARM_SYSREG_R12_FIQ
ARM_SYSREG_SP_FIQ ArmSysreg = C.ARM_SYSREG_SP_FIQ
ARM_SYSREG_LR_FIQ ArmSysreg = C.ARM_SYSREG_LR_FIQ
ARM_SYSREG_LR_IRQ ArmSysreg = C.ARM_SYSREG_LR_IRQ
ARM_SYSREG_SP_IRQ ArmSysreg = C.ARM_SYSREG_SP_IRQ
ARM_SYSREG_LR_SVC ArmSysreg = C.ARM_SYSREG_LR_SVC
ARM_SYSREG_SP_SVC ArmSysreg = C.ARM_SYSREG_SP_SVC
ARM_SYSREG_LR_ABT ArmSysreg = C.ARM_SYSREG_LR_ABT
ARM_SYSREG_SP_ABT ArmSysreg = C.ARM_SYSREG_SP_ABT
ARM_SYSREG_LR_UND ArmSysreg = C.ARM_SYSREG_LR_UND
ARM_SYSREG_SP_UND ArmSysreg = C.ARM_SYSREG_SP_UND
ARM_SYSREG_LR_MON ArmSysreg = C.ARM_SYSREG_LR_MON
ARM_SYSREG_SP_MON ArmSysreg = C.ARM_SYSREG_SP_MON
ARM_SYSREG_ELR_HYP ArmSysreg = C.ARM_SYSREG_ELR_HYP
ARM_SYSREG_SP_HYP ArmSysreg = C.ARM_SYSREG_SP_HYP
ARM_SYSREG_SPSR_FIQ ArmSysreg = C.ARM_SYSREG_SPSR_FIQ
ARM_SYSREG_SPSR_IRQ ArmSysreg = C.ARM_SYSREG_SPSR_IRQ
ARM_SYSREG_SPSR_SVC ArmSysreg = C.ARM_SYSREG_SPSR_SVC
ARM_SYSREG_SPSR_ABT ArmSysreg = C.ARM_SYSREG_SPSR_ABT
ARM_SYSREG_SPSR_UND ArmSysreg = C.ARM_SYSREG_SPSR_UND
ARM_SYSREG_SPSR_MON ArmSysreg = C.ARM_SYSREG_SPSR_MON
ARM_SYSREG_SPSR_HYP ArmSysreg = C.ARM_SYSREG_SPSR_HYP
)
type ArmVectordataType C.enum_arm_vectordata_type
const (
ARM_VECTORDATA_INVALID ArmVectordataType = C.ARM_VECTORDATA_INVALID
ARM_VECTORDATA_I8 ArmVectordataType = C.ARM_VECTORDATA_I8
ARM_VECTORDATA_I16 ArmVectordataType = C.ARM_VECTORDATA_I16
ARM_VECTORDATA_I32 ArmVectordataType = C.ARM_VECTORDATA_I32
ARM_VECTORDATA_I64 ArmVectordataType = C.ARM_VECTORDATA_I64
ARM_VECTORDATA_S8 ArmVectordataType = C.ARM_VECTORDATA_S8
ARM_VECTORDATA_S16 ArmVectordataType = C.ARM_VECTORDATA_S16
ARM_VECTORDATA_S32 ArmVectordataType = C.ARM_VECTORDATA_S32
ARM_VECTORDATA_S64 ArmVectordataType = C.ARM_VECTORDATA_S64
ARM_VECTORDATA_U8 ArmVectordataType = C.ARM_VECTORDATA_U8
ARM_VECTORDATA_U16 ArmVectordataType = C.ARM_VECTORDATA_U16
ARM_VECTORDATA_U32 ArmVectordataType = C.ARM_VECTORDATA_U32
ARM_VECTORDATA_U64 ArmVectordataType = C.ARM_VECTORDATA_U64
ARM_VECTORDATA_P8 ArmVectordataType = C.ARM_VECTORDATA_P8
ARM_VECTORDATA_F16 ArmVectordataType = C.ARM_VECTORDATA_F16
ARM_VECTORDATA_F32 ArmVectordataType = C.ARM_VECTORDATA_F32
ARM_VECTORDATA_F64 ArmVectordataType = C.ARM_VECTORDATA_F64
ARM_VECTORDATA_F16F64 ArmVectordataType = C.ARM_VECTORDATA_F16F64
ARM_VECTORDATA_F64F16 ArmVectordataType = C.ARM_VECTORDATA_F64F16
ARM_VECTORDATA_F32F16 ArmVectordataType = C.ARM_VECTORDATA_F32F16
ARM_VECTORDATA_F16F32 ArmVectordataType = C.ARM_VECTORDATA_F16F32
ARM_VECTORDATA_F64F32 ArmVectordataType = C.ARM_VECTORDATA_F64F32
ARM_VECTORDATA_F32F64 ArmVectordataType = C.ARM_VECTORDATA_F32F64
ARM_VECTORDATA_S32F32 ArmVectordataType = C.ARM_VECTORDATA_S32F32
ARM_VECTORDATA_U32F32 ArmVectordataType = C.ARM_VECTORDATA_U32F32
ARM_VECTORDATA_F32S32 ArmVectordataType = C.ARM_VECTORDATA_F32S32
ARM_VECTORDATA_F32U32 ArmVectordataType = C.ARM_VECTORDATA_F32U32
ARM_VECTORDATA_F64S16 ArmVectordataType = C.ARM_VECTORDATA_F64S16
ARM_VECTORDATA_F32S16 ArmVectordataType = C.ARM_VECTORDATA_F32S16
ARM_VECTORDATA_F64S32 ArmVectordataType = C.ARM_VECTORDATA_F64S32
ARM_VECTORDATA_S16F64 ArmVectordataType = C.ARM_VECTORDATA_S16F64
ARM_VECTORDATA_S16F32 ArmVectordataType = C.ARM_VECTORDATA_S16F32
ARM_VECTORDATA_S32F64 ArmVectordataType = C.ARM_VECTORDATA_S32F64
ARM_VECTORDATA_U16F64 ArmVectordataType = C.ARM_VECTORDATA_U16F64
ARM_VECTORDATA_U16F32 ArmVectordataType = C.ARM_VECTORDATA_U16F32
ARM_VECTORDATA_U32F64 ArmVectordataType = C.ARM_VECTORDATA_U32F64
ARM_VECTORDATA_F64U16 ArmVectordataType = C.ARM_VECTORDATA_F64U16
ARM_VECTORDATA_F32U16 ArmVectordataType = C.ARM_VECTORDATA_F32U16
ARM_VECTORDATA_F64U32 ArmVectordataType = C.ARM_VECTORDATA_F64U32
ARM_VECTORDATA_F16U16 ArmVectordataType = C.ARM_VECTORDATA_F16U16
ARM_VECTORDATA_U16F16 ArmVectordataType = C.ARM_VECTORDATA_U16F16
ARM_VECTORDATA_F16U32 ArmVectordataType = C.ARM_VECTORDATA_F16U32
ARM_VECTORDATA_U32F16 ArmVectordataType = C.ARM_VECTORDATA_U32F16
)
type ArmOpMem C.struct_arm_op_mem
type CsArm C.struct_cs_arm
type CsArmOp C.CsArmOp