From c18fbd4d541511a55a4f29326080bd3de463a5e9 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Thu, 28 Nov 2024 18:36:59 +0100 Subject: [PATCH] opt_dff: sigmap bits before looking up muxes --- passes/opt/opt_dff.cc | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 8539432c022..d033ddd5d3c 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -29,6 +29,7 @@ #include "passes/techmap/simplemap.h" #include #include +#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -95,6 +96,18 @@ struct OptDffWorker } + // If this bit sigmaps to a bit driven by a mux ouput bit that only drives this + // bit, returns that mux otherwise nullopt + std::optional mergeable_mux(SigBit bit) { + sigmap.apply(bit); + auto it = bit2mux.find(bit); + + if (it == bit2mux.end() || bitusers[bit] != 1) + return std::nullopt; + + return it->second; + } + State combine_const(State a, State b) { if (a == State::Sx && !opt.keepdc) return b; @@ -591,13 +604,12 @@ struct OptDffWorker State reset_val = State::Sx; if (ff.has_srst) reset_val = ff.val_srst[i]; - while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { - cell_int_t mbit = bit2mux.at(ff.sig_d[i]); - if (GetSize(mbit.first->getPort(ID::S)) != 1) + while (const auto mbit = mergeable_mux(ff.sig_d[i])) { + if (GetSize(mbit->first->getPort(ID::S)) != 1) break; - SigBit s = mbit.first->getPort(ID::S); - SigBit a = mbit.first->getPort(ID::A)[mbit.second]; - SigBit b = mbit.first->getPort(ID::B)[mbit.second]; + SigBit s = mbit->first->getPort(ID::S); + SigBit a = mbit->first->getPort(ID::A)[mbit->second]; + SigBit b = mbit->first->getPort(ID::B)[mbit->second]; // Workaround for funny memory WE pattern. if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1)) break; @@ -668,13 +680,12 @@ struct OptDffWorker for (int i = 0 ; i < ff.width; i++) { // First, eat up as many simple muxes as possible. ctrls_t enables; - while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) { - cell_int_t mbit = bit2mux.at(ff.sig_d[i]); - if (GetSize(mbit.first->getPort(ID::S)) != 1) + while (const auto mbit = mergeable_mux(ff.sig_d[i])) { + if (GetSize(mbit->first->getPort(ID::S)) != 1) break; - SigBit s = mbit.first->getPort(ID::S); - SigBit a = mbit.first->getPort(ID::A)[mbit.second]; - SigBit b = mbit.first->getPort(ID::B)[mbit.second]; + SigBit s = mbit->first->getPort(ID::S); + SigBit a = mbit->first->getPort(ID::A)[mbit->second]; + SigBit b = mbit->first->getPort(ID::B)[mbit->second]; if (a == ff.sig_q[i]) { enables.insert(ctrl_t(s, true)); ff.sig_d[i] = b;