WCH RVSWD protocol

Intro

RVSWD is the name of the proprietary two-wire debug interface on WCH's RISC-V MCU. Similar to ARM's SWD interface, RWSWD has two wires named SWDIO and SWCLK respectively, but the protocol is not compatible.

Basics

This protocol has some characteristics of I2C. Specifically:

• SWCLK and SWDIO are high when there's no transaction.
• SWDIO changing to low while SWCLK is high marks a START condition.
• SWDIO changing to high while SWCLK is high marks a STOP condition.
• SWDIO should change only when SWCLK is low during transaction.
• When SWCLK is high, a bit is interpreted as 1 if SWDIO is high, interpreted as 0 if SWDIO is low.

A transaction is always initiated by the host(WCH-Link). The protocol is point-to-point, thus there's no slave address. There's no ACK/NACK either.

Format

Type	START	Address	Data	Operation	Parity?	Address	Data	Status	Parity?	STOP
From	Host	Host	Host	Host	Host	Target	Target	Target	Target	Host
Length(bit)	-	7	32	2	1	7	32	2	1	-

Note:

1. All fields are MSB first.
2. Data field of read request sent from host is (always?) 0.

As one can see, this protocol basically exposes the dmi (0x11) register of DTM (Debug Transport Module) in a typical JTAG implementation.