Todo list

Unsupported yet：

1. Flash operations

Bugs/partial support:

1. Full/Real reset.
   Current reset has no effect at chip level (peripherals). WCH's RISC-V implementation is
   more like Cortex-M. Similar to AIRCR in ARM's NVIC, the system can be reset by writing
   to PFIC_CFGR, i.e mww 0xe000e048 0xbeef0080.
   However, once reset with this, the debug logic will also be reset. Since this is against
   the spec except for the DM and any logic required to access the DM., OpenOCD will be
   too surprised to see DM stop responding, and WCH-Link is too dumb to reconnect by itself
   (remember that WCH-Link also acts as a wrapper of the transport layer which appears to be
   some cJTAG-like custom protocol, and talks to DTM by itself), requiring the user to manually
   power-cycle WCH-Link.