From 7745bbec75429af5ec5741e024999069c9d4d875 Mon Sep 17 00:00:00 2001 From: Warren Toomey Date: Sun, 16 Dec 2018 16:58:14 +1000 Subject: [PATCH 1/4] Added files and blinky.core to support the ULX3S FPGA development board. --- blinky.core | 14 ++ ulx3s/ulx3s_empty.config | 439 +++++++++++++++++++++++++++++++++++++++ ulx3s/ulx3s_v20.lpf | 4 + 3 files changed, 457 insertions(+) create mode 100644 ulx3s/ulx3s_empty.config create mode 100644 ulx3s/ulx3s_v20.lpf diff --git a/blinky.core b/blinky.core index e54d1eb..bf15017 100644 --- a/blinky.core +++ b/blinky.core @@ -23,6 +23,11 @@ filesets: tinyfpga_bx: files: [tinyfpga_bx/pinout.pcf : {file_type : PCF}] + ulx3s: + files: + - ulx3s/ulx3s_empty.config : {file_type : user} + - ulx3s/ulx3s_v20.lpf : {file_type : LPF} + upduino2: files: - upduino2/blinky_upduino2.v : {file_type : verilogSource} @@ -77,6 +82,15 @@ targets: pnr: next toplevel : blinky + ulx3s: + default_tool : trellis + filesets : [rtl, proginfo, ulx3s] + parameters : [clk_freq_hz=25000000] + tools: + trellis: + nextpnr_options : [--45k --basecfg ../src/fusesoc_utils_blinky_0/ulx3s/ulx3s_empty.config --lpf ../src/fusesoc_utils_blinky_0/ulx3s/ulx3s_v20.lpf] + toplevel : blinky + upduino2: default_tool : icestorm filesets : [rtl, proginfo, upduino2] diff --git a/ulx3s/ulx3s_empty.config b/ulx3s/ulx3s_empty.config new file mode 100644 index 0000000..815e7f0 --- /dev/null +++ b/ulx3s/ulx3s_empty.config @@ -0,0 +1,439 @@ +.device LFE5U-45F + +.tile CIB_R10C3:PVT_COUNT2 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile CIB_R5C1:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + + +.tile CIB_R5C89:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + + +.tile CIB_R70C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + + +.tile CIB_R70C42:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C43:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C44:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C45:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C46:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C47:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C48:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C49:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C50:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C51:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C52:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C53:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + + +.tile CIB_R70C69:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C70:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C71:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C72:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C73:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C74:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C75:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C76:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C77:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C78:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C79:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + + +.tile CIB_R70C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + + +.tile CIB_R70C80:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + + +.tile CIB_R70C87:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + + +.tile MIB_R10C40:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 + + +.tile MIB_R10C41:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 + + +.tile MIB_R58C40:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 + + +.tile MIB_R58C41:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 + + +.tile MIB_R71C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile MIB_R71C3:BANKREF8 +unknown: F18B0 + diff --git a/ulx3s/ulx3s_v20.lpf b/ulx3s/ulx3s_v20.lpf new file mode 100644 index 0000000..79a2524 --- /dev/null +++ b/ulx3s/ulx3s_v20.lpf @@ -0,0 +1,4 @@ +LOCATE COMP "clk" SITE "G2"; +IOBUF PORT "clk" PULLMODE=NONE IO_TYPE=LVCMOS33; +LOCATE COMP "q" SITE "B2"; +IOBUF PORT "q" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; From 9ab1b8c7b0c8effea2614a74314d6ff5030d7fc9 Mon Sep 17 00:00:00 2001 From: Warren Toomey Date: Sun, 16 Dec 2018 17:21:06 +1000 Subject: [PATCH 2/4] Changed the locations of the ULX3S-specific files based on olofk's comments. --- blinky.core | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/blinky.core b/blinky.core index bf15017..8779d6d 100644 --- a/blinky.core +++ b/blinky.core @@ -25,8 +25,8 @@ filesets: ulx3s: files: - - ulx3s/ulx3s_empty.config : {file_type : user} - - ulx3s/ulx3s_v20.lpf : {file_type : LPF} + - ulx3s/ulx3s_empty.config : {file_type : user, copyto : ulx3s_empty.config} + - ulx3s/ulx3s_v20.lpf : {file_type : LPF, copyto : ulx3s_v20.lpf} upduino2: files: @@ -88,7 +88,7 @@ targets: parameters : [clk_freq_hz=25000000] tools: trellis: - nextpnr_options : [--45k --basecfg ../src/fusesoc_utils_blinky_0/ulx3s/ulx3s_empty.config --lpf ../src/fusesoc_utils_blinky_0/ulx3s/ulx3s_v20.lpf] + nextpnr_options : [--45k --basecfg ulx3s_empty.config --lpf ulx3s_v20.lpf] toplevel : blinky upduino2: From 17e705f3ac74d7ad3c1b401b6bbc13d52500bf72 Mon Sep 17 00:00:00 2001 From: Warren Toomey Date: Sun, 16 Dec 2018 17:33:09 +1000 Subject: [PATCH 3/4] Add the URL to the ULX3S FPGA development board --- README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README.md b/README.md index 0a98bb0..06fa988 100644 --- a/README.md +++ b/README.md @@ -62,3 +62,7 @@ https://www.avnet.com/shop/us/products/avnet-engineering-services/aes-s6mb-lx9-g ### Upduino 2 http://www.gnarlygrey.com/ + +### ULX3S + +https://github.com/emard/ulx3s From c1713d29a0a006cf39db900e260b1bb54e9b394f Mon Sep 17 00:00:00 2001 From: Warren Toomey Date: Sun, 16 Dec 2018 19:30:43 +1000 Subject: [PATCH 4/4] This is an initial attempt at adding Verilator simulation support to the blinky project. Things to add or fix: use the command-line info to set the VCD filename, add lint support, work out how to remove the verilator lint_off WIDTH comments in blinky.v. --- bench/blinky_tb.cpp | 40 ++++++++++++++++++ bench/testb.h | 99 +++++++++++++++++++++++++++++++++++++++++++++ blinky.core | 15 +++++++ blinky.v | 2 + 4 files changed, 156 insertions(+) create mode 100644 bench/blinky_tb.cpp create mode 100644 bench/testb.h diff --git a/bench/blinky_tb.cpp b/bench/blinky_tb.cpp new file mode 100644 index 0000000..0fdfff2 --- /dev/null +++ b/bench/blinky_tb.cpp @@ -0,0 +1,40 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "verilated.h" +#include "Vblinky.h" +#include "testb.h" + +int main(int argc, char **argv) { + Verilated::commandArgs(argc, argv); + TESTB *tb = new TESTB; + + // See if we have a +vcd=something command-line option. + // If so, create the trace.vcd file + const char *vcd = Verilated::commandArgsPlusMatch("vcd="); + if (vcd[0]) { + printf("Creating trace.vcd\n"); + tb->opentrace("trace.vcd"); + } + + // Run the simulation for 100_000 ticks + int old_q=0; + for (int i=0; i < 100000; i++) { + tb->tick(); + + // Print out if the q output has changed + if (tb->m_core->q != old_q) { + printf("LED: %d\n", tb->m_core->q); + + // and save the old q value for later comparison + old_q= tb->m_core->q; + } + } + + printf("Simulation complete\n"); +} diff --git a/bench/testb.h b/bench/testb.h new file mode 100644 index 0000000..ae542f5 --- /dev/null +++ b/bench/testb.h @@ -0,0 +1,99 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// Filename: testb.h +// +// Project: Verilog Tutorial Example file +// +// Purpose: A wrapper providing a common interface to a clocked FPGA core +// being exercised by Verilator. +// +// Creator: Dan Gisselquist, Ph.D. +// Gisselquist Technology, LLC +// +//////////////////////////////////////////////////////////////////////////////// +// +// Written and distributed by Gisselquist Technology, LLC +// +// This program is hereby granted to the public domain. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +// FITNESS FOR A PARTICULAR PURPOSE. +// +//////////////////////////////////////////////////////////////////////////////// +// +// +#ifndef TESTB_H +#define TESTB_H + +#include +#include +#include + +#define TBASSERT(TB,A) do { if (!(A)) { (TB).closetrace(); } assert(A); } while(0); + +template class TESTB { +public: + VA *m_core; + VerilatedVcdC* m_trace; + uint64_t m_tickcount; + + TESTB(void) : m_trace(NULL), m_tickcount(0l) { + m_core = new VA; + Verilated::traceEverOn(true); + m_core->clk = 0; + eval(); // Get our initial values set properly. + } + virtual ~TESTB(void) { + closetrace(); + delete m_core; + m_core = NULL; + } + + virtual void opentrace(const char *vcdname) { + if (!m_trace) { + m_trace = new VerilatedVcdC; + m_core->trace(m_trace, 99); + m_trace->open(vcdname); + } + } + + virtual void closetrace(void) { + if (m_trace) { + m_trace->close(); + delete m_trace; + m_trace = NULL; + } + } + + virtual void eval(void) { + m_core->eval(); + } + + virtual void tick(void) { + m_tickcount++; + + // Make sure we have our evaluations straight before the top + // of the clock. This is necessary since some of the + // connection modules may have made changes, for which some + // logic depends. This forces that logic to be recalculated + // before the top of the clock. + eval(); + if (m_trace) m_trace->dump((vluint64_t)(10*m_tickcount-2)); + m_core->clk = 1; + eval(); + if (m_trace) m_trace->dump((vluint64_t)(10*m_tickcount)); + m_core->clk = 0; + eval(); + if (m_trace) { + m_trace->dump((vluint64_t)(10*m_tickcount+5)); + m_trace->flush(); + } + } + + unsigned long tickcount(void) { + return m_tickcount; + } +}; + +#endif diff --git a/blinky.core b/blinky.core index 8779d6d..dc3f06e 100644 --- a/blinky.core +++ b/blinky.core @@ -33,6 +33,12 @@ filesets: - upduino2/blinky_upduino2.v : {file_type : verilogSource} - upduino2/pinout.pcf : {file_type : PCF} + verilator_tb: + files: + - bench/blinky_tb.cpp : {file_type : cppSource} + - bench/testb.h : {file_type : user} + + targets: default: filesets : [rtl] @@ -102,6 +108,15 @@ targets: pnr: next toplevel : blinky_upduino2 + verilator: + default_tool: verilator + filesets : [rtl, verilator_tb] + tools: + verilator: + verilator_options : [--trace] + parameters : [clk_freq_hz=10000] + toplevel : blinky + parameters: clk_freq_hz: datatype : int diff --git a/blinky.v b/blinky.v index 2a1c67d..96bb5f0 100644 --- a/blinky.v +++ b/blinky.v @@ -7,7 +7,9 @@ module blinky always @(posedge clk) begin count <= count + 1; +/* verilator lint_off WIDTH */ if (count == clk_freq_hz-1) begin +/* verilator lint_on WIDTH */ q <= !q; count <= 0; end