CrcGenerator.svg

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<title>CrcGenerator</title>
<desc>Block converted from VHDL to svg with entity-block.</desc>
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 >CrcGenerator</text>
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>
<text fill="#000000" fill-opacity="1" stroke="none" xml:space="preserve" x="23.6875" y="30" font-family="Ubuntu" font-size="10" font-weight="400" font-style="normal" 
 >en</text>
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>
<text fill="#008000" fill-opacity="1" stroke="none" xml:space="preserve" x="55" y="35" font-family="Ubuntu" font-size="8" font-weight="400" font-style="normal" 
 >Include byte in</text>
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 >std_logic</text>
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>
<text fill="#000000" fill-opacity="1" stroke="none" xml:space="preserve" x="20.875" y="52" font-family="Ubuntu" font-size="10" font-weight="400" font-style="normal" 
 >din</text>
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>
<text fill="#008000" fill-opacity="1" stroke="none" xml:space="preserve" x="55" y="57" font-family="Ubuntu" font-size="8" font-weight="400" font-style="normal" 
 >Input byte</text>
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>
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 >std_logic_vector (7 downto 0)</text>
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>
<text fill="#000000" fill-opacity="1" stroke="none" xml:space="preserve" x="0.875" y="96" font-family="Ubuntu" font-size="10" font-weight="400" font-style="normal" 
 >reset_n</text>
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>
<text fill="#008000" fill-opacity="1" stroke="none" xml:space="preserve" x="55" y="101" font-family="Ubuntu" font-size="8" font-weight="400" font-style="normal" 
 >asynchronous reset (active low)</text>
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 >std_logic</text>
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>
<text fill="#000000" fill-opacity="1" stroke="none" xml:space="preserve" x="4.64063" y="118" font-family="Ubuntu" font-size="10" font-weight="400" font-style="normal" 
 >sReset</text>
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>
<text fill="#008000" fill-opacity="1" stroke="none" xml:space="preserve" x="55" y="123" font-family="Ubuntu" font-size="8" font-weight="400" font-style="normal" 
 >synchronous reset to restart CRC</text>
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>
<text fill="#000080" fill-opacity="1" stroke="none" xml:space="preserve" x="55" y="113" font-family="Ubuntu" font-size="10" font-weight="400" font-style="normal" 
 >std_logic</text>
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>
<text fill="#000000" fill-opacity="1" stroke="none" xml:space="preserve" x="22.4219" y="162" font-family="Ubuntu" font-size="10" font-weight="400" font-style="normal" 
 >clk</text>
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>
<text fill="#008000" fill-opacity="1" stroke="none" xml:space="preserve" x="55" y="167" font-family="Ubuntu" font-size="8" font-weight="400" font-style="normal" 
 >125 MHz ethernet clock</text>
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<text fill="#000080" fill-opacity="1" stroke="none" xml:space="preserve" x="55" y="157" font-family="Ubuntu" font-size="10" font-weight="400" font-style="normal" 
 >std_logic</text>
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>
<text fill="#000000" fill-opacity="1" stroke="none" xml:space="preserve" x="389" y="30" font-family="Ubuntu" font-size="10" font-weight="400" font-style="normal" 
 >dv</text>
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<text fill="#008000" fill-opacity="1" stroke="none" xml:space="preserve" x="301.297" y="35" font-family="Ubuntu" font-size="8" font-weight="400" font-style="normal" 
 >CRC valid indicator</text>
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 >std_logic</text>
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 >dout</text>
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 >CRC output</text>
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 >std_logic_vector (31 downto 0)</text>
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 >REVERSEINPUT : std_logic := '1'</text>
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 >Reverse 8 bits in input byte</text>
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 >REVERSEOUTPUT : std_logic := '1'</text>
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 >Reverse 32 bits in CRC output</text>
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 >INITVAL : std_logic_vector(31 downto 0) := X&quot;FFFFFFFF&quot;</text>
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 >Initial value of the CRC when sReset</text>
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 >FINALXOR : std_logic_vector(31 downto 0) := X&quot;FFFFFFFF&quot;</text>
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 >Set to FFFFFFFF to invert CRC output</text>
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 >POLYNOMIAL : std_logic_vector(31 downto 0) := X&quot;04C11DB7&quot;</text>
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 >Generator polynomial is</text>
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