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Conflicts: logi-test/hw/logibone/ise/logibone_test.xise
2 parents 27239f4 + 5409f20 commit c1b6e67

24 files changed

+1557
-41
lines changed

‎logi-edu-test/hw/logipi/hdl/logi_edu_test.vhd

Lines changed: 22 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,8 @@ pll0 : clock_gen
156156
CLK_OUT1 => clk_100Mhz,
157157
CLK_OUT2 => clk_50Mhz,
158158
-- Status and control signals
159-
LOCKED => clock_locked);
159+
LOCKED => clock_locked
160+
);
160161

161162
gls_clk <= clk_100Mhz;
162163
vga_clk <= clk_50Mhz;
@@ -264,7 +265,7 @@ gpio0 : wishbone_gpio
264265
wbs_cycle => intercon_gpio0_wbm_cycle,
265266
--MAP GPIO TO IO PI TEST1-OUT TEST1-DIR EXPECT-PORT TEST1-REVERSE = INVERTED FROM TEST1
266267
gpio(7) =>PMOD4(7), --NES_DATA1 PMOD4(7) 0 0 1
267-
gpio(6) =>PMOD4(6), --PWM1 PMOD4(6) 0 0 1
268+
gpio(6) =>PMOD4(6), --PWM1 PMOD4(6) 0 0 1
268269
gpio(5) =>PMOD4(5), --PS2D_1 PMOD4(5) 0 0 1
269270
gpio(4) =>PMOD4(4), --PS2C_1 PMOD4(4) 1 1 0
270271
gpio(3) =>PMOD4(3), --NES_DAT2 PMOD4(3) 0 0 1
@@ -288,24 +289,24 @@ sseg0 : wishbone_7seg4x
288289
wbs_ack => intercon_sseg0_wbm_ack,
289290
wbs_cycle => intercon_sseg0_wbm_cycle,
290291

291-
sseg_edu_cathode_out => sseg_edu_cathode_out,
292-
sseg_edu_anode_out => sseg_edu_anode_out
292+
sseg_cathode_out => sseg_edu_cathode_out,
293+
sseg_anode_out => sseg_edu_anode_out
293294
);
294295

295-
PMOD2(4) <= sseg_edu_cathode_out(0); -- cathode 0
296-
PMOD2(0) <= sseg_edu_cathode_out(1); -- cathode 1
297-
PMOD2(2) <= sseg_edu_cathode_out(2); -- cathode 2
298-
PMOD2(3) <= sseg_edu_cathode_out(3); -- cathode 3
299-
PMOD2(1) <= sseg_edu_cathode_out(4); -- cathode 4
296+
PMOD2(5) <= sseg_edu_cathode_out(0); -- cathode 0
297+
PMOD2(1) <= sseg_edu_cathode_out(1); -- cathode 1
298+
PMOD3(0) <= sseg_edu_cathode_out(2); -- cathode 2
299+
PMOD3(1) <= sseg_edu_cathode_out(3); -- cathode 3
300+
PMOD2(2) <= sseg_edu_cathode_out(4); -- cathode 4
300301

301-
PMOD3(5) <= sseg_edu_anode_out(0); --A
302-
PMOD3(4) <= sseg_edu_anode_out(1); --B
303-
PMOD3(1) <= sseg_edu_anode_out(2); --C
304-
PMOD2(5) <= sseg_edu_anode_out(3); --D
305-
PMOD2(6) <= sseg_edu_anode_out(4); --E
306-
PMOD3(6) <= sseg_edu_anode_out(5); --F
307-
PMOD3(0) <= sseg_edu_anode_out(6); --G
308-
PMOD2(7) <= sseg_edu_anode_out(7); --DP
302+
PMOD3(6) <= sseg_edu_anode_out(0); --A
303+
PMOD3(5) <= sseg_edu_anode_out(1); --B
304+
PMOD3(3) <= sseg_edu_anode_out(2); --C
305+
PMOD2(6) <= sseg_edu_anode_out(3); --D
306+
PMOD2(7) <= sseg_edu_anode_out(4); --E
307+
PMOD3(7) <= sseg_edu_anode_out(5); --F
308+
PMOD3(2) <= sseg_edu_anode_out(6); --G
309+
PMOD3(4) <= sseg_edu_anode_out(7); --DP
309310

310311

311312
-- following code tests the audio out.
@@ -338,16 +339,16 @@ PMOD1(3) <= vga_hsync ;
338339
PMOD1(7) <= vga_vsync ;
339340
PMOD1(0) <= vga_red(2);
340341
PMOD1(4) <= vga_red(1);
341-
PMOD3(7) <= vga_red(0);
342+
PMOD2(4) <= vga_red(0);
342343
PMOD1(1) <= vga_green(2);
343344
PMOD1(5) <= vga_green(1);
344-
PMOD3(3) <= vga_green(0);
345+
PMOD2(3) <= vga_green(0);
345346
PMOD1(2) <= vga_blue(2);
346347
PMOD1(6) <= vga_blue(1);
347-
PMOD3(2) <= vga_blue(0);
348+
PMOD2(0) <= vga_blue(0);
348349

349350

350-
LED(0) <= sseg_edu_cathode_out(0);
351+
LED(0) <= sseg_edu_cathode_out(0);
351352
LED(1) <= PB(0) ;
352353

353354
end Behavioral;

‎logi-edu-test/hw/logipi/hdl/logipi_r1_1_edu.ucf

Lines changed: 104 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,104 @@
1+
##========================================================
2+
## Pin assignments
3+
## Logi-Pi - Pong Chu book compatible - (work in progress)
4+
## - Intended for use the the Logi-Pi and EDU expansion
5+
##========================================================
6+
7+
##========================================================
8+
NET "clk" TNM_NET = clk;
9+
TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
10+
11+
##========================================================
12+
## clock and reset
13+
##========================================================
14+
NET "clk" LOC = P85;
15+
16+
##========================================================
17+
## Buttons
18+
##========================================================
19+
NET "btn_n<0>" LOC = P102;
20+
NET "btn_n<1>" LOC = P101;
21+
#NET "reset_n" LOC = P101; #--reset needs to be moved around depending on application, use sw or button
22+
23+
##=========================================================
24+
### 2 slide switches
25+
##==========================================================
26+
NET "sw<0>" LOC = P99;
27+
NET "sw<1>" LOC = P100;
28+
29+
#========================================================
30+
# 2 discrete LEDs
31+
#========================================================
32+
NET "led<0>" LOC = P105 ;
33+
NET "led<1>" LOC = P104 ;
34+
35+
###========================================================
36+
### VGA outputs
37+
###========================================================
38+
NET "red<0>" LOC = P116 | DRIVE=24 | SLEW=FAST ; //!P2_7
39+
NET "red<1>" LOC = P88 | DRIVE=24 | SLEW=FAST ; //P1_7
40+
NET "red<2>" LOC = P5 | DRIVE=24 | SLEW=FAST ; //P1_1
41+
42+
NET "green<0>" LOC = P123 | DRIVE=24 | SLEW=FAST ; //!P2_4
43+
NET "green<1>" LOC = P92 | DRIVE=24 | SLEW=FAST ; //P1_8
44+
NET "green<2>" LOC = P2 | DRIVE=24 | SLEW=FAST ; //P1_2
45+
46+
NET "blue<0>" LOC = P124 | DRIVE=24 | SLEW=FAST ; //!P2_1
47+
NET "blue<1>" LOC = P93 | DRIVE=24 | SLEW=FAST ; //P1_9
48+
NET "blue<2>" LOC = P1 | DRIVE=24 | SLEW=FAST ; //P1_3
49+
50+
NET "vsync" LOC = P94 | DRIVE=24 | SLEW=FAST ; //P1_10
51+
NET "hsync" LOC = P16 | DRIVE=24 | SLEW=FAST ; //P1_4
52+
53+
54+
55+
##========================================================
56+
## NES controller pins
57+
##========================================================
58+
NET "nes_clk" LOC = P111 | IOSTANDARD = LVCMOS33; #PMOD4_2
59+
NET "nes_lat" LOC = P124 | IOSTANDARD = LVCMOS33; #PMOD4_3
60+
NET "nes1_dat" LOC = P133 | IOSTANDARD = LVCMOS33; #PMOD4_10
61+
NET "nes2_dat" LOC = P123 | IOSTANDARD = LVCMOS33; #PMOD4_4
62+
63+
##========================================================
64+
## PS2 port 1
65+
##========================================================
66+
NET "ps2c_1" LOC=P115; ##PMOD4-7
67+
NET "ps2d_1" LOC=P114; ##PMOD4-8
68+
69+
##========================================================
70+
## PS2 port 2
71+
##========================================================
72+
NET "ps2c_2" LOC=P124 ; ##PMOD3_3 #!PMOD2_1
73+
NET "ps2d_2" LOC=P116 ; ##PMOD3_10 #!PMOD2_7
74+
75+
# This controls segments from 0:3 right to left
76+
#========================================================
77+
# 4-digit time-multiplexed 7-segment LED display
78+
#========================================================
79+
# This is from 3-0 right to left
80+
# digit enable
81+
NET "an<3>" LOC = P144 ; #p3_2 !
82+
NET "an<2>" LOC = P142 ; #p3_1 !
83+
NET "an<1>" LOC = P15 ; #p2_2 !
84+
NET "an<0>" LOC = P14 ; #p2_8 !
85+
#NET "an_l" LOC = P141 ; #p2_2 !???
86+
87+
# This is wired low bit = a , etc. the book code is reversed order.
88+
# 7-segment led segments
89+
NET "sseg<0>" LOC = P118 ; # segment a p3_9
90+
NET "sseg<1>" LOC = P119 ; # segment b p3_8
91+
NET "sseg<2>" LOC = P137 ; # segment c p3_4
92+
NET "sseg<3>" LOC = P143 ; # segment d p2_9
93+
NET "sseg<4>" LOC = P140 ; # segment e p2_10
94+
NET "sseg<5>" LOC = P117 ; # segment f p3_10
95+
NET "sseg<6>" LOC = P138 ; # segment g p3_3
96+
NET "sseg<7>" LOC = P139 ; # decimal point p3_10
97+
98+
#========================================================
99+
# UART for Rpi
100+
# TX = FGPA TX = Host RX
101+
# RX = FPGA RX = Host TX
102+
#========================================================
103+
#NET "rx" LOC= "P83" | IOSTANDARD = LVTTL; #Pi output FPGA input #Shared with Arduino TX
104+
#NET "tx" LOC= "P82" | IOSTANDARD = LVTTL; #Pi input FPGA output #Shared with Arduino RX

‎logi-edu-test/hw/logipi/hdl/logipi_r1_5.ucf

Lines changed: 153 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,153 @@
1+
##############################################################################
2+
# Timing Constraints #
3+
##############################################################################
4+
5+
##### Grouping Constraints #####
6+
NET OSC_FPGA TNM_NET = clk50_grp;
7+
#NET DRAM_CLK TNM_NET = clk100_grp;
8+
NET SYS_SPI_SCK TNM_NET = clk32_grp;
9+
10+
##### Clock Period Constraints #####
11+
TIMESPEC TS_PER_CLK50 = PERIOD "clk50_grp" 20.0 ns ;
12+
#TIMESPEC TS_PER_CLK100 = PERIOD "clk100_grp" 10.0 ns;
13+
TIMESPEC TS_PER_CLK32 = PERIOD "clk32_grp" 20.0 ns;
14+
#PIN "sys_clocks_gen/clkout2_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
15+
NET "SYS_SPI_SCK" CLOCK_DEDICATED_ROUTE = FALSE;
16+
17+
##############################################################################
18+
# Pin LOC Constraints #
19+
##############################################################################
20+
NET "OSC_FPGA" LOC = "P85" | IOSTANDARD = LVTTL;
21+
22+
#Peripherals#############################################################
23+
NET "LED<0>" LOC = "P105" | IOSTANDARD = LVTTL; #SHARED WITH ARD_D6
24+
NET "LED<1>" LOC = "P104" | IOSTANDARD = LVTTL; #SHARED WITH ARD_D7
25+
NET "PB<0>" LOC = "P102" | IOSTANDARD = LVTTL;
26+
NET "PB<1>" LOC = "P101" | IOSTANDARD = LVTTL;
27+
#NET "SW<0>" LOC = "P99" | IOSTANDARD = LVTTL;
28+
#NET "SW<1>" LOC = "P100" | IOSTANDARD = LVTTL;
29+
30+
31+
##SATA###########################################################################
32+
#NET "SATA_D1_P" LOC = "P127" | IOSTANDARD = LVDS_33;
33+
#NET "SATA_D1_N" LOC = "P126" | IOSTANDARD = LVDS_33;
34+
#NET "SATA_D2_P" LOC = "P121" | IOSTANDARD = LVDS_33;
35+
#NET "SATA_D2_N" LOC = "P120" | IOSTANDARD = LVDS_33;
36+
#
37+
##SDRAM#########################################################################
38+
#NET "SDRAM_CKE" LOC = "P48" | IOSTANDARD = LVTTL ;
39+
#NET "SDRAM_CLK" LOC = "P50" | IOSTANDARD = LVTTL | SLEW = FAST ;
40+
#NET "SDRAM_nCAS" LOC = "P7" | IOSTANDARD = LVTTL ;
41+
#NET "SDRAM_nRAS" LOC = "P6" | IOSTANDARD = LVTTL ;
42+
#NET "SDRAM_nWE" LOC = "P8" | IOSTANDARD = LVTTL ;
43+
##NET "DRAM_CS_N" #CS IS PULLED LOW TO SAVE ON PIN COUNT - Can be pulled high with solder jumper on bottom of board
44+
#NET "SDRAM_BA<0>" LOC = "P26" | IOSTANDARD = LVTTL ;
45+
#NET "SDRAM_BA<1>" LOC = "P27" | IOSTANDARD = LVTTL ;
46+
#NET "SDRAM_DQM<0>" LOC = "P9" | IOSTANDARD = LVTTL ;
47+
#NET "SDRAM_DQM<1>" LOC = "P67" | IOSTANDARD = LVTTL ;
48+
#NET "SDRAM_ADDR<0>" LOC = "P30" | IOSTANDARD = LVTTL ;
49+
#NET "SDRAM_ADDR<1>" LOC = "P32" | IOSTANDARD = LVTTL ;
50+
#NET "SDRAM_ADDR<2>" LOC = "P33" | IOSTANDARD = LVTTL ;
51+
#NET "SDRAM_ADDR<3>" LOC = "P34" | IOSTANDARD = LVTTL ;
52+
#NET "SDRAM_ADDR<4>" LOC = "P35" | IOSTANDARD = LVTTL ;
53+
#NET "SDRAM_ADDR<5>" LOC = "P40" | IOSTANDARD = LVTTL ;
54+
#NET "SDRAM_ADDR<6>" LOC = "P41" | IOSTANDARD = LVTTL ;
55+
#NET "SDRAM_ADDR<7>" LOC = "P43" | IOSTANDARD = LVTTL ;
56+
#NET "SDRAM_ADDR<8>" LOC = "P44" | IOSTANDARD = LVTTL ;
57+
#NET "SDRAM_ADDR<9>" LOC = "P45" | IOSTANDARD = LVTTL ;
58+
#NET "SDRAM_ADDR<10>" LOC = "P29" | IOSTANDARD = LVTTL ;
59+
#NET "SDRAM_ADDR<11>" LOC = "P46" | IOSTANDARD = LVTTL ;
60+
#NET "SDRAM_ADDR<12>" LOC = "P47" | IOSTANDARD = LVTTL ;
61+
#NET "SDRAM_DQ<0>" LOC = "P24" | IOSTANDARD = LVTTL ;
62+
#NET "SDRAM_DQ<1>" LOC = "P23" | IOSTANDARD = LVTTL ;
63+
#NET "SDRAM_DQ<2>" LOC = "P22" | IOSTANDARD = LVTTL ;
64+
#NET "SDRAM_DQ<3>" LOC = "P21" | IOSTANDARD = LVTTL ;
65+
#NET "SDRAM_DQ<4>" LOC = "P17" | IOSTANDARD = LVTTL ;
66+
#NET "SDRAM_DQ<5>" LOC = "P12" | IOSTANDARD = LVTTL ;
67+
#NET "SDRAM_DQ<6>" LOC = "P11" | IOSTANDARD = LVTTL ;
68+
#NET "SDRAM_DQ<7>" LOC = "P10" | IOSTANDARD = LVTTL ;
69+
#NET "SDRAM_DQ<8>" LOC = "P66" | IOSTANDARD = LVTTL ;
70+
#NET "SDRAM_DQ<9>" LOC = "P62" | IOSTANDARD = LVTTL ;
71+
#NET "SDRAM_DQ<10>" LOC = "P61" | IOSTANDARD = LVTTL ;
72+
#NET "SDRAM_DQ<11>" LOC = "P59" | IOSTANDARD = LVTTL ;
73+
#NET "SDRAM_DQ<12>" LOC = "P58" | IOSTANDARD = LVTTL ;
74+
#NET "SDRAM_DQ<13>" LOC = "P57" | IOSTANDARD = LVTTL ;
75+
#NET "SDRAM_DQ<14>" LOC = "P56" | IOSTANDARD = LVTTL ;
76+
#NET "SDRAM_DQ<15>" LOC = "P55" | IOSTANDARD = LVTTL ;
77+
78+
#PMOD1#############################################################################
79+
NET "PMOD1<0>" LOC = "P5" | IOSTANDARD = LVTTL; #VGA_R2
80+
NET "PMOD1<1>" LOC = "P2" | IOSTANDARD = LVTTL; #VGA_G2
81+
NET "PMOD1<2>" LOC = "P1" | IOSTANDARD = LVTTL; #VGA_B2
82+
NET "PMOD1<3>" LOC = "P16" | IOSTANDARD = LVTTL; #VGA_HS
83+
NET "PMOD1<4>" LOC = "P88" | IOSTANDARD = LVTTL; #VGA_R1
84+
NET "PMOD1<5>" LOC = "P92" | IOSTANDARD = LVTTL; #VGA_G1
85+
NET "PMOD1<6>" LOC = "P93" | IOSTANDARD = LVTTL; #VGA_B1
86+
NET "PMOD1<7>" LOC = "P94" | IOSTANDARD = LVTTL; #VGA_VS
87+
#PMOD2#############################################################################
88+
NET "PMOD2<0>" LOC = "P142" | IOSTANDARD = LVTTL; #VGA_B0
89+
NET "PMOD2<1>" LOC = "P141" | IOSTANDARD = LVTTL; #SSEG_A2
90+
NET "PMOD2<2>" LOC = "P15" | IOSTANDARD = LVTTL; #SSEG_L
91+
NET "PMOD2<3>" LOC = "P14" | IOSTANDARD = LVTTL; #VGA_G0
92+
NET "PMOD2<4>" LOC = "P144" | IOSTANDARD = LVTTL; #VGA_R0
93+
NET "PMOD2<5>" LOC = "P143" | IOSTANDARD = LVTTL; #SSEG_A1
94+
NET "PMOD2<6>" LOC = "P140" | IOSTANDARD = LVTTL; #SSEG_D
95+
NET "PMOD2<7>" LOC = "P139" | IOSTANDARD = LVTTL; #SSEG_E
96+
#PMOD3#############################################################################
97+
NET "PMOD3<0>" LOC = "P138" | IOSTANDARD = LVTTL; #SSEG_A3
98+
NET "PMOD3<1>" LOC = "P137" | IOSTANDARD = LVTTL; #SSEG_A4
99+
NET "PMOD3<2>" LOC = "P124" | IOSTANDARD = LVTTL; #SSEG_G
100+
NET "PMOD3<3>" LOC = "P123" | IOSTANDARD = LVTTL; #SSEG_C
101+
NET "PMOD3<4>" LOC = "P119" | IOSTANDARD = LVTTL; #SSEG_DP
102+
NET "PMOD3<5>" LOC = "P118" | IOSTANDARD = LVTTL; #SSEG_B
103+
NET "PMOD3<6>" LOC = "P117" | IOSTANDARD = LVTTL; #SSEG_A
104+
NET "PMOD3<7>" LOC = "P116" | IOSTANDARD = LVTTL; #SSEG_F
105+
#PMOD4#############################################################################
106+
NET "PMOD4<0>" LOC = "P112" | IOSTANDARD = LVTTL; #PWM2
107+
NET "PMOD4<1>" LOC = "P111" | IOSTANDARD = LVTTL; #NES_CLK
108+
NET "PMOD4<2>" LOC = "P132" | IOSTANDARD = LVTTL; #NES_LAT
109+
NET "PMOD4<3>" LOC = "P131" | IOSTANDARD = LVTTL; #NES2_DAT
110+
NET "PMOD4<4>" LOC = "P115" | IOSTANDARD = LVTTL; #PS2_1_CLK
111+
NET "PMOD4<5>" LOC = "P114" | IOSTANDARD = LVTTL; #PS2_1_DAT
112+
NET "PMOD4<6>" LOC = "P134" | IOSTANDARD = LVTTL; #PWM1
113+
NET "PMOD4<7>" LOC = "P133" | IOSTANDARD = LVTTL; #NES1_DAT
114+
115+
#PMOD4 LVDS CONSTRAINTS#############################################################
116+
#NET "P4_1_LVDS3_P" LOC = "P112" | IOSTANDARD = LVDS_33;
117+
#NET "P4_2_LVDS3_N" LOC = "P111" | IOSTANDARD = LVDS_33;
118+
#NET "P4_3_LVDS1_P" LOC = "P132" | IOSTANDARD = LVDS_33;
119+
#NET "P4_4_LVDS1_N" LOC = "P131" | IOSTANDARD = LVDS_33;
120+
#NET "P4_7_LVDS4_P" LOC = "P115" | IOSTANDARD = LVDS_33;
121+
#NET "P4_8_LVDS4_N" LOC = "P114" | IOSTANDARD = LVDS_33;
122+
#NET "P4_9_LVDS2_P" LOC = "P134" | IOSTANDARD = LVDS_33;
123+
#NET "P4_10_LVDS2_N" LOC = "P133" | IOSTANDARD = LVDS_33;
124+
125+
#RASPBERRY-PI CONNECTOR###############################################################
126+
NET "SYS_SPI_MOSI" LOC = "P80" | IOSTANDARD = LVTTL; #Shared - Used to clk bitstream data to fpga / ARduino MOSI
127+
NET "SYS_SPI_MISO" LOC = "P75" | IOSTANDARD = LVTTL;
128+
NET "SYS_SPI_SCK" LOC = "P78" | IOSTANDARD = LVTTL; #Shared - Used to clk bitstream data to fpga / ARduino SCK
129+
NET "RP_SPI_CE0N" LOC = "P79" | IOSTANDARD = LVTTL;
130+
#!##NET "RP_SPI_CE1N" LOC = "P78" | IOSTANDARD = LVTTL;
131+
#NET "SYS_SDA" LOC = "P98" | IOSTANDARD = LVTTL; #Shared with Arduino SDA
132+
#NET "SYS_SCL" LOC = "P97" | IOSTANDARD = LVTTL; #Shared with Arduino SCL
133+
#UART FROM RASPBERRY PI - As labelled in the Rpi (master) schematic
134+
#NET "SYS_TX" LOC= "P83" | IOSTANDARD = LVTTL; #Pi output FPGA input #Shared with Arduino TX
135+
#NET "SYS_RX" LOC= "P82" | IOSTANDARD = LVTTL; #Pi input FPGA output #Shared with Arduino RX
136+
#NET "RP_GPIO_GCLK" LOC = "P95" | IOSTANDARD = LVTTL;
137+
#NET "RP_GPIO_GEN2" LOC = "P81" | IOSTANDARD = LVTTL;
138+
#NET "RP_GPIO_GEN3" LOC = "P80" | IOSTANDARD = LVTTL;
139+
140+
#ARDUINO HEADERS########################################################################
141+
#SYS_SCL #Shared with RPI i2c
142+
#SYS_SDA #Shared with RPI i2c
143+
#NET "ARD_SCK" LOC= "P84" | IOSTANDARD = LVTTL; #D13
144+
#NET "ARD_MISO" LOC= "P87" | IOSTANDARD = LVTTL; #D12
145+
#NET "ARD_MOSI" LOC= "P51" | IOSTANDARD = LVTTL; `#D11
146+
#NET "ARD_SS" LOC= "P74" | IOSTANDARD = LVTTL; #D10
147+
#NET "ARD_D9_FLSH_DI" LOC= "P64" | IOSTANDARD = LVTTL; #D9
148+
#NET "ARD_D8_FLSH_CS" LOC= "P38" | IOSTANDARD = LVTTL; #D8
149+
150+
151+
152+
153+

‎logi-edu-test/hw/logipi/ise/ipcore_dir/clock_gen.xise

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,10 +9,10 @@
99
<!-- along with the project source files, is sufficient to open and -->
1010
<!-- implement in ISE Project Navigator. -->
1111
<!-- -->
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<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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</header>
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<version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
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<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="clock_gen/example_design/clock_gen_exdes.ucf" xil_pn:type="FILE_UCF"/>

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