diff --git a/logi-edu-test/hw/logipi/hdl/logi_edu_test.vhd b/logi-edu-test/hw/logipi/hdl/logi_edu_test.vhd
index 5c4bfa34..852e96c0 100644
--- a/logi-edu-test/hw/logipi/hdl/logi_edu_test.vhd
+++ b/logi-edu-test/hw/logipi/hdl/logi_edu_test.vhd
@@ -156,7 +156,8 @@ pll0 : clock_gen
CLK_OUT1 => clk_100Mhz,
CLK_OUT2 => clk_50Mhz,
-- Status and control signals
- LOCKED => clock_locked);
+ LOCKED => clock_locked
+ );
gls_clk <= clk_100Mhz;
vga_clk <= clk_50Mhz;
@@ -264,7 +265,7 @@ gpio0 : wishbone_gpio
wbs_cycle => intercon_gpio0_wbm_cycle,
--MAP GPIO TO IO PI TEST1-OUT TEST1-DIR EXPECT-PORT TEST1-REVERSE = INVERTED FROM TEST1
gpio(7) =>PMOD4(7), --NES_DATA1 PMOD4(7) 0 0 1
- gpio(6) =>PMOD4(6), --PWM1 PMOD4(6) 0 0 1
+ gpio(6) =>PMOD4(6), --PWM1 PMOD4(6) 0 0 1
gpio(5) =>PMOD4(5), --PS2D_1 PMOD4(5) 0 0 1
gpio(4) =>PMOD4(4), --PS2C_1 PMOD4(4) 1 1 0
gpio(3) =>PMOD4(3), --NES_DAT2 PMOD4(3) 0 0 1
@@ -288,24 +289,24 @@ sseg0 : wishbone_7seg4x
wbs_ack => intercon_sseg0_wbm_ack,
wbs_cycle => intercon_sseg0_wbm_cycle,
- sseg_edu_cathode_out => sseg_edu_cathode_out,
- sseg_edu_anode_out => sseg_edu_anode_out
+ sseg_cathode_out => sseg_edu_cathode_out,
+ sseg_anode_out => sseg_edu_anode_out
);
- PMOD2(4) <= sseg_edu_cathode_out(0); -- cathode 0
- PMOD2(0) <= sseg_edu_cathode_out(1); -- cathode 1
- PMOD2(2) <= sseg_edu_cathode_out(2); -- cathode 2
- PMOD2(3) <= sseg_edu_cathode_out(3); -- cathode 3
- PMOD2(1) <= sseg_edu_cathode_out(4); -- cathode 4
+ PMOD2(5) <= sseg_edu_cathode_out(0); -- cathode 0
+ PMOD2(1) <= sseg_edu_cathode_out(1); -- cathode 1
+ PMOD3(0) <= sseg_edu_cathode_out(2); -- cathode 2
+ PMOD3(1) <= sseg_edu_cathode_out(3); -- cathode 3
+ PMOD2(2) <= sseg_edu_cathode_out(4); -- cathode 4
- PMOD3(5) <= sseg_edu_anode_out(0); --A
- PMOD3(4) <= sseg_edu_anode_out(1); --B
- PMOD3(1) <= sseg_edu_anode_out(2); --C
- PMOD2(5) <= sseg_edu_anode_out(3); --D
- PMOD2(6) <= sseg_edu_anode_out(4); --E
- PMOD3(6) <= sseg_edu_anode_out(5); --F
- PMOD3(0) <= sseg_edu_anode_out(6); --G
- PMOD2(7) <= sseg_edu_anode_out(7); --DP
+ PMOD3(6) <= sseg_edu_anode_out(0); --A
+ PMOD3(5) <= sseg_edu_anode_out(1); --B
+ PMOD3(3) <= sseg_edu_anode_out(2); --C
+ PMOD2(6) <= sseg_edu_anode_out(3); --D
+ PMOD2(7) <= sseg_edu_anode_out(4); --E
+ PMOD3(7) <= sseg_edu_anode_out(5); --F
+ PMOD3(2) <= sseg_edu_anode_out(6); --G
+ PMOD3(4) <= sseg_edu_anode_out(7); --DP
-- following code tests the audio out.
@@ -338,16 +339,16 @@ PMOD1(3) <= vga_hsync ;
PMOD1(7) <= vga_vsync ;
PMOD1(0) <= vga_red(2);
PMOD1(4) <= vga_red(1);
-PMOD3(7) <= vga_red(0);
+PMOD2(4) <= vga_red(0);
PMOD1(1) <= vga_green(2);
PMOD1(5) <= vga_green(1);
-PMOD3(3) <= vga_green(0);
+PMOD2(3) <= vga_green(0);
PMOD1(2) <= vga_blue(2);
PMOD1(6) <= vga_blue(1);
-PMOD3(2) <= vga_blue(0);
+PMOD2(0) <= vga_blue(0);
-LED(0) <= sseg_edu_cathode_out(0);
+LED(0) <= sseg_edu_cathode_out(0);
LED(1) <= PB(0) ;
end Behavioral;
diff --git a/logi-edu-test/hw/logipi/hdl/logipi_r1_1_edu.ucf b/logi-edu-test/hw/logipi/hdl/logipi_r1_1_edu.ucf
new file mode 100644
index 00000000..8309846f
--- /dev/null
+++ b/logi-edu-test/hw/logipi/hdl/logipi_r1_1_edu.ucf
@@ -0,0 +1,104 @@
+##========================================================
+## Pin assignments
+## Logi-Pi - Pong Chu book compatible - (work in progress)
+## - Intended for use the the Logi-Pi and EDU expansion
+##========================================================
+
+##========================================================
+NET "clk" TNM_NET = clk;
+TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
+
+##========================================================
+## clock and reset
+##========================================================
+NET "clk" LOC = P85;
+
+##========================================================
+## Buttons
+##========================================================
+NET "btn_n<0>" LOC = P102;
+NET "btn_n<1>" LOC = P101;
+#NET "reset_n" LOC = P101; #--reset needs to be moved around depending on application, use sw or button
+
+##=========================================================
+### 2 slide switches
+##==========================================================
+NET "sw<0>" LOC = P99;
+NET "sw<1>" LOC = P100;
+
+#========================================================
+# 2 discrete LEDs
+#========================================================
+NET "led<0>" LOC = P105 ;
+NET "led<1>" LOC = P104 ;
+
+###========================================================
+### VGA outputs
+###========================================================
+NET "red<0>" LOC = P116 | DRIVE=24 | SLEW=FAST ; //!P2_7
+NET "red<1>" LOC = P88 | DRIVE=24 | SLEW=FAST ; //P1_7
+NET "red<2>" LOC = P5 | DRIVE=24 | SLEW=FAST ; //P1_1
+
+NET "green<0>" LOC = P123 | DRIVE=24 | SLEW=FAST ; //!P2_4
+NET "green<1>" LOC = P92 | DRIVE=24 | SLEW=FAST ; //P1_8
+NET "green<2>" LOC = P2 | DRIVE=24 | SLEW=FAST ; //P1_2
+
+NET "blue<0>" LOC = P124 | DRIVE=24 | SLEW=FAST ; //!P2_1
+NET "blue<1>" LOC = P93 | DRIVE=24 | SLEW=FAST ; //P1_9
+NET "blue<2>" LOC = P1 | DRIVE=24 | SLEW=FAST ; //P1_3
+
+NET "vsync" LOC = P94 | DRIVE=24 | SLEW=FAST ; //P1_10
+NET "hsync" LOC = P16 | DRIVE=24 | SLEW=FAST ; //P1_4
+
+
+
+##========================================================
+## NES controller pins
+##========================================================
+NET "nes_clk" LOC = P111 | IOSTANDARD = LVCMOS33; #PMOD4_2
+NET "nes_lat" LOC = P124 | IOSTANDARD = LVCMOS33; #PMOD4_3
+NET "nes1_dat" LOC = P133 | IOSTANDARD = LVCMOS33; #PMOD4_10
+NET "nes2_dat" LOC = P123 | IOSTANDARD = LVCMOS33; #PMOD4_4
+
+##========================================================
+## PS2 port 1
+##========================================================
+NET "ps2c_1" LOC=P115; ##PMOD4-7
+NET "ps2d_1" LOC=P114; ##PMOD4-8
+
+##========================================================
+## PS2 port 2
+##========================================================
+NET "ps2c_2" LOC=P124 ; ##PMOD3_3 #!PMOD2_1
+NET "ps2d_2" LOC=P116 ; ##PMOD3_10 #!PMOD2_7
+
+# This controls segments from 0:3 right to left
+#========================================================
+# 4-digit time-multiplexed 7-segment LED display
+#========================================================
+# This is from 3-0 right to left
+# digit enable
+NET "an<3>" LOC = P144 ; #p3_2 !
+NET "an<2>" LOC = P142 ; #p3_1 !
+NET "an<1>" LOC = P15 ; #p2_2 !
+NET "an<0>" LOC = P14 ; #p2_8 !
+#NET "an_l" LOC = P141 ; #p2_2 !???
+
+# This is wired low bit = a , etc. the book code is reversed order.
+# 7-segment led segments
+NET "sseg<0>" LOC = P118 ; # segment a p3_9
+NET "sseg<1>" LOC = P119 ; # segment b p3_8
+NET "sseg<2>" LOC = P137 ; # segment c p3_4
+NET "sseg<3>" LOC = P143 ; # segment d p2_9
+NET "sseg<4>" LOC = P140 ; # segment e p2_10
+NET "sseg<5>" LOC = P117 ; # segment f p3_10
+NET "sseg<6>" LOC = P138 ; # segment g p3_3
+NET "sseg<7>" LOC = P139 ; # decimal point p3_10
+
+#========================================================
+# UART for Rpi
+# TX = FGPA TX = Host RX
+# RX = FPGA RX = Host TX
+#========================================================
+#NET "rx" LOC= "P83" | IOSTANDARD = LVTTL; #Pi output FPGA input #Shared with Arduino TX
+#NET "tx" LOC= "P82" | IOSTANDARD = LVTTL; #Pi input FPGA output #Shared with Arduino RX
diff --git a/logi-edu-test/hw/logipi/hdl/logipi_r1_5.ucf b/logi-edu-test/hw/logipi/hdl/logipi_r1_5.ucf
new file mode 100644
index 00000000..75baaab0
--- /dev/null
+++ b/logi-edu-test/hw/logipi/hdl/logipi_r1_5.ucf
@@ -0,0 +1,153 @@
+##############################################################################
+# Timing Constraints #
+##############################################################################
+
+##### Grouping Constraints #####
+NET OSC_FPGA TNM_NET = clk50_grp;
+#NET DRAM_CLK TNM_NET = clk100_grp;
+NET SYS_SPI_SCK TNM_NET = clk32_grp;
+
+##### Clock Period Constraints #####
+TIMESPEC TS_PER_CLK50 = PERIOD "clk50_grp" 20.0 ns ;
+#TIMESPEC TS_PER_CLK100 = PERIOD "clk100_grp" 10.0 ns;
+TIMESPEC TS_PER_CLK32 = PERIOD "clk32_grp" 20.0 ns;
+#PIN "sys_clocks_gen/clkout2_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
+NET "SYS_SPI_SCK" CLOCK_DEDICATED_ROUTE = FALSE;
+
+##############################################################################
+# Pin LOC Constraints #
+##############################################################################
+NET "OSC_FPGA" LOC = "P85" | IOSTANDARD = LVTTL;
+
+#Peripherals#############################################################
+NET "LED<0>" LOC = "P105" | IOSTANDARD = LVTTL; #SHARED WITH ARD_D6
+NET "LED<1>" LOC = "P104" | IOSTANDARD = LVTTL; #SHARED WITH ARD_D7
+NET "PB<0>" LOC = "P102" | IOSTANDARD = LVTTL;
+NET "PB<1>" LOC = "P101" | IOSTANDARD = LVTTL;
+#NET "SW<0>" LOC = "P99" | IOSTANDARD = LVTTL;
+#NET "SW<1>" LOC = "P100" | IOSTANDARD = LVTTL;
+
+
+##SATA###########################################################################
+#NET "SATA_D1_P" LOC = "P127" | IOSTANDARD = LVDS_33;
+#NET "SATA_D1_N" LOC = "P126" | IOSTANDARD = LVDS_33;
+#NET "SATA_D2_P" LOC = "P121" | IOSTANDARD = LVDS_33;
+#NET "SATA_D2_N" LOC = "P120" | IOSTANDARD = LVDS_33;
+#
+##SDRAM#########################################################################
+#NET "SDRAM_CKE" LOC = "P48" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_CLK" LOC = "P50" | IOSTANDARD = LVTTL | SLEW = FAST ;
+#NET "SDRAM_nCAS" LOC = "P7" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_nRAS" LOC = "P6" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_nWE" LOC = "P8" | IOSTANDARD = LVTTL ;
+##NET "DRAM_CS_N" #CS IS PULLED LOW TO SAVE ON PIN COUNT - Can be pulled high with solder jumper on bottom of board
+#NET "SDRAM_BA<0>" LOC = "P26" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_BA<1>" LOC = "P27" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQM<0>" LOC = "P9" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQM<1>" LOC = "P67" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_ADDR<0>" LOC = "P30" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_ADDR<1>" LOC = "P32" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_ADDR<2>" LOC = "P33" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_ADDR<3>" LOC = "P34" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_ADDR<4>" LOC = "P35" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_ADDR<5>" LOC = "P40" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_ADDR<6>" LOC = "P41" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_ADDR<7>" LOC = "P43" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_ADDR<8>" LOC = "P44" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_ADDR<9>" LOC = "P45" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_ADDR<10>" LOC = "P29" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_ADDR<11>" LOC = "P46" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_ADDR<12>" LOC = "P47" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<0>" LOC = "P24" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<1>" LOC = "P23" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<2>" LOC = "P22" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<3>" LOC = "P21" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<4>" LOC = "P17" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<5>" LOC = "P12" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<6>" LOC = "P11" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<7>" LOC = "P10" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<8>" LOC = "P66" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<9>" LOC = "P62" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<10>" LOC = "P61" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<11>" LOC = "P59" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<12>" LOC = "P58" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<13>" LOC = "P57" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<14>" LOC = "P56" | IOSTANDARD = LVTTL ;
+#NET "SDRAM_DQ<15>" LOC = "P55" | IOSTANDARD = LVTTL ;
+
+#PMOD1#############################################################################
+NET "PMOD1<0>" LOC = "P5" | IOSTANDARD = LVTTL; #VGA_R2
+NET "PMOD1<1>" LOC = "P2" | IOSTANDARD = LVTTL; #VGA_G2
+NET "PMOD1<2>" LOC = "P1" | IOSTANDARD = LVTTL; #VGA_B2
+NET "PMOD1<3>" LOC = "P16" | IOSTANDARD = LVTTL; #VGA_HS
+NET "PMOD1<4>" LOC = "P88" | IOSTANDARD = LVTTL; #VGA_R1
+NET "PMOD1<5>" LOC = "P92" | IOSTANDARD = LVTTL; #VGA_G1
+NET "PMOD1<6>" LOC = "P93" | IOSTANDARD = LVTTL; #VGA_B1
+NET "PMOD1<7>" LOC = "P94" | IOSTANDARD = LVTTL; #VGA_VS
+#PMOD2#############################################################################
+NET "PMOD2<0>" LOC = "P142" | IOSTANDARD = LVTTL; #VGA_B0
+NET "PMOD2<1>" LOC = "P141" | IOSTANDARD = LVTTL; #SSEG_A2
+NET "PMOD2<2>" LOC = "P15" | IOSTANDARD = LVTTL; #SSEG_L
+NET "PMOD2<3>" LOC = "P14" | IOSTANDARD = LVTTL; #VGA_G0
+NET "PMOD2<4>" LOC = "P144" | IOSTANDARD = LVTTL; #VGA_R0
+NET "PMOD2<5>" LOC = "P143" | IOSTANDARD = LVTTL; #SSEG_A1
+NET "PMOD2<6>" LOC = "P140" | IOSTANDARD = LVTTL; #SSEG_D
+NET "PMOD2<7>" LOC = "P139" | IOSTANDARD = LVTTL; #SSEG_E
+#PMOD3#############################################################################
+NET "PMOD3<0>" LOC = "P138" | IOSTANDARD = LVTTL; #SSEG_A3
+NET "PMOD3<1>" LOC = "P137" | IOSTANDARD = LVTTL; #SSEG_A4
+NET "PMOD3<2>" LOC = "P124" | IOSTANDARD = LVTTL; #SSEG_G
+NET "PMOD3<3>" LOC = "P123" | IOSTANDARD = LVTTL; #SSEG_C
+NET "PMOD3<4>" LOC = "P119" | IOSTANDARD = LVTTL; #SSEG_DP
+NET "PMOD3<5>" LOC = "P118" | IOSTANDARD = LVTTL; #SSEG_B
+NET "PMOD3<6>" LOC = "P117" | IOSTANDARD = LVTTL; #SSEG_A
+NET "PMOD3<7>" LOC = "P116" | IOSTANDARD = LVTTL; #SSEG_F
+#PMOD4#############################################################################
+NET "PMOD4<0>" LOC = "P112" | IOSTANDARD = LVTTL; #PWM2
+NET "PMOD4<1>" LOC = "P111" | IOSTANDARD = LVTTL; #NES_CLK
+NET "PMOD4<2>" LOC = "P132" | IOSTANDARD = LVTTL; #NES_LAT
+NET "PMOD4<3>" LOC = "P131" | IOSTANDARD = LVTTL; #NES2_DAT
+NET "PMOD4<4>" LOC = "P115" | IOSTANDARD = LVTTL; #PS2_1_CLK
+NET "PMOD4<5>" LOC = "P114" | IOSTANDARD = LVTTL; #PS2_1_DAT
+NET "PMOD4<6>" LOC = "P134" | IOSTANDARD = LVTTL; #PWM1
+NET "PMOD4<7>" LOC = "P133" | IOSTANDARD = LVTTL; #NES1_DAT
+
+#PMOD4 LVDS CONSTRAINTS#############################################################
+#NET "P4_1_LVDS3_P" LOC = "P112" | IOSTANDARD = LVDS_33;
+#NET "P4_2_LVDS3_N" LOC = "P111" | IOSTANDARD = LVDS_33;
+#NET "P4_3_LVDS1_P" LOC = "P132" | IOSTANDARD = LVDS_33;
+#NET "P4_4_LVDS1_N" LOC = "P131" | IOSTANDARD = LVDS_33;
+#NET "P4_7_LVDS4_P" LOC = "P115" | IOSTANDARD = LVDS_33;
+#NET "P4_8_LVDS4_N" LOC = "P114" | IOSTANDARD = LVDS_33;
+#NET "P4_9_LVDS2_P" LOC = "P134" | IOSTANDARD = LVDS_33;
+#NET "P4_10_LVDS2_N" LOC = "P133" | IOSTANDARD = LVDS_33;
+
+#RASPBERRY-PI CONNECTOR###############################################################
+NET "SYS_SPI_MOSI" LOC = "P80" | IOSTANDARD = LVTTL; #Shared - Used to clk bitstream data to fpga / ARduino MOSI
+NET "SYS_SPI_MISO" LOC = "P75" | IOSTANDARD = LVTTL;
+NET "SYS_SPI_SCK" LOC = "P78" | IOSTANDARD = LVTTL; #Shared - Used to clk bitstream data to fpga / ARduino SCK
+NET "RP_SPI_CE0N" LOC = "P79" | IOSTANDARD = LVTTL;
+#!##NET "RP_SPI_CE1N" LOC = "P78" | IOSTANDARD = LVTTL;
+#NET "SYS_SDA" LOC = "P98" | IOSTANDARD = LVTTL; #Shared with Arduino SDA
+#NET "SYS_SCL" LOC = "P97" | IOSTANDARD = LVTTL; #Shared with Arduino SCL
+#UART FROM RASPBERRY PI - As labelled in the Rpi (master) schematic
+#NET "SYS_TX" LOC= "P83" | IOSTANDARD = LVTTL; #Pi output FPGA input #Shared with Arduino TX
+#NET "SYS_RX" LOC= "P82" | IOSTANDARD = LVTTL; #Pi input FPGA output #Shared with Arduino RX
+#NET "RP_GPIO_GCLK" LOC = "P95" | IOSTANDARD = LVTTL;
+#NET "RP_GPIO_GEN2" LOC = "P81" | IOSTANDARD = LVTTL;
+#NET "RP_GPIO_GEN3" LOC = "P80" | IOSTANDARD = LVTTL;
+
+#ARDUINO HEADERS########################################################################
+#SYS_SCL #Shared with RPI i2c
+#SYS_SDA #Shared with RPI i2c
+#NET "ARD_SCK" LOC= "P84" | IOSTANDARD = LVTTL; #D13
+#NET "ARD_MISO" LOC= "P87" | IOSTANDARD = LVTTL; #D12
+#NET "ARD_MOSI" LOC= "P51" | IOSTANDARD = LVTTL; `#D11
+#NET "ARD_SS" LOC= "P74" | IOSTANDARD = LVTTL; #D10
+#NET "ARD_D9_FLSH_DI" LOC= "P64" | IOSTANDARD = LVTTL; #D9
+#NET "ARD_D8_FLSH_CS" LOC= "P38" | IOSTANDARD = LVTTL; #D8
+
+
+
+
+
diff --git a/logi-edu-test/hw/logipi/ise/ipcore_dir/clock_gen.xise b/logi-edu-test/hw/logipi/ise/ipcore_dir/clock_gen.xise
index 079ba597..b0adad17 100644
--- a/logi-edu-test/hw/logipi/ise/ipcore_dir/clock_gen.xise
+++ b/logi-edu-test/hw/logipi/ise/ipcore_dir/clock_gen.xise
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="clock_gen/example_design/clock_gen_exdes.ucf" xil_pn:type="FILE_UCF"/>
diff --git a/logi-edu-test/hw/logipi/ise/logi_edu_test.xise b/logi-edu-test/hw/logipi/ise/logi_edu_test.xise
index 5253e655..323f9de2 100644
--- a/logi-edu-test/hw/logipi/ise/logi_edu_test.xise
+++ b/logi-edu-test/hw/logipi/ise/logi_edu_test.xise
@@ -9,19 +9,16 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../hdl/logi_edu_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
- <file xil_pn:name="../hdl/logipi_ra3.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
<file xil_pn:name="../../../../../logi-hard/hdl/utils/logi_utils_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
@@ -48,7 +45,7 @@
</file>
<file xil_pn:name="ipcore_dir/clock_gen.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../hdl/sound_440.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -56,7 +53,7 @@
</file>
<file xil_pn:name="../hdl/vga_bar_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../hdl/vga_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
@@ -64,7 +61,10 @@
</file>
<file xil_pn:name="../../../../../logi-hard/hdl/wishbone/peripherals/wishbone_7seg4x.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ </file>
+ <file xil_pn:name="../hdl/logipi_r1_5.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/clock_gen.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -96,7 +96,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -345,7 +345,7 @@
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+ <property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -396,9 +396,7 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
- <bindings>
- <binding xil_pn:location="/logi_edu_test" xil_pn:name="../hdl/logipi_ra3.ucf"/>
- </bindings>
+ <bindings/>
<libraries/>