From 42fc2dad5289733933b7635f0407ab35ce2c0475 Mon Sep 17 00:00:00 2001
From: Jonathan Piat <piat.jonathan@gmail.com>
Date: Tue, 15 Sep 2015 17:35:59 +0200
Subject: [PATCH] Added spi file for 1.5 logibone and modified project to let
 unused pins floating

---
 .../hw/logibone/hdl/logibone_r1_5.ucf         | 148 ++++++++++++++++++
 .../hw/logibone/ise/ipcore_dir/clock_gen.gise |  23 ++-
 .../hw/logibone/ise/logibone_com_test.xise    |   8 +-
 3 files changed, 175 insertions(+), 4 deletions(-)
 create mode 100644 logi-com-test/hw/logibone/hdl/logibone_r1_5.ucf

diff --git a/logi-com-test/hw/logibone/hdl/logibone_r1_5.ucf b/logi-com-test/hw/logibone/hdl/logibone_r1_5.ucf
new file mode 100644
index 00000000..653bca18
--- /dev/null
+++ b/logi-com-test/hw/logibone/hdl/logibone_r1_5.ucf
@@ -0,0 +1,148 @@
+######################################################
+######################################################
+## These constraints are for MARK-1 RPI/FPGA shield ##
+######################################################
+######################################################
+#logi-bone r1.5 check 150315 mj
+######################
+# Timing Constraints #
+######################
+
+##### Grouping Constraints #####
+NET "OSC_FPGA" TNM_NET = clk50_grp;
+NET "SYS_SPI_SCK" TNM_NET = clk100_grp;
+##### Clock Period Constraints #####
+TIMESPEC TS_PER_CLK50 = PERIOD "clk50_grp" 20.0 ns;
+TIMESPEC TS_PER_CLK100 = PERIOD "clk100_grp" 20.0 ns;
+
+NET "SYS_SPI_SCK" CLOCK_DEDICATED_ROUTE = FALSE;
+
+#INST "gpmc2wishbone" LOC = SLICE_X1Y3;
+
+#PIN "pll0/clkout4_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
+#PIN "pll0/clkout5_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
+#######################
+# Pin LOC Constraints #
+#######################
+
+#OSCILLATOR
+NET "OSC_FPGA"				LOC = "P85";
+
+#MISC###################################################################################
+NET "ARD_SCL" LOC = "P80" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ;
+NET "ARD_SDA" LOC = "P79" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ;
+#NET "ARD_D<5>" LOC = "P39" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ;
+#NET "ARD_D<4>" LOC = "P64" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW |PULLUP;
+#NET "ARD_D<3>" LOC = "P38" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ;
+#NET "ARD_D<2>" LOC = "P21" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW |PULLUP;
+#NET "ARD_D<1>" LOC = "P87" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW |PULLUP;
+#NET "ARD_D<0>" LOC = "P84" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW |PULLUP;
+#NET "ARD_TX_MODE0" LOC = "P69" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ;
+#NET "ARD_RX_MODE1" LOC = "P60" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ;
+#LED######################################################################################
+NET "LED<0>"           LOC = "P74"   ;   # 
+NET "LED<1>"           LOC = "P140" ;   # 
+#PUSH BUTTONS##############################################################################
+#NET "PB<0>"           LOC = "P83" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW  ;   # 
+#NET "PB<1>"           LOC = "P59" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW  ;   # 
+#PUSH BUTTONS##############################################################################
+#NET "SW<0>"           LOC = "P75" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW  ;   # 
+#NET "SW<1>"           LOC = "P78" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW  ;   # 
+#BB SPI PORT################################################################################
+NET "SYS_SPI_MISO"    LOC = "P82";
+NET "SYS_SPI_SCK"     LOC = "P70";	# not connected to pin by default, must enable output on buffer (fppa and flash are connected to this pin and have priority)
+NET "SYS_SPI_SS"      LOC = "P81";        
+NET "SYS_SPI_MOSI"    LOC = "P65";  # not connected to pin by default, must enable output on buffer (fppa and flash are connected to this pin and have priority)
+#PMOD1######################################################################################
+#NET "PMOD1<0>"	LOC = "P112"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW  |PULLUP;
+#NET "PMOD1<1>"	LOC = "P111"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW  |PULLUP;
+#NET "PMOD1<2>"	LOC = "P67"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW  |PULLUP;
+#NET "PMOD1<3>"	LOC = "P66"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW  |PULLUP;
+#NET "PMOD1<4>"	LOC = "P62"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW  |PULLUP;
+#NET "PMOD1<5>"	LOC = "P61"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW  |PULLUP;
+#NET "PMOD1<6>"	LOC = "P58"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW  |PULLUP;
+#NET "PMOD1<7>"	LOC = "P57"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW  |PULLUP;
+##PMOD2########################################################################################
+#NET "PMOD2<0>"	LOC = "P56"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW |PULLUP;
+#NET "PMOD2<1>"	LOC = "P55"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW |PULLUP;
+#NET "PMOD2<2>"	LOC = "P46"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW |PULLUP;
+#NET "PMOD2<3>"	LOC = "P45"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW |PULLUP;
+#NET "PMOD2<4>"	LOC = "P48"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW |PULLUP;
+#NET "PMOD2<5>"	LOC = "P47"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW |PULLUP;
+#NET "PMOD2<6>"	LOC = "P44"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW |PULLUP;
+#NET "PMOD2<7>"	LOC = "P43"| IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW |PULLUP;
+##SATA##########################################################################################
+#NET "SATA_D1_P"	LOC = "P41";
+#NET "SATA_D1_N"	LOC = "P40";
+#NET "SATA_D2_P"	LOC = "P51";
+#NET "SATA_D2_N"	LOC = "P50";
+##GPMC PORT##############################################################################
+##GPMC CLK
+#NET "GPMC_CLK"           LOC = "P95"| IOSTANDARD = LVTTL | SLEW = FAST |  IOB=FORCE ;   # 
+##GPMC CONTROL
+#NET "GPMC_CSN"          LOC = "P101"| IOSTANDARD = LVTTL | SLEW = FAST  |  IOB=FORCE ;  # 
+#NET "GPMC_ADVN"          LOC = "P119"| IOSTANDARD = LVTTL | SLEW = FAST   |  IOB=FORCE;   #
+#NET "GPMC_OEN"           LOC = "P118"| IOSTANDARD = LVTTL | SLEW = FAST   |  IOB=FORCE;   #  
+#NET "GPMC_BEN<0>"          LOC = "P117"| IOSTANDARD = LVTTL | SLEW = FAST  |  IOB=FORCE ;   # 
+#NET "GPMC_BEN<1>"          LOC = "P88"| IOSTANDARD = LVTTL | SLEW = FAST   |  IOB=FORCE;   # 
+#NET "GPMC_WEN"          LOC = "P116"| IOSTANDARD = LVTTL | SLEW = FAST  |  IOB=FORCE ;  # 
+##GPMC A/D
+#NET "GPMC_AD<0>"   LOC = "P97"| IOSTANDARD = LVTTL | SLEW = FAST   |  IOB=FORCE ;   # 
+#NET "GPMC_AD<1>"   LOC = "P98"| IOSTANDARD = LVTTL | SLEW = FAST   |  IOB=FORCE;   # 
+#NET "GPMC_AD<2>"           LOC = "P121"| IOSTANDARD = LVTTL | SLEW = FAST  |  IOB=FORCE;   # 
+#NET "GPMC_AD<3>"           LOC = "P120"| IOSTANDARD = LVTTL | SLEW = FAST  |  IOB=FORCE;   # 
+#NET "GPMC_AD<4>"           LOC = "P99"| IOSTANDARD = LVTTL | SLEW = FAST  |  IOB=FORCE;  # 
+#NET "GPMC_AD<5>"           LOC = "P100"| IOSTANDARD = LVTTL |  SLEW = FAST |  IOB=FORCE ;   # 
+#NET "GPMC_AD<6>"           LOC = "P124"| IOSTANDARD = LVTTL |  SLEW = FAST |  IOB=FORCE ;   # 
+#NET "GPMC_AD<7>"           LOC = "P123"| IOSTANDARD = LVTTL |  SLEW = FAST |  IOB=FORCE ;   # 
+#NET "GPMC_AD<8>"           LOC = "P102"| IOSTANDARD = LVTTL |  SLEW = FAST |  IOB=FORCE;   # 
+#NET "GPMC_AD<9>"           LOC = "P105"| IOSTANDARD = LVTTL |  SLEW = FAST |  IOB=FORCE;   # 
+#NET "GPMC_AD<10>"          LOC = "P104"| IOSTANDARD = LVTTL |  SLEW = FAST |  IOB=FORCE ;  # 
+#NET "GPMC_AD<11>"          LOC = "P94"| IOSTANDARD = LVTTL |  SLEW = FAST  |  IOB=FORCE;   # 
+#NET "GPMC_AD<12>"          LOC = "P114"| IOSTANDARD = LVTTL |  SLEW = FAST |  IOB=FORCE ;   # 
+#NET "GPMC_AD<13>"          LOC = "P115"| IOSTANDARD = LVTTL |  SLEW = FAST |  IOB=FORCE ;  # 
+#NET "GPMC_AD<14>"          LOC = "P93"| IOSTANDARD = LVTTL |  SLEW = FAST |  IOB=FORCE ;  # 
+#NET "GPMC_AD<15>"          LOC = "P92"| IOSTANDARD = LVTTL |  SLEW = FAST |  IOB=FORCE ;   # 
+#
+#
+#
+##SDRAM###########################################################################################
+#NET "SDRAM_CKE"	LOC = P24		| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_CLK"	LOC = P23		| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;
+#NET "SDRAM_nCAS"	LOC = P143	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_nRAS"	LOC = P142	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;
+#NET "SDRAM_nWE"	LOC = P144	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;
+##NET "DRAM_CS_N"  #THIS PIN IS PULLED LOW TO SAVE ON PIN COUNT.  CAN BE PULLED HIGH(DISABLED)WITH JUMPER ON BOTTOM OF BOARD.
+#NET "SDRAM_BA<0>"	LOC = P141		| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_BA<1>"	LOC = P1		| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQM<0>" LOC = P139	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;
+#NET "SDRAM_DQM<1>" LOC = P22	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_ADDR<0>"	LOC = P5	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_ADDR<1>"	LOC = P6	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_ADDR<2>"	LOC = P7	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_ADDR<3>"	LOC = P8	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_ADDR<4>"	LOC = P35	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_ADDR<5>"	LOC = P34	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_ADDR<6>"	LOC = P33	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_ADDR<7>"	LOC = P32	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_ADDR<8>"	LOC = P30	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_ADDR<9>"	LOC = P29	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_ADDR<10>"	LOC = P2		| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;		
+#NET "SDRAM_ADDR<11>"	LOC = P27	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_ADDR<12>"	LOC = P26	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;		
+#NET "SDRAM_DQ<0>" LOC = P126	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<1>" LOC = P127	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<2>" LOC = P131	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<3>" LOC = P132	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<4>" LOC = P133	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<5>" LOC = P134	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<6>" LOC = P137	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<7>" LOC = P138	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<8>" LOC = P17		| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<9>" LOC = P16		| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<10>" LOC = P15	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<11>" LOC = P14	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<12>" LOC = P12	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<13>" LOC = P11	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;		
+#NET "SDRAM_DQ<14>" LOC = P10	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;	
+#NET "SDRAM_DQ<15>" LOC = P9	| IOSTANDARD = LVTTL | SLEW = FAST | IOB=TRUE  ;
diff --git a/logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen.gise b/logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen.gise
index 1147e94c..be35c198 100644
--- a/logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen.gise
+++ b/logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen.gise
@@ -26,6 +26,27 @@
     <file xil_pn:fileType="FILE_VHO" xil_pn:name="clock_gen.vho" xil_pn:origination="imported"/>
   </files>
 
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1442330739" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1442330739">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1442330739" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4968307030376727929" xil_pn:start_ts="1442330739">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1442330739" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6494861454191587191" xil_pn:start_ts="1442330739">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1442330739" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1442330739">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1442330739" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8190026018971872887" xil_pn:start_ts="1442330739">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+  </transforms>
 
 </generated_project>
diff --git a/logi-com-test/hw/logibone/ise/logibone_com_test.xise b/logi-com-test/hw/logibone/ise/logibone_com_test.xise
index e74e1932..ed2f43cf 100644
--- a/logi-com-test/hw/logibone/ise/logibone_com_test.xise
+++ b/logi-com-test/hw/logibone/ise/logibone_com_test.xise
@@ -66,7 +66,8 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
-    <file xil_pn:name="../hdl/logibone_r1_spi.ucf" xil_pn:type="FILE_UCF">
+    <file xil_pn:name="../hdl/logibone_r1_spi.ucf" xil_pn:type="FILE_UCF"/>
+    <file xil_pn:name="../hdl/logibone_r1_5.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="ipcore_dir/clock_gen.xise" xil_pn:type="FILE_COREGENISE">
@@ -347,7 +348,7 @@
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -369,7 +370,7 @@
     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.1/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
     <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
@@ -401,6 +402,7 @@
   <bindings>
     <binding xil_pn:location="/logibone_com_test" xil_pn:name="../hdl/logibone_r1.ucf"/>
     <binding xil_pn:location="/logibone_com_test_spi" xil_pn:name="../hdl/logibone_r1_spi.ucf"/>
+    <binding xil_pn:location="/logibone_com_test_spi" xil_pn:name="../hdl/logibone_r1_5.ucf"/>
   </bindings>
 
   <libraries/>