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cpu.cpp
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// (C) 2018-2024 by Folkert van Heusden
// Released under MIT license
#include <assert.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "breakpoint.h"
#include "bus.h"
#include "cpu.h"
#include "gen.h"
#include "log.h"
#include "utils.h"
#define SIGN(x, wm) ((wm) == wm_byte ? (x) & 0x80 : (x) & 0x8000)
#define IS_0(x, wm) ((wm) == wm_byte ? ((x) & 0xff) == 0 : (x) == 0)
// see https://retrocomputing.stackexchange.com/questions/6960/what-was-the-clock-speed-and-ips-for-the-original-pdp-11
constexpr const double pdp11_clock_cycle = 150; // ns, for the 11/70
constexpr const double pdp11_MHz = 1000.0 / pdp11_clock_cycle;
constexpr const double pdp11_avg_cycles_per_instruction = (1 + 5) / 2.0;
constexpr const double pdp11_estimated_mips = pdp11_MHz / pdp11_avg_cycles_per_instruction;
cpu::cpu(bus *const b, std::atomic_uint32_t *const event) : b(b), event(event)
{
reset();
#if defined(BUILD_FOR_RP2040)
xSemaphoreGive(qi_lock); // initialize
#endif
}
cpu::~cpu()
{
}
void cpu::init_interrupt_queue()
{
queued_interrupts.clear();
for(uint8_t level=0; level<8; level++)
queued_interrupts.insert({ level, { } });
}
void cpu::emulation_start()
{
instruction_count = 0;
running_since = get_us();
wait_time = 0;
}
std::optional<std::string> cpu::check_breakpoint()
{
for(auto & bp: breakpoints) {
auto rc = bp.second->is_triggered();
if (rc.has_value())
return rc;
}
return { };
}
int cpu::set_breakpoint(breakpoint *const bp)
{
breakpoints.insert({ ++bp_nr, bp });
return bp_nr;
}
bool cpu::remove_breakpoint(const int bp_id)
{
auto it = breakpoints.find(bp_id);
if (it == breakpoints.end())
return false;
delete it->second;
return breakpoints.erase(bp_id) == 1;
}
std::map<int, breakpoint *> cpu::list_breakpoints()
{
return breakpoints;
}
uint64_t cpu::get_instructions_executed_count() const
{
// this may wreck havoc as it is not protected by a mutex
// but a mutex would slow things down too much (as would
// do an atomic)
return instruction_count;
}
std::tuple<double, double, uint64_t, uint32_t, double> cpu::get_mips_rel_speed(const std::optional<uint64_t> & instruction_count, const std::optional<uint64_t> & t_diff_in) const
{
uint64_t instr_count = instruction_count.has_value() ? instruction_count.value() : get_instructions_executed_count();
uint64_t t_diff = t_diff_in.has_value() ? t_diff_in.value() : (get_us() - running_since - wait_time);
double mips = t_diff ? instr_count / double(t_diff) : 0;
return { mips, mips * 100 / pdp11_estimated_mips, instr_count, t_diff, wait_time };
}
uint32_t cpu::get_effective_run_time(const uint64_t instruction_count) const
{
// division is to go from ns to ms
return instruction_count * pdp11_avg_cycles_per_instruction * pdp11_clock_cycle / 1000000l;
}
void cpu::add_to_stack_trace(const uint16_t p)
{
auto da = disassemble(p);
stacktrace.push_back({ p, da["instruction-text"][0] });
while (stacktrace.size() >= max_stacktrace_depth)
stacktrace.erase(stacktrace.begin());
}
void cpu::pop_from_stack_trace()
{
if (!stacktrace.empty())
stacktrace.pop_back();
}
std::vector<std::pair<uint16_t, std::string> > cpu::get_stack_trace() const
{
return stacktrace;
}
void cpu::reset()
{
memset(regs0_5, 0x00, sizeof regs0_5);
memset(sp, 0x00, sizeof sp);
pc = 0;
psw = 0; // 7 << 5;
fpsr = 0;
init_interrupt_queue();
}
uint16_t cpu::get_register(const int nr) const
{
if (nr < 6) {
int set = get_register_set();
return regs0_5[set][nr];
}
if (nr == 6)
return sp[getPSW_runmode()];
assert(nr == 7);
return pc;
}
void cpu::set_register(const int nr, const uint16_t value)
{
if (nr < 6) {
int set = get_register_set();
regs0_5[set][nr] = value;
}
else if (nr == 6)
sp[getPSW_runmode()] = value;
else {
assert(nr == 7);
pc = value;
}
}
void cpu::set_registerLowByte(const int nr, const word_mode_t word_mode, const uint16_t value)
{
if (word_mode == wm_byte) {
uint16_t v = get_register(nr);
v &= 0xff00;
assert(value < 256);
v |= value;
set_register(nr, v);
}
else {
set_register(nr, value);
}
}
bool cpu::put_result(const gam_rc_t & g, const uint16_t value)
{
if (g.addr.has_value() == false) {
set_registerLowByte(g.reg.value(), g.word_mode, value);
return true;
}
return b->write(g.addr.value(), g.word_mode, value, g.mode_selection, g.space) == false;
}
uint16_t cpu::add_register(const int nr, const uint16_t value)
{
if (nr < 6)
return regs0_5[get_register_set()][nr] += value;
if (nr == 6)
return sp[getPSW_runmode()] += value;
assert(nr == 7);
return pc += value;
}
void cpu::lowlevel_register_set(const uint8_t set, const uint8_t reg, const uint16_t value)
{
assert(set < 2);
assert(reg < 8);
if (reg < 6)
regs0_5[set][reg] = value;
else if (reg == 6)
sp[set == 0 ? 0 : 3] = value;
else {
assert(reg == 7);
pc = value;
}
}
uint16_t cpu::lowlevel_register_get(const uint8_t set, const uint8_t reg)
{
assert(set < 2);
assert(reg < 8);
if (reg < 6)
return regs0_5[set][reg];
if (reg == 6)
return sp[set == 0 ? 0 : 3];
assert(reg == 7);
return pc;
}
void cpu::lowlevel_register_sp_set(const uint8_t set, const uint16_t value)
{
assert(set < 4);
sp[set] = value;
}
bool cpu::getBitPSW(const int bit) const
{
return (psw >> bit) & 1;
}
bool cpu::getPSW_c() const
{
return getBitPSW(0);
}
bool cpu::getPSW_v() const
{
return getBitPSW(1);
}
bool cpu::getPSW_z() const
{
return getBitPSW(2);
}
bool cpu::getPSW_n() const
{
return getBitPSW(3);
}
void cpu::setBitPSW(const int bit, const bool v)
{
psw &= ~(1 << bit);
psw |= v << bit;
}
void cpu::setPSW_c(const bool v)
{
setBitPSW(0, v);
}
void cpu::setPSW_v(const bool v)
{
setBitPSW(1, v);
}
void cpu::setPSW_z(const bool v)
{
setBitPSW(2, v);
}
void cpu::setPSW_n(const bool v)
{
setBitPSW(3, v);
}
void cpu::setPSW_spl(const int v)
{
psw &= ~(7 << 5);
psw |= v << 5;
}
int cpu::getPSW_spl() const
{
return (psw >> 5) & 7;
}
void cpu::setPSW(const uint16_t v, const bool limited)
{
if (limited) {
// cannot replace the run-mode bits nor the set of registers
// psw = (psw & ~0340) | (v & 0174340);
psw = (psw & 0177400) | (v & 037777);
}
else {
psw = v;
}
}
void cpu::setPSW_flags_nzv(const uint16_t value, const word_mode_t word_mode)
{
setPSW_n(SIGN(value, word_mode));
setPSW_z(IS_0(value, word_mode));
setPSW_v(false);
}
bool cpu::check_pending_interrupts() const
{
if (trap_delay.has_value() && trap_delay.value() > 1)
return false;
uint8_t start_level = getPSW_spl() + 1;
for(uint8_t i=start_level; i < 8; i++) {
auto interrupts = queued_interrupts.find(i);
assert(interrupts != queued_interrupts.end());
if (interrupts->second.empty() == false)
return true;
}
return false;
}
bool cpu::execute_any_pending_interrupt()
{
#if defined(BUILD_FOR_RP2040)
xSemaphoreTake(qi_lock, portMAX_DELAY);
#else
std::unique_lock<std::mutex> lck(qi_lock);
#endif
bool can_trigger = false;
if (trap_delay.has_value()) {
trap_delay.value()--;
TRACE("Delayed trap: %d instructions left", trap_delay.value());
if (trap_delay.value() > 0)
return false;
trap_delay.reset();
can_trigger = true;
}
any_queued_interrupts = false;
uint8_t current_level = getPSW_spl();
// uint8_t start_level = current_level <= 3 ? 0 : current_level + 1;
// PDP-11_70_Handbook_1977-78.pdf page 1-5, "processor priority"
uint8_t start_level = current_level + 1;
for(uint8_t i=0; i < 8; i++) {
auto interrupts = queued_interrupts.find(i);
if (interrupts->second.empty() == false) {
any_queued_interrupts = true;
if (i < start_level) // at leas we know now that there's an interrupt scheduled
continue;
if (can_trigger == false) {
trap_delay = initial_trap_delay;
return false;
}
auto vector = interrupts->second.begin();
uint8_t v = *vector;
interrupts->second.erase(vector);
TRACE("Invoking interrupt vector %o (IPL %d, current: %d)", v, i, current_level);
trap(v, i, true);
// when there are more interrupts scheduled, invoke them asap
trap_delay = initial_trap_delay;
#if defined(BUILD_FOR_RP2040)
xSemaphoreGive(qi_lock);
#endif
return true;
}
}
if (any_queued_interrupts && trap_delay.has_value() == false)
trap_delay = initial_trap_delay;
#if defined(BUILD_FOR_RP2040)
xSemaphoreGive(qi_lock);
#endif
return false;
}
void cpu::queue_interrupt(const uint8_t level, const uint8_t vector)
{
#if defined(BUILD_FOR_RP2040)
xSemaphoreTake(qi_lock, portMAX_DELAY);
#else
std::unique_lock<std::mutex> lck(qi_lock);
#endif
auto it = queued_interrupts.find(level);
assert(it != queued_interrupts.end());
it->second.insert(vector);
#if defined(BUILD_FOR_RP2040)
xSemaphoreGive(qi_lock);
uint8_t value = 1;
xQueueSend(qi_q, &value, portMAX_DELAY);
#else
qi_cv.notify_all();
#endif
any_queued_interrupts = true;
TRACE("Queueing interrupt vector %o (IPL %d, current: %d), n: %zu", vector, level, getPSW_spl(), it->second.size());
}
void cpu::addToMMR1(const gam_rc_t & g)
{
if (!b->getMMU()->isMMR1Locked() && g.mmr1_update.has_value()) {
assert(g.mmr1_update.value().delta);
b->getMMU()->addToMMR1(g.mmr1_update.value().delta, g.mmr1_update.value().reg);
}
}
// GAM = general addressing modes
gam_rc_t cpu::getGAM(const uint8_t mode, const uint8_t reg, const word_mode_t word_mode, const bool read_value)
{
gam_rc_t g { word_mode, rm_cur, i_space, mode, { }, { }, { }, { } };
d_i_space_t isR7_space = reg == 7 ? i_space : (b->getMMU()->get_use_data_space(getPSW_runmode()) ? d_space : i_space);
// ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ always d_space here? TODO
g.space = isR7_space;
uint16_t next_word = 0;
switch(mode) {
case 0: // Rn
g.reg = reg;
g.value = get_register(reg) & (word_mode == wm_byte ? 0xff : 0xffff);
break;
case 1: // (Rn)
g.addr = get_register(reg);
if (read_value)
g.value = b->read(g.addr.value(), word_mode, rm_cur, isR7_space);
break;
case 2: // (Rn)+ / #n
g.addr = get_register(reg);
if (read_value)
g.value = b->read(g.addr.value(), word_mode, rm_cur, isR7_space);
add_register(reg, word_mode == wm_word || reg == 7 || reg == 6 ? 2 : 1);
g.mmr1_update = { word_mode == wm_word || reg == 7 || reg == 6 ? 2 : 1, reg };
break;
case 3: // @(Rn)+ / @#a
g.addr = b->read(get_register(reg), wm_word, rm_cur, isR7_space);
// might be wrong: the adds should happen when the read is really performed, because of traps
add_register(reg, 2);
g.mmr1_update = { 2, reg };
g.space = d_space;
if (read_value)
g.value = b->read(g.addr.value(), word_mode, rm_cur, g.space);
break;
case 4: // -(Rn)
add_register(reg, word_mode == wm_word || reg == 7 || reg == 6 ? -2 : -1);
g.mmr1_update = { word_mode == wm_word || reg == 7 || reg == 6 ? -2 : -1, reg };
g.space = d_space;
g.addr = get_register(reg);
if (read_value)
g.value = b->read(g.addr.value(), word_mode, rm_cur, isR7_space);
break;
case 5: // @-(Rn)
add_register(reg, -2);
g.mmr1_update = { -2, reg };
g.addr = b->read(get_register(reg), wm_word, rm_cur, isR7_space);
g.space = d_space;
if (read_value)
g.value = b->read(g.addr.value(), word_mode, rm_cur, g.space);
break;
case 6: // x(Rn) / a
next_word = b->read(getPC(), wm_word, rm_cur, i_space);
add_register(7, + 2);
g.addr = get_register(reg) + next_word;
g.space = d_space;
if (read_value)
g.value = b->read(g.addr.value(), word_mode, rm_cur, g.space);
break;
case 7: // @x(Rn) / @a
next_word = b->read(getPC(), wm_word, rm_cur, i_space);
add_register(7, + 2);
g.addr = b->read(get_register(reg) + next_word, wm_word, rm_cur, d_space);
g.space = d_space;
if (read_value)
g.value = b->read(g.addr.value(), word_mode, rm_cur, g.space);
break;
}
assert(g.value < 256 || word_mode == wm_word);
return g;
}
bool cpu::putGAM(const gam_rc_t & g, const uint16_t value)
{
assert(value < 256 || g.word_mode == wm_word);
if (g.addr.has_value()) {
auto rc = b->write(g.addr.value(), g.word_mode, value, g.mode_selection, g.space);
return rc == false;
}
if (g.mode_selection == rm_prev) {
assert(g.reg.value() == 6);
sp[getPSW_prev_runmode()] = value;
}
else {
set_register(g.reg.value(), value);
}
return true;
}
gam_rc_t cpu::getGAMAddress(const uint8_t mode, const int reg, const word_mode_t word_mode)
{
return getGAM(mode, reg, word_mode, false);
}
bool cpu::double_operand_instructions(const uint16_t instr)
{
const uint8_t operation = (instr >> 12) & 7;
if (operation == 0b000)
return single_operand_instructions(instr);
const word_mode_t word_mode = instr & 0x8000 ? wm_byte : wm_word;
if (operation == 0b111) {
if (word_mode == wm_byte)
return false;
return additional_double_operand_instructions(instr);
}
const uint8_t src = (instr >> 6) & 63;
const uint8_t src_mode = (src >> 3) & 7;
const uint8_t src_reg = src & 7;
const uint8_t dst = instr & 63;
const uint8_t dst_mode = (dst >> 3) & 7;
const uint8_t dst_reg = dst & 7;
switch(operation) {
case 0b001: { // MOV/MOVB Move Word/Byte
gam_rc_t g_src = getGAM(src_mode, src_reg, word_mode);
bool set_flags = true;
if (word_mode == wm_byte && dst_mode == 0)
set_register(dst_reg, int8_t(g_src.value.value())); // int8_t: sign extension
else {
auto g_dst = getGAMAddress(dst_mode, dst_reg, word_mode);
addToMMR1(g_dst);
set_flags = putGAM(g_dst, g_src.value.value());
}
addToMMR1(g_src);
if (set_flags)
setPSW_flags_nzv(g_src.value.value(), word_mode);
return true;
}
case 0b010: { // CMP/CMPB Compare Word/Byte
gam_rc_t g_src = getGAM(src_mode, src_reg, word_mode);
auto g_dst = getGAM(dst_mode, dst_reg, word_mode);
addToMMR1(g_dst);
addToMMR1(g_src);
uint16_t temp = (g_src.value.value() - g_dst.value.value()) & (word_mode == wm_byte ? 0xff : 0xffff);
setPSW_n(SIGN(temp, word_mode));
setPSW_z(IS_0(temp, word_mode));
setPSW_v(SIGN((g_src.value.value() ^ g_dst.value.value()) & (~g_dst.value.value() ^ temp), word_mode));
setPSW_c(g_src.value.value() < g_dst.value.value());
return true;
}
case 0b011: { // BIT/BITB Bit Test Word/Byte
gam_rc_t g_src = getGAM(src_mode, src_reg, word_mode);
auto g_dst = getGAM(dst_mode, dst_reg, word_mode);
addToMMR1(g_dst);
addToMMR1(g_src);
uint16_t result = (g_dst.value.value() & g_src.value.value()) & (word_mode == wm_byte ? 0xff : 0xffff);
setPSW_flags_nzv(result, word_mode);
return true;
}
case 0b100: { // BIC/BICB Bit Clear Word/Byte
gam_rc_t g_src = getGAM(src_mode, src_reg, word_mode);
if (dst_mode == 0) {
addToMMR1(g_src); // keep here because of order of updates
uint16_t v = get_register(dst_reg); // need the full word
uint16_t result = v & ~g_src.value.value();
set_register(dst_reg, result);
setPSW_flags_nzv(result, word_mode);
}
else {
auto g_dst = getGAM(dst_mode, dst_reg, word_mode);
addToMMR1(g_dst);
addToMMR1(g_src);
uint16_t result = g_dst.value.value() & ~g_src.value.value();
if (put_result(g_dst, result))
setPSW_flags_nzv(result, word_mode);
}
return true;
}
case 0b101: { // BIS/BISB Bit Set Word/Byte
gam_rc_t g_src = getGAM(src_mode, src_reg, word_mode);
if (dst_mode == 0) {
addToMMR1(g_src); // keep here because of order of updates
uint16_t v = get_register(dst_reg); // need the full word
uint16_t result = v | g_src.value.value();
set_register(dst_reg, result);
setPSW_n(SIGN(result, word_mode));
setPSW_z(IS_0(result, word_mode));
setPSW_v(false);
}
else {
auto g_dst = getGAM(dst_mode, dst_reg, word_mode);
addToMMR1(g_dst);
addToMMR1(g_src);
uint16_t result = g_dst.value.value() | g_src.value.value();
if (put_result(g_dst, result)) {
setPSW_n(SIGN(result, word_mode));
setPSW_z(IS_0(result, word_mode));
setPSW_v(false);
}
}
return true;
}
case 0b110: { // ADD/SUB Add/Subtract Word
auto g_ssrc = getGAM(src_mode, src_reg, wm_word);
auto g_dst = getGAM(dst_mode, dst_reg, wm_word);
addToMMR1(g_dst);
addToMMR1(g_ssrc);
int16_t result = 0;
bool set_flags = true;
if (g_dst.addr.has_value())
set_flags = !b->is_psw(g_dst.addr.value(), g_dst.mode_selection, g_dst.space);
if (instr & 0x8000) { // SUB
result = (g_dst.value.value() - g_ssrc.value.value()) & 0xffff;
if (set_flags) {
setPSW_v(SIGN((g_dst.value.value() ^ g_ssrc.value.value()) & (~g_ssrc.value.value() ^ result), wm_word));
setPSW_c(uint16_t(g_dst.value.value()) < uint16_t(g_ssrc.value.value()));
}
}
else { // ADD
uint32_t temp = g_dst.value.value() + g_ssrc.value.value();
result = temp;
if (set_flags) {
setPSW_v(SIGN((~g_ssrc.value.value() ^ g_dst.value.value()) & (g_ssrc.value.value() ^ (temp & 0xffff)), wm_word));
setPSW_c(uint16_t(result) < uint16_t(g_ssrc.value.value()));
}
}
if (set_flags) {
setPSW_n(result < 0);
setPSW_z(result == 0);
}
(void)putGAM(g_dst, result);
return true;
}
}
return false;
}
bool cpu::additional_double_operand_instructions(const uint16_t instr)
{
const uint8_t reg = (instr >> 6) & 7;
const uint8_t dst = instr & 63;
const uint8_t dst_mode = (dst >> 3) & 7;
const uint8_t dst_reg = dst & 7;
const int operation = (instr >> 9) & 7;
switch(operation) {
case 0: { // MUL
int16_t R1 = get_register(reg);
auto R2g = getGAM(dst_mode, dst_reg, wm_word);
addToMMR1(R2g);
int16_t R2 = R2g.value.value();
int32_t result = R1 * R2;
set_register(reg, result >> 16);
set_register(reg | 1, result & 65535);
setPSW_n(result < 0);
setPSW_z(result == 0);
setPSW_v(false);
setPSW_c(result < -32768 || result > 32767);
return true;
}
case 1: { // DIV
auto R2g = getGAM(dst_mode, dst_reg, wm_word);
addToMMR1(R2g);
int16_t divider = R2g.value.value();
int32_t R0R1 = (uint32_t(get_register(reg)) << 16) | get_register(reg | 1);
if (divider == 0) { // divide by zero
setPSW_n(false);
setPSW_z(true);
setPSW_v(true);
setPSW_c(true);
return true;
}
else if (divider == -1 && uint32_t(R0R1) == 0x80000000) { // maximum negative value; too big
setPSW_n(false);
setPSW_z(false);
setPSW_v(true);
setPSW_c(false);
return true;
}
int32_t quot = R0R1 / divider;
int16_t rem = R0R1 % divider;
setPSW_n(quot < 0);
setPSW_z(quot == 0);
setPSW_c(false);
if (quot > 32767 || quot < -32768) {
setPSW_v(true);
return true;
}
set_register(reg, quot);
set_register(reg | 1, rem);
setPSW_v(false);
return true;
}
case 2: { // ASH
uint32_t R = get_register(reg), oldR = R;
auto g_dst = getGAM(dst_mode, dst_reg, wm_word);
addToMMR1(g_dst);
uint16_t shift = g_dst.value.value() & 077;
TRACE("shift %06o with %d", R, shift);
bool sign = SIGN(R, wm_word);
if (shift == 0) {
setPSW_c(false);
setPSW_v(false);
}
else if (shift <= 15) {
R <<= shift;
setPSW_c(R & 0x10000);
setPSW_v(SIGN(oldR, wm_word) != SIGN(R, wm_word));
}
else if (shift < 32) {
setPSW_c((R << (shift - 16)) & 1);
R = 0;
setPSW_v(SIGN(oldR, wm_word) != SIGN(R, wm_word));
}
else if (shift == 32) {
R = -sign;
setPSW_c(sign);
setPSW_v(SIGN(R, wm_word) != SIGN(oldR, wm_word));
}
else {
int shift_n = 64 - shift;
uint32_t sign_extend = sign ? 0x8000 : 0;
for(int i=0; i<shift_n; i++) {
setPSW_c(R & 1);
R >>= 1;
R |= sign_extend;
}
setPSW_v(SIGN(R, wm_word) != SIGN(oldR, wm_word));
}
R &= 0xffff;
setPSW_n(SIGN(R, wm_word));
setPSW_z(R == 0);
set_register(reg, R);
return true;
}
case 3: { // ASHC
uint32_t R0R1 = (uint32_t(get_register(reg)) << 16) | get_register(reg | 1);
auto g_dst = getGAM(dst_mode, dst_reg, wm_word);
addToMMR1(g_dst);
uint16_t shift = g_dst.value.value() & 077;
bool sign = R0R1 & 0x80000000;
setPSW_v(false);
if (shift == 0)
setPSW_c(false);
else if (shift < 32) {
R0R1 <<= shift - 1;
setPSW_c(R0R1 >> 31);
R0R1 <<= 1;
}
else if (shift == 32) {
R0R1 = -sign;
setPSW_c(sign);
}
else {
int shift_n = (64 - shift) - 1;
// extend sign-bit
if (sign) { // convert to unsigned 64b int & extend sign
R0R1 = (uint64_t(R0R1) | 0xffffffff00000000ll) >> shift_n;
setPSW_c(R0R1 & 1);
R0R1 = (uint64_t(R0R1) | 0xffffffff00000000ll) >> 1;
}
else {
R0R1 >>= shift_n;
setPSW_c(R0R1 & 1);
R0R1 >>= 1;
}
}
bool new_sign = R0R1 & 0x80000000;
setPSW_v(sign != new_sign);
set_register(reg, R0R1 >> 16);
set_register(reg | 1, R0R1 & 65535);
setPSW_n(R0R1 & 0x80000000);
setPSW_z(R0R1 == 0);
return true;
}
case 4: { // XOR (word only)
uint16_t reg_v = get_register(reg); // in case it is R7
auto g_dst = getGAM(dst_mode, dst_reg, wm_word);
addToMMR1(g_dst);
uint16_t vl = g_dst.value.value() ^ reg_v;
bool set_flags = putGAM(g_dst, vl);
if (set_flags)
setPSW_flags_nzv(vl, wm_word);
return true;
}
case 7: { // SOB
if (add_register(reg, -1)) {
uint16_t newPC = getPC() - dst * 2;
setPC(newPC);
}
return true;
}
}
return false;
}
bool cpu::single_operand_instructions(const uint16_t instr)
{
const uint16_t opcode = (instr >> 6) & 0b111111111;
const uint8_t dst = instr & 63;
const uint8_t dst_mode = (dst >> 3) & 7;
const uint8_t dst_reg = dst & 7;
const word_mode_t word_mode = instr & 0x8000 ? wm_byte : wm_word;
switch(opcode) {
case 0b00000011: { // SWAB
if (word_mode == wm_byte) // handled elsewhere
return false;
auto g_dst = getGAM(dst_mode, dst_reg, word_mode);
addToMMR1(g_dst);
uint16_t v = g_dst.value.value();
v = (v << 8) | (v >> 8);
bool set_flags = putGAM(g_dst, v);
if (set_flags) {
setPSW_flags_nzv(v, wm_byte);
setPSW_c(false);
}
break;