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synth_basic_dsp.qsf
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# Copyright (C) 2001-2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#############################################################
# Device setup
#############################################################
set_global_assignment -name FAMILY "Stratix 10"
set_global_assignment -name DEVICE 1SG280LU3F50E3VGS2
#############################################################
# Files and basic setup
#############################################################
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name TOP_LEVEL_ENTITY basic_dsp_persona_top
#############################################################
# PR setup
#############################################################
set_global_assignment -name REVISION_TYPE PR_SYN
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Pro Edition"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name SYSTEMVERILOG_FILE source/basic_dsp_persona/basic_dsp_persona_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/basic_dsp_persona/basic_dsp_persona.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/basic_dsp_persona/basic_dsp_top.sv
set_global_assignment -name QSYS_FILE source/common/reg_file/reg_file.qsys
set_global_assignment -name IP_FILE source/common/reg_file/ip/reg_file/reg_file_clock_bridge.ip
set_global_assignment -name IP_FILE source/common/reg_file/ip/reg_file/reg_file_mm_bridge.ip
set_global_assignment -name IP_FILE source/common/reg_file/ip/reg_file/reg_file_reset_bridge.ip
set_global_assignment -name IP_FILE source/common/reg_file/ip/reg_file/reg_file_pio_out.ip
set_global_assignment -name IP_FILE source/common/reg_file/ip/reg_file/reg_file_pio_in.ip
#############################################################
# SignalTap
#############################################################
set_global_assignment -name IP_FILE source/common/sld_jtag_host/ip/sld_jtag_host.ip
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE basic_dsp_persona.stp
set_global_assignment -name SIGNALTAP_FILE basic_dsp_persona.stp