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pr_logic_impl_template.qsf.template
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#############################################################
# Device setup
#############################################################
set_global_assignment -name FAMILY "Stratix 10"
set_global_assignment -name DEVICE 1SG280LU3F50E3VGS2
#############################################################
# Files and basic setup
#############################################################
set_global_assignment -name TOP_LEVEL_ENTITY s10_pcie_ref_design
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
#############################################################
# SDC constraints - Note they are before the Qsys files
#############################################################
set_global_assignment -name SDC_FILE jtag.sdc
set_global_assignment -name SDC_FILE s10_pcie_devkit_pr.sdc
#############################################################
# QSYS and IP Files
#############################################################
set_global_assignment -name QSYS_FILE source/static_region/bsp_top.qsys
set_global_assignment -name QSYS_FILE source/static_region/design_top.qsys
set_global_assignment -name QSYS_FILE source/static_region/pr_subsystem.qsys
set_global_assignment -name IP_FILE source/static_region/ip/bsp_top/bsp_top_emif_s10_0.ip
set_global_assignment -name IP_FILE source/static_region/ip/bsp_top/s10_pcie.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/avalon_mm_clk.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/avalon_system_config.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/ddr4_calibration_pio.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/ddr4_ctlr_mm_clock_bridge.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/emif_clock.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/emif_reset_n.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/global_rst_n.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/pcie_mm_clock_crossing_bridge.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/pcie_rst_n.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/pr_subsystem_pll_ref_clk.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/pcie_avmm_pbridge.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/emif_avmm_pbridge.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/design_top_iopll.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/s10_pr.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/emif_avmm_bridge.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/ddr4_reset_request.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/bar4_avmm_pipeline_bridge_0.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/bar4_avmm_cc_bridge.ip
set_global_assignment -name IP_FILE source/static_region/ip/design_top/ddr4_reset_status.ip
set_global_assignment -name IP_FILE source/static_region/ip/pr_subsystem/pr_subsystem_clock_bridge_0.ip
set_global_assignment -name IP_FILE source/static_region/ip/pr_subsystem/pr_subsystem_reset_bridge_0.ip
set_global_assignment -name IP_FILE source/static_region/ip/pr_subsystem/pr_subsystem_pr_region_controller_0.ip
set_global_assignment -name IP_FILE source/static_region/ip/pr_subsystem/pr_subsystem_freeze_bridge_cra.ip
set_global_assignment -name IP_FILE source/static_region/ip/pr_subsystem/pr_subsystem_freeze_bridge_ddr4.ip
set_global_assignment -name IP_FILE source/static_region/ip/pr_subsystem/pr_subsystem_emif_clock_bridge.ip
set_global_assignment -name IP_FILE source/static_region/ip/pr_subsystem/pr_subsystem_sld_jtag_bridge_agent.ip
set_global_assignment -name QSYS_FILE source/common/reg_file/reg_file.qsys
set_global_assignment -name QSYS_FILE source/common/emif_interface/emif_avmm_interface.qsys
set_global_assignment -name IP_FILE source/common/reg_file/ip/reg_file/reg_file_clock_bridge.ip
set_global_assignment -name IP_FILE source/common/reg_file/ip/reg_file/reg_file_mm_bridge.ip
set_global_assignment -name IP_FILE source/common/reg_file/ip/reg_file/reg_file_pio_in.ip
set_global_assignment -name IP_FILE source/common/reg_file/ip/reg_file/reg_file_pio_out.ip
set_global_assignment -name IP_FILE source/common/reg_file/ip/reg_file/reg_file_reset_bridge.ip
set_global_assignment -name IP_FILE source/common/emif_interface/ip/emif_avmm_interface/emif_global_reset.ip
set_global_assignment -name IP_FILE source/common/emif_interface/ip/emif_avmm_interface/emif_avmm_interface_mm_bridge_0.ip
set_global_assignment -name IP_FILE source/common/emif_interface/ip/emif_avmm_interface/emif_avmm_interface_mm_clock_crossing_bridge.ip
set_global_assignment -name IP_FILE source/common/emif_interface/ip/emif_avmm_interface/pr_region_clock.ip
set_global_assignment -name IP_FILE source/common/emif_interface/ip/emif_avmm_interface/emif_avmm_interface_clock_in.ip
set_global_assignment -name IP_FILE source/common/emif_interface/ip/emif_avmm_interface/emif_avmm_interface_reset_in.ip
set_global_assignment -name IP_FILE source/static_region/ip/pr_subsystem/emif_pipeline_bridge.ip
set_global_assignment -name IP_FILE source/static_region/ip/pr_subsystem/emif_bridge.ip
#############################################################
# SDC constraints - Note they are after the Qsys files
#############################################################
set_global_assignment -name SDC_FILE auxiliary.sdc
#############################################################
# Pinouts
#############################################################
##LEDS
#set_location_assignment PIN_B19 -to green_leds[0]
#set_location_assignment PIN_E17 -to green_leds[1]
#set_location_assignment PIN_D18 -to green_leds[2]
#set_location_assignment PIN_D19 -to green_leds[3]
#set_location_assignment PIN_B18 -to red_leds[0]
#set_location_assignment PIN_F17 -to red_leds[1]
#set_location_assignment PIN_E18 -to red_leds[2]
#set_location_assignment PIN_E19 -to red_leds[3]
#set_instance_assignment -name IO_STANDARD "1.8 V" -to green_leds[0]
#set_instance_assignment -name IO_STANDARD "1.8 V" -to green_leds[1]
#set_instance_assignment -name IO_STANDARD "1.8 V" -to green_leds[2]
#set_instance_assignment -name IO_STANDARD "1.8 V" -to green_leds[3]
#set_instance_assignment -name IO_STANDARD "1.8 V" -to red_leds[0]
#set_instance_assignment -name IO_STANDARD "1.8 V" -to red_leds[1]
#set_instance_assignment -name IO_STANDARD "1.8 V" -to red_leds[2]
#set_instance_assignment -name IO_STANDARD "1.8 V" -to red_leds[3]
## Clocks
set_location_assignment PIN_BH33 -to config_clk_clk
set_instance_assignment -name IO_STANDARD "1.8 V" -to config_clk_clk -entity s10_pcie_ref_design
## DDR4A
set_location_assignment PIN_M35 -to pll_ref_clk
set_location_assignment PIN_P34 -to oct_rzqin
set_location_assignment PIN_L36 -to mem_ba[0]
set_location_assignment PIN_T35 -to mem_ba[1]
set_location_assignment PIN_R36 -to mem_bg[0]
set_location_assignment PIN_L40 -to mem_cke[0]
set_location_assignment PIN_F39 -to mem_ck[0]
set_location_assignment PIN_G39 -to mem_ck_n[0]
set_location_assignment PIN_G38 -to mem_cs_n[0]
set_location_assignment PIN_E40 -to mem_reset_n[0]
set_location_assignment PIN_G40 -to mem_odt[0]
set_location_assignment PIN_H38 -to mem_act_n[0]
set_location_assignment PIN_H40 -to mem_par[0]
set_location_assignment PIN_R33 -to mem_alert_n[0]
set_location_assignment PIN_K38 -to mem_a[0]
set_location_assignment PIN_L37 -to mem_a[1]
set_location_assignment PIN_M37 -to mem_a[2]
set_location_assignment PIN_M38 -to mem_a[3]
set_location_assignment PIN_J39 -to mem_a[4]
set_location_assignment PIN_J38 -to mem_a[5]
set_location_assignment PIN_K39 -to mem_a[6]
set_location_assignment PIN_L39 -to mem_a[7]
set_location_assignment PIN_P37 -to mem_a[8]
set_location_assignment PIN_R37 -to mem_a[9]
set_location_assignment PIN_N37 -to mem_a[10]
set_location_assignment PIN_P38 -to mem_a[11]
set_location_assignment PIN_P35 -to mem_a[12]
set_location_assignment PIN_K36 -to mem_a[13]
set_location_assignment PIN_K37 -to mem_a[14]
set_location_assignment PIN_N36 -to mem_a[15]
set_location_assignment PIN_P36 -to mem_a[16]
set_location_assignment PIN_T31 -to mem_dbi_n[0]
set_location_assignment PIN_M27 -to mem_dbi_n[1]
#Group0
set_location_assignment PIN_R34 -to mem_dq[0]
set_location_assignment PIN_R31 -to mem_dq[1]
set_location_assignment PIN_U33 -to mem_dq[2]
set_location_assignment PIN_U34 -to mem_dq[3]
set_location_assignment PIN_T34 -to mem_dq[4]
set_location_assignment PIN_U32 -to mem_dq[5]
set_location_assignment PIN_V32 -to mem_dq[6]
set_location_assignment PIN_P33 -to mem_dq[7]
set_location_assignment PIN_R32 -to mem_dqs[0]
set_location_assignment PIN_T32 -to mem_dqs_n[0]
#Group1
set_location_assignment PIN_H27 -to mem_dq[8]
set_location_assignment PIN_H26 -to mem_dq[9]
set_location_assignment PIN_J25 -to mem_dq[10]
set_location_assignment PIN_H25 -to mem_dq[11]
set_location_assignment PIN_L27 -to mem_dq[12]
set_location_assignment PIN_L26 -to mem_dq[13]
set_location_assignment PIN_G25 -to mem_dq[14]
set_location_assignment PIN_K27 -to mem_dq[15]
set_location_assignment PIN_J26 -to mem_dqs[1]
set_location_assignment PIN_K26 -to mem_dqs_n[1]
## PCIe
set_location_assignment PIN_AK41 -to ref_clk_clk
set_location_assignment PIN_AK40 -to "ref_clk_clk(n)"
set_instance_assignment -name IO_STANDARD HCSL -to ref_clk_clk -entity s10_pcie_ref_design
set_location_assignment PIN_AJ34 -to pcie_rstn_pin_perst
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to pcie_rstn_pin_perst -entity s10_pcie_ref_design
set_location_assignment PIN_BH41 -to hip_serial_rx_in[0]
set_location_assignment PIN_BJ43 -to hip_serial_rx_in[1]
set_location_assignment PIN_BG43 -to hip_serial_rx_in[2]
set_location_assignment PIN_BE43 -to hip_serial_rx_in[3]
set_location_assignment PIN_BC43 -to hip_serial_rx_in[4]
set_location_assignment PIN_BD45 -to hip_serial_rx_in[5]
set_location_assignment PIN_BA43 -to hip_serial_rx_in[6]
set_location_assignment PIN_BB45 -to hip_serial_rx_in[7]
set_location_assignment PIN_AW43 -to hip_serial_rx_in[8]
set_location_assignment PIN_AY45 -to hip_serial_rx_in[9]
set_location_assignment PIN_AU43 -to hip_serial_rx_in[10]
set_location_assignment PIN_AV45 -to hip_serial_rx_in[11]
set_location_assignment PIN_AR43 -to hip_serial_rx_in[12]
set_location_assignment PIN_AT45 -to hip_serial_rx_in[13]
set_location_assignment PIN_AP45 -to hip_serial_rx_in[14]
set_location_assignment PIN_AN43 -to hip_serial_rx_in[15]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to hip_serial_rx -entity s10_pcie_ref_design
set_location_assignment PIN_BJ46 -to hip_serial_tx_out[0]
set_location_assignment PIN_BF45 -to hip_serial_tx_out[1]
set_location_assignment PIN_BG47 -to hip_serial_tx_out[2]
set_location_assignment PIN_BE47 -to hip_serial_tx_out[3]
set_location_assignment PIN_BF49 -to hip_serial_tx_out[4]
set_location_assignment PIN_BC47 -to hip_serial_tx_out[5]
set_location_assignment PIN_BD49 -to hip_serial_tx_out[6]
set_location_assignment PIN_BA47 -to hip_serial_tx_out[7]
set_location_assignment PIN_BB49 -to hip_serial_tx_out[8]
set_location_assignment PIN_AW47 -to hip_serial_tx_out[9]
set_location_assignment PIN_AY49 -to hip_serial_tx_out[10]
set_location_assignment PIN_AU47 -to hip_serial_tx_out[11]
set_location_assignment PIN_AV49 -to hip_serial_tx_out[12]
set_location_assignment PIN_AR47 -to hip_serial_tx_out[13]
set_location_assignment PIN_AT49 -to hip_serial_tx_out[14]
set_location_assignment PIN_AP49 -to hip_serial_tx_out[15]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to hip_serial_tx_out -entity s10_pcie_ref_design
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X16"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name ENABLE_ED_CRC_CHECK ON
set_global_assignment -name MINIMUM_SEU_INTERVAL 0
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ
#############################################################
# Synthesis and Fitter Fine-Tuning
#############################################################
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
#############################################################
# SignalTap
#############################################################
# Note that enabling SignalTap may require changing the floorplan
#set_global_assignment -name ENABLE_SIGNALTAP ON
#set_global_assignment -name USE_SIGNALTAP_FILE s10_pcie_devkit_pr.stp
#set_global_assignment -name SIGNALTAP_FILE s10_pcie_devkit_pr.stp
#############################################################
# PR setup
#############################################################
set_global_assignment -name REVISION_TYPE PR_IMPL
#############################################################
# VID
#############################################################
set_global_assignment -name USE_PWRMGT_SCL SDM_IO14
set_global_assignment -name USE_PWRMGT_SDA SDM_IO11
set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ"
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTM4677
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 4F
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00
set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "AUTO DISCOVERY"
set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Pro Edition"