diff --git a/.gitmodules b/.gitmodules
index 63b41590..f8c2efe3 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -14,3 +14,6 @@
 [submodule "Vitis/examples/xilinx_2021.1"]
 	path = Vitis/examples/xilinx_2021.1
 	url = https://github.com/Xilinx/Vitis_Accel_Examples
+[submodule "Vitis/examples/xilinx_2021.2"]
+	path = Vitis/examples/xilinx_2021.2
+	url = https://github.com/Xilinx/Vitis_Accel_Examples
diff --git a/Jenkinsfile b/Jenkinsfile
index b08b0f6a..a285ea2a 100644
--- a/Jenkinsfile
+++ b/Jenkinsfile
@@ -126,15 +126,16 @@ task_label = [
 ]
 
 // Put the latest version last
-def xilinx_versions = [ '2021.1' ]
-def vitis_versions = ['2021.1' ]
+def xilinx_versions = [ '2021.2' ]
+def vitis_versions = ['2021.2' ]
 
 // We want the default to be the latest.
 def default_xilinx_version = xilinx_versions.last()
 
 def xsa_map = [
     '2020.2' : [ 'DYNAMIC':'dyn'],
-    '2021.1' : [ 'DYNAMIC':'dyn']
+    '2021.1' : [ 'DYNAMIC':'dyn'],
+    '2021.2' : [ 'DYNAMIC':'dyn']
 ]
 
 def vitis_example_default_map = [
@@ -161,6 +162,12 @@ def vitis_example_default_map = [
         'RTL_Vadd_Debug': 'Vitis/examples/xilinx/rtl_kernels/rtl_vadd_hw_debug',
         'gemm_blas': 'Vitis/examples/xilinx/library_examples/gemm'
     ],
+    '2021.2' : [
+        'Hello_World_1ddr': 'Vitis/examples/xilinx/ocl_kernels/cl_helloworld',
+        'Gmem_2Banks_2ddr': 'Vitis/examples/xilinx/ocl_kernels/cl_gmem_2banks',
+        'Kernel_Global_Bw_4ddr': 'Vitis/examples/xilinx/performance/kernel_global_bandwidth',
+        'RTL_Vadd_Debug': 'Vitis/examples/xilinx/rtl_kernels/rtl_vadd_hw_debug'
+    ],
 ]
 
 def simulator_tool_default_map = [
@@ -193,6 +200,12 @@ def simulator_tool_default_map = [
          'vcs': 'synopsys/vcs-mx/R-2020.12',
          'questa': 'questa/2020.4',
          'ies': 'incisive/15.20.083'
+     ],
+     '2021.2' : [
+         'vivado': 'xilinx/Vivado/2021.2',
+         'vcs': 'synopsys/vcs-mx/R-2020.12',
+         'questa': 'questa/2020.4',
+         'xcelium': '20.09.006'
      ]
 ]
 
diff --git a/Jenkinsfile_int_sims b/Jenkinsfile_int_sims
index eac43375..4b630781 100644
--- a/Jenkinsfile_int_sims
+++ b/Jenkinsfile_int_sims
@@ -36,7 +36,7 @@ task_label = [
 ]
 
 // Put the latest version last
-def xilinx_versions = [ '2021.1' ]
+def xilinx_versions = [ '2021.2' ]
 
 // We want the default to be the latest.
 def default_xilinx_version = xilinx_versions.last()
@@ -71,6 +71,12 @@ def simulator_tool_default_map = [
          'vcs': 'synopsys/vcs/R-2020.12',
          'questa': 'questa/2020.4',
          'ies': 'incisive/15.20.083'
+     ],
+     '2021.2' : [
+         'vivado': 'xilinx/Vivado/2021.2',
+         'vcs': 'synopsys/vcs/R-2020.12',
+         'questa': 'questa/2020.4',
+         'xcelium': 'xcelium/20.09.006'
      ]
 ]
 
@@ -156,7 +162,7 @@ if (test_sims) {
             def simulators = ['vivado']
             def sim_nodes = [:]
             if(params.internal_simulations) {
-                simulators = ['vcs', 'ies', 'questa', 'vivado']
+                simulators = ['vcs', 'xcelium', 'questa', 'vivado']
             }
 
             for (x in cl_names) {
@@ -165,7 +171,7 @@ if (test_sims) {
                         String xilinx_version = y
                         String cl_name = x
                         String simulator = z
-                        if((cl_name == 'cl_vhdl_hello_world') && (simulator == 'ies')) {
+                        if((cl_name == 'cl_vhdl_hello_world') && (simulator == 'xcelium')) {
                            println ("Skipping Simulator: ${simulator}  CL: ${cl_name}")
                            continue;
                         }
@@ -179,7 +185,7 @@ if (test_sims) {
                         def tool_module_map = simulator_tool_default_map.get(xilinx_version)
                         String vcs_module = tool_module_map.get('vcs')
                         String questa_module = tool_module_map.get('questa')
-                        String ies_module = tool_module_map.get('ies')
+                        String xcelium_module = tool_module_map.get('xcelium')
                         String vivado_module = tool_module_map.get('vivado')
 
                         if(params.internal_simulations) {
@@ -199,7 +205,7 @@ if (test_sims) {
                                         module load ${vivado_module}
                                         module load ${vcs_module}
                                         module load ${questa_module}
-                                        module load ${ies_module}
+                                        module load ${xcelium_module}
                                         source $WORKSPACE/hdk_setup.sh
                                         python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file} --simulator ${simulator} --batch 'TRUE'
                                         """
diff --git a/README.md b/README.md
index 8731cb65..1c3c5fab 100644
--- a/README.md
+++ b/README.md
@@ -50,16 +50,17 @@ AWS marketplace offers multiple versions of the FPGA Developer AMI. The followin
 
 ## Xilinx tool support
 
-| Developer Kit Version | Tool Version Supported | Compatible FPGA Developer AMI Version |
-|-----------|-----------|------|
-| 1.4.21+ | 2021.1 | v1.11.X (Xilinx Vivado/Vitis 2021.1) |
-| 1.4.18+ | 2020.2 | v1.10.X (Xilinx Vivado/Vitis 2020.2) |
-| 1.4.16+ | 2020.1 | v1.9.0-v1.9.X (Xilinx Vivado/Vitis 2020.1) |
-| 1.4.13+ | 2019.2 | v1.8.0-v1.8.X (Xilinx Vivado/Vitis 2019.2) |
-| 1.4.11+ | 2019.1 | v1.7.0-v1.7.X (Xilinx Vivado/SDx 2019.1) |
-| 1.4.8 - 1.4.15b | 2018.3 | v1.6.0-v1.6.X (Xilinx Vivado/SDx 2018.3) |
-| 1.4.3 - 1.4.15b | 2018.2 | v1.5.0-v1.5.X (Xilinx Vivado/SDx 2018.2) |
-|⚠️ 1.3.7 - 1.4.15b | 2017.4 | v1.4.0-v1.4.X (Xilinx Vivado/SDx 2017.4) ⚠️|
+| Developer Kit Version | Tool Version Supported | Compatible FPGA Developer AMI Version       |
+|-----------------------|------------------------|---------------------------------------------|
+| 1.4.23+               | 2021.2                 | v1.12.X (Xilinx Vivado/Vitis 2021.2)        |
+| 1.4.21+               | 2021.1                 | v1.11.X (Xilinx Vivado/Vitis 2021.1)        |
+| 1.4.18+               | 2020.2                 | v1.10.X (Xilinx Vivado/Vitis 2020.2)        |
+| 1.4.16+               | 2020.1                 | v1.9.0-v1.9.X (Xilinx Vivado/Vitis 2020.1)  |
+| 1.4.13+               | 2019.2                 | v1.8.0-v1.8.X (Xilinx Vivado/Vitis 2019.2)  |
+| 1.4.11+               | 2019.1                 | v1.7.0-v1.7.X (Xilinx Vivado/SDx 2019.1)    |
+| 1.4.8 - 1.4.15b       | 2018.3                 | v1.6.0-v1.6.X (Xilinx Vivado/SDx 2018.3)    |
+| 1.4.3 - 1.4.15b       | 2018.2                 | v1.5.0-v1.5.X (Xilinx Vivado/SDx 2018.2)    |
+| ⚠️ 1.3.7 - 1.4.15b    | 2017.4                 | v1.4.0-v1.4.X (Xilinx Vivado/SDx 2017.4) ⚠️ |
 
 ⚠️ Developer kit release v1.4.16 will remove support for Xilinx 2017.4, 2018.2, 2018.3 toolsets. While developer kit release v1.4.16 onwards will not support older Xilinx tools, you can still use them using HDK releases v1.4.15b or earlier. 
 Please check out [the latest v1.4.15b release tag from Github](https://github.com/aws/aws-fpga/releases/tag/v1.4.15b) to use Xilinx 2017.4, 2018.2, 2018.3 toolsets.
@@ -71,10 +72,10 @@ For software-defined development please look at the runtime compatibility table
 
 ### End of life Announcements
 
-| Xilinx Tool version | State | Statement | 
-|-----------|-----------|------|
-| 2017.1 | 🚫 Deprecated on 09/01/2018 | Developer kit versions prior to v1.3.7 and Developer AMI prior to v1.4 (2017.1) [reached end-of-life](https://forums.aws.amazon.com/ann.jspa?annID=6068). |
-| 2017.4 | ⚠️ Upcoming deprecation on 12/31/2021 | Support for Xilinx 2017.4 toolsets will be deprecated on 12/31/2021. Please check our [forum announcement for more details](https://forums.aws.amazon.com/ann.jspa?annID=8949). |
+| Xilinx Tool version | State | Statement                                                                                                                                                                 | 
+|-----------|-----------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| 2017.1 | 🚫 Deprecated on 09/01/2018 | Developer kit versions prior to v1.3.7 and Developer AMI prior to v1.4 (2017.1) [reached end-of-life](https://forums.aws.amazon.com/ann.jspa?annID=6068).                 |
+| 2017.4 | 🚫 Deprecated on 12/31/2021 | [Support for Xilinx 2017.4 toolsets was deprecated on 12/31/2021](https://forums.aws.amazon.com/ann.jspa?annID=8949). |
 
 ## Hardware Development Kit (HDK)
 
@@ -123,7 +124,7 @@ The [SDK directory](./sdk/README.md) includes the runtime environment required t
 * 1-8 Xilinx UltraScale+ VU9P based FPGA slots
 * Per FPGA Slot, Interfaces available for Custom Logic(CL):
     * One x16 PCIe Gen 3 Interface
-    * Four DDR4 RDIMM interfaces (with ECC)
+    * Four DDR4 RDIMM interfaces (72-bit with ECC, 16 GiB each; 64 GiB total)
     * AXI4 protocol support on all interfaces
 * User-defined clock frequency driving all CL to Shell interfaces
 * Multiple free running auxiliary clocks
@@ -219,8 +220,7 @@ Documentation is located throughout this developer kit and the table below conso
 
 # Developer Support
 
-* The [**Amazon FPGA Development User Forum**](https://forums.aws.amazon.com/forum.jspa?forumID=243&start=0) is the first place to go to post questions, learn from other users and read announcements.
-    * We recommend joining the [AWS forums](https://forums.aws.amazon.com/forum.jspa?forumID=243) to engage with the FPGA developer community, AWS and Xilinx engineers to get help.
+* [**AWS Re:Post**](https://repost.aws/) is the first place to go to post questions, learn from other users, to engage with the FPGA developer community, AWS and Xilinx engineers to get help.
 
-* You could also file a [Github Issue](https://github.com/aws/aws-fpga/issues) for support. We prefer the forums as this helps the entire community learn from issues, feedback and answers.
+* You could also file a [Github Issue](https://github.com/aws/aws-fpga/issues) for support. We prefer AWS Re:Post as this helps the entire community learn from issues, feedback and answers.
     * Click the "Watch" button in GitHub upper right corner to get regular updates.
diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md
index f00f7be2..173ec91b 100644
--- a/RELEASE_NOTES.md
+++ b/RELEASE_NOTES.md
@@ -2,6 +2,9 @@
 
 **NOTE:** See [ERRATA](./ERRATA.md) for unsupported features
 
+## Release 1.4.22
+* FPGA developer kit now supports Xilinx Vivado/Vitis 2021.2
+
 ## Release 1.4.22
 * FPGA developer kit update to upgrade Virtual Ethernet to support jumbo frames using newer versions of dpdk/pktgen
 
diff --git a/SDAccel/FAQ.md b/SDAccel/FAQ.md
index 3f41a2d6..5fcda5b9 100644
--- a/SDAccel/FAQ.md
+++ b/SDAccel/FAQ.md
@@ -82,25 +82,6 @@ A: We support creating AFI's from CL's that have been built to work at Frequenci
 # Additional Resources
 
 * The [AWS SDAccel README](README.md).
-* Xilinx web portal for [Xilinx SDAccel documentation](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html?resultsTablePreSelect=xlnxdocumenttypes:SeeAll#documentation) 
+* Xilinx web portal for [Xilinx SDAccel documentation](https://www.xilinx.com/products/design-tools/legacy-tools/sdaccel.html) 
 * [Xilinx SDAccel GitHub repository](https://github.com/Xilinx/SDAccel_Examples)
-
-* Links pointing to **2017.4** version of the user guides
-   * [UG1023: SDAccel Environment User Guide][UG1023 2017.4]
-   * [UG1021: SDAccel Environment Tutorial: Getting Started Guide (including emulation/build/running on H/W flow)][UG1021 2017.4]
-   * [UG1207: SDAccel Environment Optimization Guide][UG1207 2017.4]
-   * [UG1238: SDx Development Environment Release Notes, Installation, and Licensing Guide][UG1238 2017.4]
-   * [SDAccel_landing_page](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html)
-   * [Vivado HLS landing page](https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html
-   * [Vivado landing page](https://www.xilinx.com/products/design-tools/vivado.html)
-   * [SDAccel Environment User Guide](https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1023-sdaccel-user-guide.pdf)
-   * [SDAccel Intro Tutorial](https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1021-sdaccel-intro-tutorial.pdf)
-   * [SDAccel Environment Optimization Guide](https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1207-sdaccel-optimization-guide.pdf)
-   * [Vivado Design Methodology](https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug949-vivado-design-methodology.pdf)
-   * [2017.4 SDAccel User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1023-sdaccel-user-guide.pdf)
-   * [2017.4 SDAccel Intro Tutorial](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1021-sdaccel-intro-tutorial.pdf)
-   * [2017.4 SDAccel Environment Optimization Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1207-sdaccel-optimization-guide.pdf)
-   * [Xilinx SDAccel documentation](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html#documentation)
-   * [Xilinx SDAccel GitHub repository](https://github.com/Xilinx/SDAccel_Examples)
-   * [AWS SDAccel Readme](README.md)
-   * [Debug HLS Performance: Limited memory ports](./docs/SDAccel_HLS_Debug.md)
+* [Debug HLS Performance: Limited memory ports](./docs/SDAccel_HLS_Debug.md)
diff --git a/SDAccel/docs/On_Premises_Development_Steps.md b/SDAccel/docs/On_Premises_Development_Steps.md
index 27cc1255..c67a59df 100644
--- a/SDAccel/docs/On_Premises_Development_Steps.md
+++ b/SDAccel/docs/On_Premises_Development_Steps.md
@@ -138,40 +138,3 @@ The steps required to deploy and execute your uploaded applocation are the same
 - Execute your application
 
 All these are described in the [AWS SDAccel README]
-
-	
-# Additional Resources
-
-Xilinx web portal for [Xilinx SDAccel documentation] and for [Xilinx SDAccel GitHub repository]
-
-Links pointing to **2017.4** version of the user guides
-
-[UG1023: SDAccel Environment User Guide][UG1023 2017.4]
-
-[UG1021: SDAccel Environment Tutorial: Getting Started Guide (including emulation/build/running on H/W flow)][UG1021 2017.4]
-
-[UG1207: SDAccel Environment Optimization Guide][UG1207 2017.4]
-
-[UG1238: SDx Development Environment Release Notes, Installation, and Licensing Guide][UG1238 2017.4]
-
-[SDAccel_landing_page]: https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html
-[VHLS_landing_page]: https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html
-[Vivado_landing_page]: https://www.xilinx.com/products/design-tools/vivado.html
-
-[latest SDAccel Environment User Guide]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1023-sdaccel-user-guide.pdf
-[latest UG1021]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1021-sdaccel-intro-tutorial.pdf
-[latest SDAccel Environment Optimization Guide]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1207-sdaccel-optimization-guide.pdf
-[latest UG949]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug949-vivado-design-methodology.pdf
-[latest UG902]: https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug902-vivado-high-level-synthesis.pdf
-
-[UG1023 2017.4]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1023-sdaccel-user-guide.pdf
-[UG1021 2017.4]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1021-sdaccel-intro-tutorial.pdf
-[UG1207 2017.4]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1207-sdaccel-optimization-guide.pdf
-[UG1238 2017.4]:http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1238-sdx-rnil.pdf
-[Xilinx SDAccel documentation]: https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html#documentation
-[Xilinx SDAccel GitHub repository]: https://github.com/Xilinx/SDAccel_Examples
-
-[SDAccel download and License instructions]:https://github.com/aws/aws-fpga/blob/master/hdk/docs/on_premise_licensing_help.md
-[Vivado download]:https://www.xilinx.com/products/design-tools/acceleration-zone/ef-vivado-sdx-vu9p-op-fl-nl.html
-[SDAccel Download Page]: https://www.xilinx.com/registration/sign-in.html?oamProtectedResource=wh%3Dwww.xilinx.com%20wu%3D%2Fmember%2Fforms%2Fdownload%2Fxef.html%3Ffilename%3DXilinx_SDx_op_2017.1_sdx_0715_1_Lin64.bin%26akdm%3D0%20wo%3D1%20rh%3Dhttp%3A%2F%2Fwww.xilinx.com%20ru%3D%252Fmember%252Fforms%252Fdownload%252Fxef.html%20rq%3Dfilename%253DXilinx_SDx_op_2017.1_sdx_0715_1_Lin64.bin%2526akdm%253D0
-[AWS SDAccel Readme]: ../README.md
diff --git a/SDAccel/docs/SDAccel_Guide_AWS_F1.md b/SDAccel/docs/SDAccel_Guide_AWS_F1.md
index 0f7dab8e..1612da27 100644
--- a/SDAccel/docs/SDAccel_Guide_AWS_F1.md
+++ b/SDAccel/docs/SDAccel_Guide_AWS_F1.md
@@ -2,7 +2,7 @@
 *It is assumed that the reader has run the instructions found in the [AWS SDAccel README] successfully*
 
 
-This document provides a detailed reference to the [SDAccel Development Environment][SDAccel_landing_page] and its use with AWS F1 FPGA instances. 
+This document provides a detailed reference to the SDAccel Development Environment and its use with AWS F1 FPGA instances. 
 
 The SDAccel environment allows kernels expressed in OpenCL or C/C++ to be accelerated by implementing them in custom FPGA hardware. The flexible SDAccel Development Environment also allows the acceleration to be performed using pre-existing RTL designs. 
 
@@ -18,7 +18,7 @@ In addition, you can review the following useful documents:
 
 SDAccel uses a compiler named `xocc` which can be thought of as similar to the GNU gcc compiler -i.e. it allows you to compile source code to create Xilinx object (.xo) files and then can link said .xo files together to create an executable program; the .xo files contain an RTL representation of the accelerated kernels and the executable program is the design to be programmed onto the AWS F1 FPGA. 
 
-When the source code is OpenCL or C/C++ the [Vivado High-Level Synthesis (HLS)][VHLS_landing_page] tool is used under-the-hood to create the RTL that implements the custom hardware to meet the required performance and then an .xo file is created using the [Vivado toolchain][Vivado_landing_page].
+When the source code is OpenCL or C/C++ the Vivado High-Level Synthesis (HLS) tool is used under-the-hood to create the RTL that implements the custom hardware to meet the required performance and then an .xo file is created using the [Vivado toolchain][Vivado_landing_page].
 
 When the source code is RTL, the Vivado toolchain creates the .xo file directly without using Vivado HLS to generate any RTL description.
 
@@ -165,15 +165,8 @@ Conversely, code which is simply a few lines of basic operations, and has no tas
 # Additional Resources
 
 * The [AWS SDAccel README](../README.md).
-* Xilinx web portal for [Xilinx SDAccel documentation](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html?resultsTablePreSelect=xlnxdocumenttypes:SeeAll#documentation) 
 * [Xilinx SDAccel GitHub repository](https://github.com/Xilinx/SDAccel_Examples)
-* [Xilinx SDAccel landing page](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html)
-* [Vivado landing page](https://www.xilinx.com/products/design-tools/vivado.html)
-* [SDAccel Environment User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1023-sdaccel-user-guide.pdf)
-* [SDAccel Intro Tutorial](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1021-sdaccel-intro-tutorial.pdf)
-* [SDAccel Environment Optimization Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1207-sdaccel-optimization-guide.pdf)
-* [UltraFast Design Methodology Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug949-vivado-design-methodology.pdf)
-* [Vivado High Level Synthesis User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug902-vivado-high-level-synthesis.pdf)
+* [Xilinx SDAccel landing page](https://www.xilinx.com/products/design-tools/legacy-tools/sdaccel.html)
 * [On Premise Development steps](On_Premises_Development_Steps.md)
 * [SDAccel Power Analysis](SDAccel_Power_Analysis.md)
 * [FAQ](../FAQ.md)
diff --git a/Vitis/README.md b/Vitis/README.md
index 0e494430..bff27ce5 100644
--- a/Vitis/README.md
+++ b/Vitis/README.md
@@ -58,8 +58,8 @@ The F1 HW Target compile time is ~50 minutes, therefore, software and hardware e
 
 * Sourcing the *vitis_setup.sh* script:
   * Downloads and sets the correct AWS Platform:
-    * [AWS Vitis Platform](./aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_2) that contains the dynamic hardware that enables Vitis kernels to run on AWS F1 instances.
-    * Valid platforms for shell_v04261818: `AWS_PLATFORM_201920_2` (Default) AWS F1 Vitis platform.
+    * AWS Vitis Platform that contains the dynamic hardware that enables Vitis kernels to run on AWS F1 instances.
+    * Valid platforms for shell_v04261818: `AWS_PLATFORM_201920_3` (Default) AWS F1 Vitis platform.
   * Sets up the Xilinx Vitis example submodules.
   * Installs the required libraries and package dependencies.
   * Run environment checks to verify supported tool/lib versions.
diff --git a/Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_2/sw/xilinx_aws-vu9p-f1_shell-v04261818_201920_2.spfm b/Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_3/sw/xilinx_aws-vu9p-f1_shell-v04261818_201920_3.spfm
similarity index 96%
rename from Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_2/sw/xilinx_aws-vu9p-f1_shell-v04261818_201920_2.spfm
rename to Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_3/sw/xilinx_aws-vu9p-f1_shell-v04261818_201920_3.spfm
index 8cf04dce..4e70cb9f 100644
--- a/Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_2/sw/xilinx_aws-vu9p-f1_shell-v04261818_201920_2.spfm
+++ b/Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_3/sw/xilinx_aws-vu9p-f1_shell-v04261818_201920_3.spfm
@@ -2,7 +2,7 @@
 <sdx:platform sdx:vendor="xilinx"
               sdx:library="aws-vu9p-f1"
               sdx:name="shell-v04261818"
-              sdx:version="201920.2"
+              sdx:version="201920.3"
               sdx:schemaVersion="1.0"
               xmlns:sdx="http://www.xilinx.com/sdx">
   <sdx:description>
diff --git a/Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_2/xilinx_aws-vu9p-f1_shell-v04261818_201920_2.xpfm b/Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_3/xilinx_aws-vu9p-f1_shell-v04261818_201920_3.xpfm
similarity index 83%
rename from Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_2/xilinx_aws-vu9p-f1_shell-v04261818_201920_2.xpfm
rename to Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_3/xilinx_aws-vu9p-f1_shell-v04261818_201920_3.xpfm
index b0f9bee9..2d3a059b 100644
--- a/Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_2/xilinx_aws-vu9p-f1_shell-v04261818_201920_2.xpfm
+++ b/Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_3/xilinx_aws-vu9p-f1_shell-v04261818_201920_3.xpfm
@@ -2,7 +2,7 @@
 <sdx:platform sdx:vendor="xilinx"
               sdx:library="aws-vu9p-f1"
               sdx:name="shell-v04261818"
-              sdx:version="201920.2"
+              sdx:version="201920.3"
               sdx:schemaVersion="1.0"
               xmlns:sdx="http://www.xilinx.com/sdx">
   <sdx:description>
@@ -10,11 +10,11 @@
   </sdx:description>
 
   <sdx:hardwarePlatforms>
-    <sdx:hardwarePlatform sdx:path="hw" sdx:name="xilinx_aws-vu9p-f1_shell-v04261818_201920_2.xsa"/>
+    <sdx:hardwarePlatform sdx:path="hw" sdx:name="xilinx_aws-vu9p-f1_shell-v04261818_201920_3.xsa"/>
   </sdx:hardwarePlatforms>
 
   <sdx:softwarePlatforms>
-    <sdx:softwarePlatform sdx:path="sw" sdx:name="xilinx_aws-vu9p-f1_shell-v04261818_201920_2.spfm"/>
+    <sdx:softwarePlatform sdx:path="sw" sdx:name="xilinx_aws-vu9p-f1_shell-v04261818_201920_3.spfm"/>
   </sdx:softwarePlatforms>
 
 </sdx:platform>
diff --git a/Vitis/docs/Alveo_to_AWS_F1_Migration/example/README.md b/Vitis/docs/Alveo_to_AWS_F1_Migration/example/README.md
index c072c6bb..36783102 100644
--- a/Vitis/docs/Alveo_to_AWS_F1_Migration/example/README.md
+++ b/Vitis/docs/Alveo_to_AWS_F1_Migration/example/README.md
@@ -63,7 +63,7 @@ In order to port the vector-add example from Alveo U200 to AWS F1, the only chan
 2.  The `options.cfg` file for AWS F1 contains the following options:
 
     ```
-    platform=xilinx_aws-vu9p-f1_shell-v04261818_201920_2
+    platform=xilinx_aws-vu9p-f1_shell-v04261818_201920_3
     [connectivity]
     sp=vadd_1.in1:DDR[0]
     sp=vadd_1.in2:DDR[0]
@@ -88,7 +88,7 @@ In order to port the vector-add example from Alveo U200 to AWS F1, the only chan
     v++ -l -g -t hw -R 1 --config ./options.cfg --profile_kernel data:all:all:all --profile_kernel stall:all:all:all --temp_dir ./temp_dir --report_dir ./report_dir --log_dir ./log_dir -I../src vadd.hw.xo -o vadd.xclbin    
     ```
     
-    *NOTE: The PLATFORM_REPO_PATHS environment variable is used to specify the directory where the AWS platform (xilinx_aws-vu9p-f1_shell-v04261818_201920_2) is installed.*
+    *NOTE: The PLATFORM_REPO_PATHS environment variable is used to specify the directory where the AWS platform (xilinx_aws-vu9p-f1_shell-v04261818_201920_3) is installed.*
     
 4. When targeting AWS F1, you need to go through the additional step of creating an Amazon FPGA Image (AFI). This is done with the `create_vitis_afi.sh` command provided by AWS. More information about this command is available on the [AWS documentation](https://github.com/aws/aws-fpga/blob/master/Vitis/README.md#2-create-an-amazon-fpga-image-afi).     
 
diff --git a/Vitis/docs/Alveo_to_AWS_F1_Migration/example/f1/options.cfg b/Vitis/docs/Alveo_to_AWS_F1_Migration/example/f1/options.cfg
index a5eca86f..664131e0 100644
--- a/Vitis/docs/Alveo_to_AWS_F1_Migration/example/f1/options.cfg
+++ b/Vitis/docs/Alveo_to_AWS_F1_Migration/example/f1/options.cfg
@@ -1,4 +1,4 @@
-platform=xilinx_aws-vu9p-f1_shell-v04261818_201920_2
+platform=xilinx_aws-vu9p-f1_shell-v04261818_201920_3
 [connectivity]
 sp=vadd_1.in1:DDR[0]
 sp=vadd_1.in2:DDR[0]
diff --git a/Vitis/docs/Create_Runtime_AMI.md b/Vitis/docs/Create_Runtime_AMI.md
index b84dab0a..6a41c943 100644
--- a/Vitis/docs/Create_Runtime_AMI.md
+++ b/Vitis/docs/Create_Runtime_AMI.md
@@ -2,12 +2,13 @@
 
 ## Runtime AMI Compatibility Table
 
-| Vitis Version used for AFI Development | Compatible Xilinx Runtime |
-|--------------------------------------|-----------------------------|
-| 2021.1 | AWS FPGA Developer AMI 1.10.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2021.1/html/build.html) |
-| 2020.2 | AWS FPGA Developer AMI 1.10.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2020.2/html/build.html) |
-| 2020.1 | AWS FPGA Developer AMI 1.9.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2020.1/html/build.html) |
-| 2019.2 | AWS FPGA Developer AMI 1.8.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2019.2/html/build.html) |
+| Vitis Version used for AFI Development | Compatible Xilinx Runtime                                                                                          |
+|----------------------------------------|--------------------------------------------------------------------------------------------------------------------|
+| 2021.2                                 | AWS FPGA Developer AMI 1.12.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2021.2/html/build.html) |
+| 2021.1                                 | AWS FPGA Developer AMI 1.11.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2021.1/html/build.html) |
+| 2020.2                                 | AWS FPGA Developer AMI 1.10.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2020.2/html/build.html) |
+| 2020.1                                 | AWS FPGA Developer AMI 1.9.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2020.1/html/build.html)  |
+| 2019.2                                 | AWS FPGA Developer AMI 1.8.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2019.2/html/build.html)  |
 
 ## 1. Launch a Runtime Instance & Install Required Packages 
 
diff --git a/Vitis/examples/xilinx_2021.2 b/Vitis/examples/xilinx_2021.2
new file mode 160000
index 00000000..f61637e9
--- /dev/null
+++ b/Vitis/examples/xilinx_2021.2
@@ -0,0 +1 @@
+Subproject commit f61637e9263ecc1be3df34182ea6c53a0ca10447
diff --git a/Vitis/tools/create_vitis_afi.sh b/Vitis/tools/create_vitis_afi.sh
index 085490dc..3b096b21 100755
--- a/Vitis/tools/create_vitis_afi.sh
+++ b/Vitis/tools/create_vitis_afi.sh
@@ -215,7 +215,7 @@ clock_extra_c0=$(echo `grep -B 2 KERNEL_CLK ${timestamp}_clocks.json | grep -o -
 
 if [[ "$vendor" != "xilinx" && "$board_id" != "aws-vu9p-f1" && "$plat_name" != "shell-v04261818" && "$major" != "201920" && "$minor" != "2" ]]
 then                                 
-    err_msg "Platform ${vendor}_${board_id}_${plat_name}_${major}_${minor} used to create xclbin is not correct, you should be using xilinx_aws-vu9p-f1_shell-v04261818_201920_2"
+    err_msg "Platform ${vendor}_${board_id}_${plat_name}_${major}_${minor} used to create xclbin is not correct, you should be using xilinx_aws-vu9p-f1_shell-v04261818_201920_3"
     exit                                                                                              
 fi                                                                                                    
 
@@ -281,7 +281,7 @@ echo ${timestamp}_agfi_id.txt
 #Create .awsxclbin
 
 
-if [[ "$RELEASE_VER" == "2020.2" || "$RELEASE_VER" == "2021.1" ]]
+if [[ "$RELEASE_VER" == "2020.2" || "$RELEASE_VER" == "2021.1" || "$RELEASE_VER" == "2021.2" ]]
 then
 	/opt/xilinx/xrt/bin/xclbinutil -i $xclbin --remove-section PARTITION_METADATA --replace-section BITSTREAM:RAW:${timestamp}_agfi_id.txt -o ${awsxclbin}.awsxclbin
 else
diff --git a/Vitis/vitis_xrt_version.txt b/Vitis/vitis_xrt_version.txt
index 7da906d3..679bb8da 100644
--- a/Vitis/vitis_xrt_version.txt
+++ b/Vitis/vitis_xrt_version.txt
@@ -3,3 +3,4 @@
 2020.1:d09c4a458c16e8d843b3165dcf929c38f7a32b6f
 2020.2:77d5484b5c4daa691a7f78235053fb036829b1e9
 2021.1:5ad5998d67080f00bca5bf15b3838cf35e0a7b26
+2021.2:723d9e7abbe3a2c374682dbb1a59c47f230f3ee2
diff --git a/docs/examples/example_list.md b/docs/examples/example_list.md
index 61ae69e5..88a1f52a 100644
--- a/docs/examples/example_list.md
+++ b/docs/examples/example_list.md
@@ -9,9 +9,6 @@
 | Custom hardware | [Pipelined Workload Applications - cl\_dram\_dma\_data\_retention](../../hdk/docs/data_retention.md)| [HDK](../../hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma_retention.c) [SDAccel](../../SDAccel/examples/aws/data_retention) | Demonstrates how to preserve data in DRAMs while swapping out accelerators. Applications that use a temporal accelerator pipeline can take advantage of this feature to reduce latency between FPGA image swaps  |
 | High Level Synthesis | [Digital Up-Converter - cl\_hls\_dds\_hlx](../../hdk/cl/examples/cl_hls_dds_hlx) | HLx - C-to-RTL  | Demonstrates an example application written in C that is synthesized to RTL (Verilog) |
 | Custom Hardware with Software Defined Acceleration | [RTL Kernels](https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/rtl_kernels) | Vitis - RTL (Verilog) + C/C++/OpenCL  | These examples demonstrate developing new hardware designs (RTL) in a Software Defined workflow|
-| Vitis Compression Libraries | [File Compression using GZip](https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/library_examples/gzip_app) | Vitis - C/C++/OpenCL  | This example demonstrates how to use Vitis Libraries to speed up GZIP compression on an FPGA |
-| Vitis Financial libraries | [Monte Carlo European Engine](https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/library_examples/MCEuropeanEngine) | Vitis - C/C++/OpenCL  | This example shows how to use Vitis Financial Libraries to accelerate MCEuropean Engine on an FPGA|
-
 ## Application Notes 
 
 App Note | Description |
diff --git a/hdk/docs/AFI_Manifest.md b/hdk/docs/AFI_Manifest.md
index 4fa568c0..bb9eea59 100644
--- a/hdk/docs/AFI_Manifest.md
+++ b/hdk/docs/AFI_Manifest.md
@@ -38,13 +38,14 @@ The manifest file is a text file formatted with key=value pairs. Some keys are m
 * **tool_version=**.....   [Mandatory]
   * use vivado tool version with below table as a reference
      
-| vivado tool version | field value |
-|------------------- | -----------|
-| 2021.1 |  tool_version=v2021.1 |
-| 2020.2 |  tool_version=v2020.2 |
-| 2020.1 |  tool_version=v2020.1 |
-| 2019.2 |  tool_version=v2019.2 |
-| 2019.1 |  tool_version=v2019.1 |
+| vivado tool version | field value          |
+|---------------------|----------------------|
+| 2021.2              | tool_version=v2021.2 |
+| 2021.1              | tool_version=v2021.1 |
+| 2020.2              | tool_version=v2020.2 |
+| 2020.1              | tool_version=v2020.1 |
+| 2019.2              | tool_version=v2019.2 |
+| 2019.1              | tool_version=v2019.1 |
              
 * **date=** YY_MM_DD-HHMMSS         
      *Following same format used in the automatic build reports used by AWS scripts*
diff --git a/hdk/docs/RTL_Simulating_CL_Designs.md b/hdk/docs/RTL_Simulating_CL_Designs.md
index 13dfc853..3d4c1053 100644
--- a/hdk/docs/RTL_Simulating_CL_Designs.md
+++ b/hdk/docs/RTL_Simulating_CL_Designs.md
@@ -4,12 +4,14 @@
 
 Developers tend to simulate their designs to validate the RTL design and functionality, before hitting the build stage and registering it with AWS EC2 as Amazon FPGA Image (AFI). AWS FPGA HDK comes with a shell simulation model that supports RTL-level simulation using Xilinx' Vivado XSIM,  MentorGraphics' Questa, Cadence Incisive and Synopsys' VCS RTL simulators. See table below for supported simulator versions. 
 
-| Simulator | Vivado 2019.1 |  Vivado 2019.2 | Vivado 2020.1 | Vivado 2020.2 | Vivado 2021.1 | 
-|-----------| --- | --- | --- | --- | --- |
-| Xilinx Vivado XSIM | Vivado v2019.1 | Vivado v2019.2 | Vivado v2020.1 | Vivado v2020.2 | Vivado v2021.1 |
-| Synopsys VCS | O-2018.09 | O-2018.09-SP2-1 | P-2019.06-SP1-1 | Q-2020.03 | R-2020.12 | 
-| Mentor Graphics Questa | 10.7c | 2019.2 | 2019.4 | 2020.2 | 2020.4 |
-| Cadence Incisive Enterprise Simulator(IES) | 15.20.065 | 15.20.073 | 15.20.079 | 15.20.083 | 15.20.083 |
+| Simulator                                  | Vivado 2019.1  | Vivado 2019.2   | Vivado 2020.1   | Vivado 2020.2  | Vivado 2021.1  | Vivado 2021.2 | 
+|--------------------------------------------|----------------|-----------------|-----------------|----------------|----------------|---------------|
+| Xilinx Vivado XSIM                         | Vivado v2019.1 | Vivado v2019.2  | Vivado v2020.1  | Vivado v2020.2 | Vivado v2021.1 | Vivado v2021.2 |
+| Synopsys VCS                               | O-2018.09      | O-2018.09-SP2-1 | P-2019.06-SP1-1 | Q-2020.03      | R-2020.12      | R-2020.12 |
+| Mentor Graphics Questa                     | 10.7c          | 2019.2          | 2019.4          | 2020.2         | 2020.4         | 2020.4 |
+| Cadence Incisive Enterprise Simulator(IES) | 15.20.065      | 15.20.073       | 15.20.079       | 15.20.083      | 15.20.083      | N/A |
+| Cadence Xcelium Parallel Simulator         | N/A            | N/A             | N/A             | N/A            | N/A            | 20.09.006 |
+
 
 Developers can write their tests in SystemVerilog and/or C languages. If a developer chooses to use the supplied C framework, he/she can use the same C code for simulation and for runtime on your FPGA-enabled instance like F1.
 
diff --git a/hdk/hdk_version.txt b/hdk/hdk_version.txt
index 79097eab..10f34b6c 100644
--- a/hdk/hdk_version.txt
+++ b/hdk/hdk_version.txt
@@ -1 +1 @@
-HDK_VERSION=1.4.22
+HDK_VERSION=1.4.23
diff --git a/hdk/tests/simulation_tests/run_sim.sh b/hdk/tests/simulation_tests/run_sim.sh
index ee2b5a0a..a882ae2f 100755
--- a/hdk/tests/simulation_tests/run_sim.sh
+++ b/hdk/tests/simulation_tests/run_sim.sh
@@ -65,7 +65,7 @@ vivado_version=${vivado_version//./_}
 if [ $batch == "TRUE" ]; then
 # COMMAND="batch_submit.py -q vcs-lo --jd Cad-centos7_2 --jn github_regress_${test_name}_${test_type}_${vivado_version}_${simulator} --wait --echo -c make"
 # COMMAND="sbatch -c 1 --mem 64GB -p regress -J github_regress_${test_name}_${test_type}_${vivado_version}_${simulator} -L VCSMXRunTime_Net -W -o ${test_name}_${test_type}_${simulator}.stdout.sim.log -e ${test_name}_${test_type}_${simulator}.stderr.sim.log sbatch_wrap.sh make"
-COMMAND="srun -c 1 --mem 64GB --time 160 -p regress -J github_regress_${test_name}_${test_type}_${vivado_version}_${simulator} -L VCSMXRunTime_Net make"
+COMMAND="srun -c 1 --mem 64GB --time 160 -p verif_regress -J github_regress_${test_name}_${test_type}_${vivado_version}_${simulator} -L VCSMXRunTime_Net make"
 
 else
 COMMAND="make"
diff --git a/hdk/tests/test_create_afi.py b/hdk/tests/test_create_afi.py
index 9655f9b1..5b695f52 100644
--- a/hdk/tests/test_create_afi.py
+++ b/hdk/tests/test_create_afi.py
@@ -141,7 +141,7 @@ def test_cl_hello_world_vhdl(self, xilinxVersion):
     @pytest.mark.parametrize("uram_option", AwsFpgaTestBase.DCP_URAM_OPTIONS)
     def test_cl_uram_example(self, xilinxVersion, uram_option):
         cl = 'cl_uram_example'
-        self.base_test(cl, xilinxVersion, clock_recipe_a='A2', uram_option=uram_option)
+        self.base_test(cl, xilinxVersion, clock_recipe_a='A0', uram_option=uram_option)
 
     @pytest.mark.parametrize("build_strategy", AwsFpgaTestBase.DCP_BUILD_STRATEGIES)
     @pytest.mark.parametrize("clock_recipe_c", sorted(AwsFpgaTestBase.DCP_CLOCK_RECIPES['C']['recipes'].keys()))
diff --git a/hdk/tests/test_gen_dcp.py b/hdk/tests/test_gen_dcp.py
index 4f968661..1fa95dd9 100644
--- a/hdk/tests/test_gen_dcp.py
+++ b/hdk/tests/test_gen_dcp.py
@@ -103,6 +103,8 @@ def set_allowed_warnings(cls):
             (('.*',), r'WARNING: \[Synth 8-7071\] .*'),
             (('.*',), r'WARNING: \[Synth 8-7129\] .*'),
             (('.*',), r'WARNING: \[Route 35-3387\] .*'),
+            (('.*',), r'WARNING: \[Synth 8-6779\] .*'),
+            (('.*',), r'WARNING: \[Synth 8-7080\] .*'),
             (('cl_sde_*',), r'WARNING: \[Vivado 12-180\] No cells matched .*'),
             (('cl_sde_*',), r'WARNING: \[Vivado 12-1008\] No clocks found for command.*'),
             (('cl_sde_*',), r'CRITICAL WARNING: \[Designutils 20-1280\] .*'),
@@ -364,7 +366,7 @@ def test_cl_hello_world_vhdl(self, xilinxVersion):
     def test_cl_uram_example(self, xilinxVersion, uram_option):
         cl = 'cl_uram_example'
         logger.info("uram_option={}".format(uram_option))
-        self.base_test(cl, xilinxVersion, clock_recipe_a='A2', uram_option=uram_option)
+        self.base_test(cl, xilinxVersion, clock_recipe_a='A0', uram_option=uram_option)
 
     @pytest.mark.parametrize("build_strategy", AwsFpgaTestBase.DCP_BUILD_STRATEGIES)
     @pytest.mark.parametrize("clock_recipe_c", sorted(AwsFpgaTestBase.DCP_CLOCK_RECIPES['C']['recipes'].keys()))
diff --git a/hdk/tests/test_load_afi.py b/hdk/tests/test_load_afi.py
index c2d47f36..c01cc7db 100644
--- a/hdk/tests/test_load_afi.py
+++ b/hdk/tests/test_load_afi.py
@@ -324,7 +324,7 @@ def test_cl_hello_world_vhdl(self, xilinxVersion):
     @pytest.mark.parametrize("uram_option", AwsFpgaTestBase.DCP_URAM_OPTIONS)
     def test_cl_uram_example(self, xilinxVersion, uram_option):
         cl = 'cl_uram_example'
-        self.base_fdf_test(cl, xilinxVersion, clock_recipe_a='A2', uram_option=uram_option, install_xdma_driver=False)
+        self.base_fdf_test(cl, xilinxVersion, clock_recipe_a='A0', uram_option=uram_option, install_xdma_driver=False)
 
     @pytest.mark.parametrize("build_strategy", AwsFpgaTestBase.DCP_BUILD_STRATEGIES)
     @pytest.mark.parametrize("clock_recipe_c", sorted(AwsFpgaTestBase.DCP_CLOCK_RECIPES['C']['recipes'].keys()))
diff --git a/shared/lib/aws_fpga_test_utils/AwsFpgaTestBase.py b/shared/lib/aws_fpga_test_utils/AwsFpgaTestBase.py
index 8d8156d5..2cb0886f 100644
--- a/shared/lib/aws_fpga_test_utils/AwsFpgaTestBase.py
+++ b/shared/lib/aws_fpga_test_utils/AwsFpgaTestBase.py
@@ -263,7 +263,7 @@ def get_sdaccel_xclbin_dir(examplePath):
 
     @staticmethod
     def get_vitis_xclbin_dir(examplePath, target='hw'):
-        return os.path.join(AwsFpgaTestBase.get_sdaccel_example_fullpath(examplePath=examplePath), "build_dir.{}.xilinx_aws-vu9p-f1_shell-v04261818_201920_2".format(target))
+        return os.path.join(AwsFpgaTestBase.get_sdaccel_example_fullpath(examplePath=examplePath), "build_dir.{}.xilinx_aws-vu9p-f1_shell-v04261818_201920_3".format(target))
 
     @staticmethod
     def get_sdaccel_example_s3_root_tag(examplePath, target, rteName, xilinxVersion):
@@ -438,7 +438,7 @@ def get_vitis_example_run_cmd(examplePath, xilinxVersion):
 
         if launch_description[0].get("cmd_args", None):
             run_cmd += " {}".format(((launch_description[0].get("cmd_args", None).replace(".xclbin", ".awsxclbin")).replace(
-                        "PROJECT", ".")).replace("BUILD", "./build_dir.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2")).replace(
+                        "PROJECT", ".")).replace("BUILD", "./build_dir.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_3")).replace(
                 "REPO_DIR", AwsFpgaTestBase.get_vitis_example_base_dir(xilinxVersion))
 
         assert run_cmd is not None, "Could not find run_cmd(em_cmd) or (host_exe) in the example description here {}".format(
diff --git a/supported_vivado_versions.txt b/supported_vivado_versions.txt
index 9b8c0301..968172de 100644
--- a/supported_vivado_versions.txt
+++ b/supported_vivado_versions.txt
@@ -9,3 +9,4 @@ Vivado v2019.2_AR73068 (64-bit)
 Vivado v2020.1 (64-bit)
 Vivado v2020.2 (64-bit)
 Vivado v2021.1 (64-bit)
+Vivado v2021.2 (64-bit)
diff --git a/vitis_runtime_setup.sh b/vitis_runtime_setup.sh
index 9decc206..99c387c5 100644
--- a/vitis_runtime_setup.sh
+++ b/vitis_runtime_setup.sh
@@ -142,7 +142,7 @@ info_msg "VIVADO_TOOL_VERSION is $VIVADO_TOOL_VERSION"
 check_kernel_ver
 check_xdma_driver
 
-if [[ "$VIVADO_TOOL_VERSION" =~ .*2019\.2.*  || "$VIVADO_TOOL_VERSION" =~ .*2020\.1.* || "$VIVADO_TOOL_VERSION" =~ .*2020\.2.* || "$VIVADO_TOOL_VERSION" =~ .*2021\.1.* ]]; then
+if [[ "$VIVADO_TOOL_VERSION" =~ .*2019\.2.*  || "$VIVADO_TOOL_VERSION" =~ .*2020\.* || "$VIVADO_TOOL_VERSION" =~ .*2021\.*  ]]; then
     info_msg "Xilinx Vivado version is $VIVADO_TOOL_VERSION"
 
     if [ $override == 1 ]; then
@@ -183,7 +183,7 @@ if [[ "$VIVADO_TOOL_VERSION" =~ .*2019\.2.*  || "$VIVADO_TOOL_VERSION" =~ .*2020
        return 1
     fi
 else
-   err_msg "Xilinx Vivado version is $VIVADO_TOOL_VERSION , only 2019.2, 2020.1, 2020.2 or 2021.1 are supported for Vitis "
+   err_msg "Xilinx Vivado version is $VIVADO_TOOL_VERSION , only 2019.2, 2020.1, 2020.2, 2021.1 or 2021.2 are supported for Vitis "
    return 1
 fi
 
diff --git a/vitis_setup.sh b/vitis_setup.sh
index 486d3955..354e6cfb 100644
--- a/vitis_setup.sh
+++ b/vitis_setup.sh
@@ -171,7 +171,7 @@ setup_patches
 
 # Update Xilinx Vitis Examples from GitHub
 info_msg "Using Vitis $RELEASE_VER"
-if [[ $RELEASE_VER =~ .*2019\.2.*  ||  $RELEASE_VER =~ .*2020\.1.* ||  $RELEASE_VER =~ .*2020\.2.* ||  $RELEASE_VER =~ .*2021\.1.* ]]; then
+if [[ $RELEASE_VER =~ .*2019\.2.*  ||  $RELEASE_VER =~ .*2020\.* ||  $RELEASE_VER =~ .*2021\.* ]]; then
     info_msg "Updating Xilinx Vitis Examples $RELEASE_VER"
     git submodule update --init -- Vitis/examples/xilinx_$RELEASE_VER
     export VIVADO_TOOL_VER=$RELEASE_VER
@@ -183,7 +183,7 @@ if [[ $RELEASE_VER =~ .*2019\.2.*  ||  $RELEASE_VER =~ .*2020\.1.* ||  $RELEASE_
     fi
     ln -sf $VITIS_DIR/examples/xilinx_$RELEASE_VER $VITIS_DIR/examples/xilinx
 else
-   echo " $RELEASE_VER is not supported (2019.2, 2020.1, 2020.2 or 2021.1 are supported).\n"
+   echo " $RELEASE_VER is not supported (2019.2, 2020.1, 2020.2, 2021.1 or 2021.2 are supported).\n"
    return 2
 fi
 
@@ -275,17 +275,17 @@ function setup_xsa {
     fi
 }
 
-    #-------------------201920_2 Vitis Platform----------------------
-    setup_xsa xilinx_aws-vu9p-f1_shell-v04261818_201920_2 xsa_v121319_shell_v04261818 AWS_PLATFORM_201920_2
-    info_msg "AWS Platform: 201920_2 Vitis Platform is up-to-date"
-    #-------------------201920_2 Vitis Platform----------------------
+    #-------------------201920_3 Vitis Platform----------------------
+    setup_xsa xilinx_aws-vu9p-f1_shell-v04261818_201920_3 xsa_v121319_shell_v04261818 AWS_PLATFORM_201920_3
+    info_msg "AWS Platform: 201920_3 Vitis Platform is up-to-date"
+    #-------------------201920_3 Vitis Platform----------------------
 
 
 # Setup XRT as we need it for building
 setup_runtime
 
-export AWS_PLATFORM=$AWS_PLATFORM_201920_2
-info_msg "The default AWS Platform has been set to: \"AWS_PLATFORM=\$AWS_PLATFORM_201920_2\" "
+export AWS_PLATFORM=$AWS_PLATFORM_201920_3
+info_msg "The default AWS Platform has been set to: \"AWS_PLATFORM=\$AWS_PLATFORM_201920_3\" "
 
 info_msg "Vitis Setup PASSED"