diff --git a/FAQs.md b/FAQs.md index fa74c10a..5313387f 100644 --- a/FAQs.md +++ b/FAQs.md @@ -460,14 +460,9 @@ Parent process (pid 8160) has died. This helper process will now exit You would need a valid [on premise license](./hdk/docs/on_premise_licensing_help.md) provided by Xilinx. -*For runs using the FPGA Developer AMI:* - -**NOTE:** -> * The license included on FPGA Developer AMI Versions 1.3.0_a and earlier expires on October 31 2017. -> * If you see the above error, please update to FPGA Developer AMI Version 1.3.3 or later. -> * All FPGA Developer AMI Versions 1.3.0_a and earlier will be deprecated once Version 1.3.3 is released. -> * If you are using the FPGA Developer AMI Version 1.3.3 or later, please check if the environment variable `XILINXD_LICENSE_FILE` is set to `/opt/Xilinx/license/XilinxAWS.lic` -> * If you still face the above error, please contact us on the forums and we'd be happy to help further. +*For runs using the FPGA Developer AMI:* Please contact us through [AWS FPGA Developers forum](https://forums.aws.amazon.com/forum.jspa?forumID=243) + + **Q: Why does Vivado in GUI mode show up blank ? or Why does Vivado in GUI mode show up as an empty window?** diff --git a/Jenkinsfile b/Jenkinsfile index b56377ab..163b2f9b 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -11,6 +11,7 @@ properties([parameters([ booleanParam(name: 'test_hdk_scripts', defaultValue: true, description: 'Test the HDK setup scripts'), booleanParam(name: 'test_sims', defaultValue: true, description: 'Run all Simulations'), booleanParam(name: 'test_edma', defaultValue: true, description: 'Run EDMA unit and perf tests'), + booleanParam(name: 'test_non_root_access', defaultValue: true, description: 'Test non-root access to FPGA tools'), booleanParam(name: 'test_xdma', defaultValue: true, description: 'Test XDMA driver'), booleanParam(name: 'test_runtime_software', defaultValue: true, description: 'Test precompiled AFIs'), booleanParam(name: 'test_dcp_recipes', defaultValue: false, description: 'Run DCP generation with all clock recipes and build strategies.'), @@ -22,8 +23,8 @@ properties([parameters([ booleanParam(name: 'debug_fdf_uram', defaultValue: false, description: 'Debug the FDF for cl_uram_example.'), booleanParam(name: 'fdf_ddr_comb', defaultValue: false, description: 'run FDF for cl_dram_dma ddr combinations.'), booleanParam(name: 'disable_runtime_tests', defaultValue: false, description: 'Option to disable runtime tests.'), - booleanParam(name: 'use_test_ami', defaultValue: false, description: 'This option asks for the test AMI from Jenkins') - + booleanParam(name: 'use_test_ami', defaultValue: false, description: 'This option asks for the test AMI from Jenkins'), + booleanParam(name: 'internal_simulations', defaultValue: false, description: 'This option asks for default agent from Jenkins') ])]) //============================================================================= @@ -35,6 +36,7 @@ boolean test_hdk_scripts = params.get('test_hdk_scripts') boolean test_fpga_tools = params.get('test_fpga_tools') boolean test_sims = params.get('test_sims') boolean test_edma = params.get('test_edma') +boolean test_non_root_access = params.get('test_non_root_access') boolean test_xdma = params.get('test_xdma') boolean test_runtime_software = params.get('test_runtime_software') boolean test_dcp_recipes = params.get('test_dcp_recipes') @@ -102,14 +104,14 @@ def all_tests = [:] // Task to Label map task_label = [ 'create_afi': 't2.l_50', - 'simulation': 'c4.xl', - 'dcp_gen': 'c4.4xl', + 'simulation': 'z1d.l', + 'dcp_gen': 'z1d.2xl', 'runtime': 'f1.2xl', 'runtime_all_slots': 'f1.16xl', 'source_scripts': 'c4.xl', 'md_links': 'c4.xl', 'find_tests': 't2.l_50', - 'sdaccel_builds': 'c4.4xl' + 'sdaccel_builds': 'z1d.2xl' ] def xilinx_versions = [ '2017.4', '2018.2' ] @@ -133,6 +135,19 @@ def sdaccel_example_default_map = [ '2017.4' : [ 'Hello_World_1ddr': 'SDAccel/ex ] ] +def simulator_tool_default_map = [ '2017.4' : [ 'vivado': 'xilinx/SDx/2017.4_04112018', + 'vcs': 'vcs-mx/L-2016.06-1', + 'questa': 'questa/10.6b', + 'ies': 'incisive/15.20.063' + ], + '2018.2' : [ 'vivado': 'xilinx/SDx/2018.2_06142018', + 'vcs': 'vcs-mx/N-2017.12-SP1-1', + 'questa': 'questa/10.6c_1', + 'ies': 'incisive/15.20.063' + ] +] + + // Get serializable entry set @NonCPS def entrySet(m) {m.collect {k, v -> [key: k, value: v]}} @@ -150,6 +165,10 @@ def get_task_label(Map args=[ : ]) { echo "Test AMI Requested" task_label = task_label + '_test' } + if (params.internal_simulations) { + echo "internal simulation agent requested" + task_label = 'f1' + } echo "Label Requested: $task_label" return task_label @@ -341,27 +360,56 @@ if (test_fpga_tools) { } } + if (test_sims) { all_tests['Run Sims'] = { stage('Run Sims') { def cl_names = ['cl_uram_example', 'cl_dram_dma', 'cl_hello_world'] + def simulators = ['vivado'] def sim_nodes = [:] + if(params.internal_simulations) { + simulators = ['vcs', 'ies', 'questa', 'vivado'] + } for (x in cl_names) { for (y in xilinx_versions) { - String xilinx_version = y - String cl_name = x - String node_name = "Sim ${cl_name} ${xilinx_version}" - String key = "test_${cl_name}__" - String report_file = "test_sims_${cl_name}_${xilinx_version}.xml" - sim_nodes[node_name] = { + for ( z in simulators) { + String xilinx_version = y + String cl_name = x + String simulator = z + String node_name = "Sim ${cl_name} ${xilinx_version}" + String key = "test_${cl_name}__" + String report_file = "test_sims_${cl_name}_${xilinx_version}.xml" + def tool_module_map = simulator_tool_default_map.get(xilinx_version) + String vcs_module = tool_module_map.get('vcs') + String questa_module = tool_module_map.get('questa') + String ies_module = tool_module_map.get('ies') + String vivado_module = tool_module_map.get('vivado') + if(params.internal_simulations) { + report_file = "test_sims_${cl_name}_${xilinx_version}_${simulator}.xml" + } + sim_nodes[node_name] = { node(get_task_label(task: 'simulation', xilinx_version: xilinx_version)) { checkout scm try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_hdk_env.sh - python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file} - """ + if(params.internal_simulations) { + sh """ + set -e + module purge + module load python/2.7.9 + module load ${vivado_module} + module load ${vcs_module} + module load ${questa_module} + module load ${ies_module} + source $WORKSPACE/hdk_setup.sh + python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file} --Simulator ${simulator} + """ + } else { + sh """ + set -e + source $WORKSPACE/shared/tests/bin/setup_test_hdk_env.sh + python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file} --Simulator ${simulator} + """ + } } catch (exc) { echo "${node_name} failed: archiving results" archiveArtifacts artifacts: "hdk/cl/examples/${cl_name}/verif/sim/**", fingerprint: true @@ -377,6 +425,7 @@ if (test_sims) { } } } + } } parallel sim_nodes } @@ -420,6 +469,39 @@ if (test_edma) { } } +if (test_non_root_access) { + all_tests['Test non-root access to FPGA tools'] = { + stage('Test non-root access to FPGA tools') { + node(get_task_label(task: 'runtime', xilinx_version: default_xilinx_version)) { + + echo "Test non-root access to FPGA tools" + checkout scm + + String test = "sdk/tests/test_non_root_access.py" + String report_file = "test_non_root_access.xml" + + try { + sh """ + export AWS_FPGA_ALLOW_NON_ROOT=y + export AWS_FPGA_SDK_OVERRIDE_GROUP=y + set -e + source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh + newgrp fpgauser + export SDK_DIR="${WORKSPACE}/sdk" + source $WORKSPACE/shared/tests/bin/setup_test_env.sh + python2.7 -m pytest -v $WORKSPACE/${test} --junit-xml $WORKSPACE/${report_file} + """ + } catch (exc) { + input message: "Non-root access test failed. Click Proceed or Abort when you are done debugging on the instance." + throw exc + } finally { + junit healthScaleFactor: 10.0, testResults: report_file + } + } + } + } +} + if (test_xdma) { all_tests['Test XDMA Driver'] = { stage('Test XDMA Driver') { diff --git a/README.md b/README.md index 9b305cc9..aaf8a448 100644 --- a/README.md +++ b/README.md @@ -141,7 +141,6 @@ The [SDK directory](./sdk/README.md) includes the runtime environment required t * Linux Kernel Drivers - The developer kit includes three drivers: * [XDMA Driver](sdk/linux_kernel_drivers/xdma/README.md) - DMA interface to/from HDK accelerators. * [XOCL Driver](sdk/linux_kernel_drivers/xocl) - DMA interface with software defined accelerators (also called hardware kernels). - * [EDMA Driver](sdk/linux_kernel_drivers/edma/README.md) - Legacy DMA interface to/from HDK accelerators. * [FPGA Libraries](sdk/userspace/fpga_libs) - APIs used by C/C++ host applications. * [FPGA Management Tools](sdk/userspace/fpga_mgmt_tools/README.md) - AFI management APIs for runtime loading/clearing FPGA image, gathering metrics and debug interface on the F1 instance. diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md index 1cdf8839..03aedc33 100644 --- a/RELEASE_NOTES.md +++ b/RELEASE_NOTES.md @@ -26,6 +26,37 @@ * 1 DDR controller implemented in the SH (always available) * 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed) +## Release 1.4.6 (See [ERRATA](./ERRATA.md) for unsupported features) + + * Fixes SDx 2018.2 [missing profile report items in SDAccel](https://forums.aws.amazon.com/thread.jspa?threadID=293541&tstart=0) + * Requires [Xilinx 2018.2 Patch AR71715](hdk/docs/SDxPatch_AR71715_and_XRT_installation_instructions.md#installing-sdx-20182-tool-patch-ar71715) + * Requires [Xilinx runtime release 2018.2_XDF.RC4](https://github.com/Xilinx/XRT/tree/2018.2_XDF.RC4) + * Please see patching & XRT installation instructions [here](hdk/docs/SDxPatch_AR71715_and_XRT_installation_instructions.md) + * Fixes SDx 2018.2 [multithreaded kernel driver scheduling](https://forums.aws.amazon.com/thread.jspa?threadID=293166&tstart=0) + * Requires [Xilinx runtime release 2018.2_XDF.RC4](https://github.com/Xilinx/XRT/tree/2018.2_XDF.RC4) + * Please see XRT installation instructions [here](hdk/docs/SDxPatch_AR71715_and_XRT_installation_instructions.md#installing-xilinx-runtime-xrt-20182_xdfrc4) + * EDMA Driver is no longer supported. + * AWS strongly recommends moving your applications to [XDMA](sdk/linux_kernel_drivers/xdma/README.md). + * [EDMA Driver](sdk/linux_kernel_drivers/edma/README.md) will be fully removed from Developer kit 1.4.7+. + * Fixed Issues + * [NULL definition include in header file](https://github.com/aws/aws-fpga/pull/414) + * [Improved messaging for AFI builder script](https://github.com/aws/aws-fpga/pull/407) + * [Fixes address decoding to DDR slaves in cl_dram_dma example](hdk/cl/examples/cl_dram_dma/design) + * Improvements + * [Improves SDK FPGA managment tools error messaging](sdk/userspace/fpga_mgmt_tools/README.md) + * [Enhanced DMA lib for general device number mapping](sdk/userspace/fpga_libs/fpga_dma/fpga_dma_utils.c) + * [Improved guidelines for AFI power managment](hdk/docs/afi_power.md) + * [Improved Streaming Data Engine IP Integration Documentation](sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md) + + * Package versions used to validate SDAccel runtime + + | Package | AMI 1.5.0 [SDx 2018.2] | AMI 1.4.0 [SDx 2017.4] | + |---------|------------------------|------------------------| + | kernel | 3.10.0-862.11.6.el7.x86_64 | 3.10.0-693.21.1.el7.x86_64 | + | kernel-devel | 3.10.0-862.11.6.el7.x86_64 | 3.10.0-693.21.1.el7.x86_64 | + | LIBSTDC++ | libstdc++-4.8.5-36.el7.x86_64 | libstdc++-4.8.5-16.el7_4.2.x86_64 | + + ## Release 1.4.5 (See [ERRATA](./ERRATA.md) for unsupported features) * [Documents SDAccel Runtime compatibility](SDAccel/docs/Create_Runtime_AMI.md#runtime-ami-compatability-table) @@ -93,7 +124,7 @@ Look for the ./hdk/hdk_version.txt file. **Q: How do I know what my Shell version is? ** -The Shell version of an FPGA slot is available through the FPGA Image Management tools. See the description of `fpga-describe-local-image` for more details on retrieving the shell version from a slot. +The Shell version of an FPGA slot is available through the FPGA Image Management tools after an AFI has been loaded. See the description of `fpga-describe-local-image` for more details on retrieving the shell version from a slot. Prior to loading an AFI, the state of the FPGA (including shell version) is undefined and non-deterministic. **Q: How do I know what version of FPGA Image management tools are running on my instance? ** diff --git a/SDAccel/README.md b/SDAccel/README.md index 1708b1a1..0248a4dc 100644 --- a/SDAccel/README.md +++ b/SDAccel/README.md @@ -125,6 +125,8 @@ The instructions below describe how to build the Xilinx FPGA Binary and host app $ make TARGETS=hw DEVICES=$AWS_PLATFORM all ``` +NOTE: If you encounter an error with `No current synthesis run set`, you may have previously run the [HDK IPI examples](../hdk/docs/IPI_GUI_Vivado_Setup.md) and created a `Vivado_init.tcl` file in `~/.Xilinx/Vivado`. This will cause [problems](https://forums.aws.amazon.com/thread.jspa?threadID=268202&tstart=25) with the build process, thus it is recommended to remove it before starting a hardware system build. + Now that you have built your Xilinx FPGA binary, see [SDAccel Power Analysis Guide](./docs/SDAccel_Power_Analysis.md) for more details on how to analyze power for your binary. @@ -209,20 +211,11 @@ Here are the steps: * Ensure the host application can find and load the \*.awsxclbin AWS FPGA binary file. * Source the Runtime Environment & Execute your Host Application - * Xilinx SDx 2017.4: - ``` - $ sudo sh - # source /opt/Xilinx/SDx/2017.4.rte.dyn/setup.sh # Other runtime env settings needed by the host app should be setup after this step - # ./helloworld - ``` - - * Xilinx SDx 2018.2: ``` $ sudo sh - # source /opt/xilinx/xrt/setup.sh # Other runtime env settings needed by the host app should be setup after this step + # source $AWS_FPGA_REPO_DIR/sdaccel_runtime_setup.sh # Other runtime env settings needed by the host app should be setup after this step # ./helloworld ``` - # Additional SDAccel Information (2017.4) diff --git a/SDAccel/docs/Create_Runtime_AMI.md b/SDAccel/docs/Create_Runtime_AMI.md index 630a617a..75de0a48 100644 --- a/SDAccel/docs/Create_Runtime_AMI.md +++ b/SDAccel/docs/Create_Runtime_AMI.md @@ -51,25 +51,43 @@ ## 2. Copy required Xilinx SDAccel Runtime Libraries to the Instance and Reboot your Runtime Instance. -* Using an instance running [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) or an on-premises machine with access to a Xilinx SDAccel Tools Installation, run the following: +* Using an instance running [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) or an on-premises machine with access to a Xilinx SDAccel Tools Installation, first source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh and then run following commands: + +* if using Ubuntu or debian distribution set GLIBPATH env variable to Ubuntu. If using any other OS distribution set GLIBPATH to default. + +* set env variable 'XLNXRTE' to intended runtime install directory path. + +### **For Vivado SDX 2017.4** ```` - $ mkdir -p xlnxrte/lib/lnx64.o - $ mkdir -p xlnxrte/runtime/bin - $ cp $XIILNX_SDX/lib/lnx64.o/libstdc++.so* xlnxrte/lib/lnx64.o/. - $ cp $XIILNX_SDX/lib/lnx64.o/libxilinxopencl.so xlnxrte/lib/lnx64.o/. - $ cp $XIILNX_SDX/runtime/bin/xclbinsplit xlnxrte/runtime/bin - $ cp $XIILNX_SDX/runtime/bin/xclbincat xlnxrte/runtime/bin + $ export GLIBPATH= + $ export XLNXRTE= + $ mkdir -p $XLNXRTE/runtime/platforms/$(DSA)/driver + $ mkdir -p $XLNXRTE/lib/lnx64.o + $ mkdir -p $XLNXRTE/runtime/bin + $ mkdir -p $XLNXRTE/runtime/lib/x86_64 + $ cp $SDACCEL_DIR/userspace/src2/libxrt-aws.so $XLNXRTE/runtime/platforms/xilinx_aws-vu9p-f1-04261818_dynamic_5_0/driver/ + $ cp $SDACCEL_DIR/tools/awssak2/xbsak $XLNXRTE/runtime/bin/ + $ cp $XIILNX_SDX/lib/lnx64.o/$GLIBPATH/libstdc++.so* xlnxrte/lib/x86_64/ + $ cp $XIILNX_SDX/runtime/bin/xclbinsplit xlnxrte/runtime/bin/ + $ cp $XIILNX_SDX/runtime/bin/xclbincat xlnxrte/runtime/bin/ + $ cp $SDACCEL_DIR/aws_platform/xilinx_aws-vu9p-f1-04261818_dynamic_5_0/sw/lib/x86_64/libxilinxopencl.so $XLNXRTE/runtime/lib/x86_64/ + $ cp /opt/Xilinx/SDx/2017.4.rte.dyn/setup.sh $XLNXRTE/ + $ cp /opt/Xilinx/SDx/2017.4.rte.dyn/setup.csh $XLNXRTE/ ```` +* You may need to update path in $XLNXRTE/setup.sh and $XLNXRTE/setup.csh script to match your runtime instance. +* Copy $XLNXRTE directory created to $HOME on your Runtime Instance. -* Copy xlnxrte directory created to $HOME on your Runtime Instance. - +### **For Vivado SDX 2018.2** + please refer to [Installing the Xilinx Runtime](https://www.xilinx.com/html_docs/xilinx2018_2_xdf/sdaccel_doc/ejy1538090924727.html) for instructions on how to install runtime on your AMI. + + ## 3. Install Runtime Drivers and run your FPGA accelerated application on your Runtime Instance. * Log back on to the Runtime Instance: ``` - $ export XILINX_SDX=$HOME/xlnxrte + $ export XILINX_SDX=$HOME/$XLNXRTE ```` * You should be able to [run your FPGA accelerated application as described here](https://github.com/aws/aws-fpga/tree/master/SDAccel#runonf1), without needing to launch a new F1 instance diff --git a/SDAccel/docs/Debug_RTL_Kernel.md b/SDAccel/docs/Debug_RTL_Kernel.md index e5e2f5dd..3c968219 100644 --- a/SDAccel/docs/Debug_RTL_Kernel.md +++ b/SDAccel/docs/Debug_RTL_Kernel.md @@ -149,7 +149,7 @@ Please note, the angle bracket directories need to be replaced according to the ``` $ sudo sh - # source /opt/Xilinx/SDx/2017.4.rte.dyn/setup.sh + # source $AWS_FPGA_REPO_DIR/sdaccel_runtime_setup.sh # ./host ``` This produces the following output: diff --git a/SDAccel/examples/aws/helloworld_ocl_runtime/README.md b/SDAccel/examples/aws/helloworld_ocl_runtime/README.md index 638886c1..e812c270 100644 --- a/SDAccel/examples/aws/helloworld_ocl_runtime/README.md +++ b/SDAccel/examples/aws/helloworld_ocl_runtime/README.md @@ -36,7 +36,7 @@ Command sequence ``` sudo fpga-clear-local-image -S 0 >>$sudo sh -sh-4.2# source /opt/Xilinx/SDx/2017.4.rte.dyn/setup.sh +sh-4.2# source $AWS_FPGA_REPO_DIR/sdaccel_runtime_setup.sh sh-4.2# ./helloworld ``` diff --git a/SDAccel/sdaccel_xrt_version.txt b/SDAccel/sdaccel_xrt_version.txt new file mode 100644 index 00000000..2d2fb595 --- /dev/null +++ b/SDAccel/sdaccel_xrt_version.txt @@ -0,0 +1 @@ +343186f76f59edd01bc48d84cf67fe22a0a3f338 diff --git a/SDAccel/tests/test_run_sdaccel_example.py b/SDAccel/tests/test_run_sdaccel_example.py index 107d60d2..1a0cc32b 100644 --- a/SDAccel/tests/test_run_sdaccel_example.py +++ b/SDAccel/tests/test_run_sdaccel_example.py @@ -72,21 +72,19 @@ def teardown_method(self, test_method): aws_fpga_test_utils.remove_all_drivers() def test_run_sdaccel_example(self, examplePath, rteName, xilinxVersion): - + aws_fpga_test_utils.install_xocl_driver() os.chdir(self.get_sdaccel_example_fullpath(examplePath)) (rc, stdout_lines, stderr_lines) = self.run_cmd("make exe") assert rc == 0 em_run_cmd = self.get_sdaccel_example_run_cmd(examplePath) + check_runtime_script = os.path.join(AwsFpgaTestBase.WORKSPACE,'sdaccel_runtime_setup.sh') self.get_sdaccel_aws_xclbin_file(examplePath, rteName, xilinxVersion) - - run_cmd = "sudo -E /bin/bash -l -c \"source /opt/Xilinx/SDx/{}.rte.{}/setup.sh && {} \"".format(xilinxVersion, rteName, em_run_cmd) + + run_cmd = "sudo -E /bin/bash -l -c \"source {} && {} \"".format(check_runtime_script, em_run_cmd) - if xilinxVersion == "2018.2": - run_cmd = "sudo -E /bin/bash -l -c \"source /opt/xilinx/xrt/setup.sh && {} \"".format(em_run_cmd) - logger.info("Running cmd={}".format(run_cmd)) (rc, stdout_lines, stderr_lines) = self.run_cmd(run_cmd) assert rc == 0 diff --git a/SDAccel/tools/create_sdaccel_afi.sh b/SDAccel/tools/create_sdaccel_afi.sh index dd842fe5..1e258708 100755 --- a/SDAccel/tools/create_sdaccel_afi.sh +++ b/SDAccel/tools/create_sdaccel_afi.sh @@ -22,6 +22,7 @@ full_script=$(readlink -f $script) script_name=$(basename $full_script) source $AWS_FPGA_REPO_DIR/shared/bin/set_common_functions.sh +source $AWS_FPGA_REPO_DIR/shared/bin/set_common_env_vars.sh debug=0 @@ -90,9 +91,15 @@ while [ "$1" != "" ]; do shift done +if [ "$HDK_DIR" == "" ] +then + err_msg "Env HDK_DIR not set" + exit 1 +fi + if [ "$RELEASE_VER" == "" ] then - err_msg "Env variable RELEASE_VER not set, did you `source sdaccel_setup.sh`?" + err_msg "Env variable RELEASE_VER not set, did you source sdaccel_setup.sh?" exit 1 fi diff --git a/conftest.py b/conftest.py index c28c8339..0a9bf21d 100644 --- a/conftest.py +++ b/conftest.py @@ -22,6 +22,8 @@ import pytest def pytest_addoption(parser): + parser.addoption("--Simulator", action="store", required=False, type=str, + help="Simulator tool requested for this test", default="vivado") parser.addoption("--examplePath", action="store", required=False, type=str, help="Path to the Xilinx Example to test", default="SDAccel/examples/xilinx/getting_started/host/helloworld_ocl") parser.addoption("--rteName", action="store", required=False, type=str, @@ -30,6 +32,11 @@ def pytest_addoption(parser): help="Xilinx Version. For eg: 2017.1, 2017.4, etc", default="2017.4") def pytest_generate_tests(metafunc): + + if metafunc.cls.ADD_SIMULATOR: + print("Configuring parameters of {}::{}".format(metafunc.module.__name__, metafunc.function.__name__)) + print("Simulator = " + metafunc.config.getoption('Simulator')) + metafunc.parametrize("Simulator", [metafunc.config.getoption('Simulator')]) if metafunc.cls.ADD_EXAMPLEPATH: print("Configuring parameters of {}::{}".format(metafunc.module.__name__, metafunc.function.__name__)) diff --git a/hdk/cl/examples/cl_dram_dma/README.md b/hdk/cl/examples/cl_dram_dma/README.md index 26572bea..cce7de92 100644 --- a/hdk/cl/examples/cl_dram_dma/README.md +++ b/hdk/cl/examples/cl_dram_dma/README.md @@ -188,6 +188,6 @@ Alternatively, you can directly use a pre-generated AFI for this CL. | PCI Vendor ID | 0x1D0F (Amazon) | | PCI Subsystem ID | 0x1D51 | | PCI Subsystem Vendor ID | 0xFEDC | -| Pre-generated AFI ID | afi-0a3a14f0372228f55 | -| Pre-generated AGFI ID | agfi-01dc2520aaf357e86 | +| Pre-generated AFI ID | afi-0583e8d7a84ac7ce2 | +| Pre-generated AGFI ID | agfi-0d132ece5c8010bf7 | diff --git a/hdk/cl/examples/cl_dram_dma/build/scripts/encrypt.tcl b/hdk/cl/examples/cl_dram_dma/build/scripts/encrypt.tcl index 683e3b3d..1008376d 100644 --- a/hdk/cl/examples/cl_dram_dma/build/scripts/encrypt.tcl +++ b/hdk/cl/examples/cl_dram_dma/build/scripts/encrypt.tcl @@ -45,12 +45,11 @@ file copy -force $CL_DIR/design/mem_scrb.sv $TARGET_DIR file copy -force $CL_DIR/design/cl_tst_scrb.sv $TARGET_DIR file copy -force $CL_DIR/design/axil_slave.sv $TARGET_DIR file copy -force $CL_DIR/design/cl_int_slv.sv $TARGET_DIR -file copy -force $CL_DIR/design/cl_mstr_axi_tst.sv $TARGET_DIR file copy -force $CL_DIR/design/cl_pcim_mstr.sv $TARGET_DIR file copy -force $CL_DIR/design/cl_vio.sv $TARGET_DIR file copy -force $CL_DIR/design/cl_dma_pcis_slv.sv $TARGET_DIR file copy -force $CL_DIR/design/cl_ila.sv $TARGET_DIR -file copy -force $CL_DIR/design/cl_ocl_slv.sv $TARGET_DIR +file copy -force $CL_DIR/design/cl_ocl_slv.sv $TARGET_DIR file copy -force $CL_DIR/design/cl_sda_slv.sv $TARGET_DIR file copy -force $CL_DIR/design/cl_dram_dma_axi_mstr.sv $TARGET_DIR file copy -force $UNUSED_TEMPLATES_DIR/unused_sh_bar1_template.inc $TARGET_DIR diff --git a/hdk/cl/examples/cl_dram_dma/design/cl_dma_pcis_slv.sv b/hdk/cl/examples/cl_dram_dma/design/cl_dma_pcis_slv.sv index ca20f376..1c1de075 100644 --- a/hdk/cl/examples/cl_dram_dma/design/cl_dma_pcis_slv.sv +++ b/hdk/cl/examples/cl_dram_dma/design/cl_dma_pcis_slv.sv @@ -40,14 +40,14 @@ module cl_dma_pcis_slv #(parameter SCRB_MAX_ADDR = 64'h3FFFFFFFF, parameter SCRB axi_bus_t.slave cl_sh_ddr_bus - + ); localparam NUM_CFG_STGS_CL_DDR_ATG = 4; localparam NUM_CFG_STGS_SH_DDR_ATG = 4; -//---------------------------- +//---------------------------- // Internal signals -//---------------------------- +//---------------------------- axi_bus_t lcl_cl_sh_ddra_q(); axi_bus_t lcl_cl_sh_ddrb_q(); axi_bus_t lcl_cl_sh_ddrd_q(); @@ -61,7 +61,7 @@ axi_bus_t cl_sh_ddr_q(); axi_bus_t cl_sh_ddr_q2(); axi_bus_t cl_sh_ddr_q3(); axi_bus_t sh_cl_pcis(); - + cfg_bus_t ddra_tst_cfg_bus_q(); cfg_bus_t ddrb_tst_cfg_bus_q(); cfg_bus_t ddrc_tst_cfg_bus_q(); @@ -72,9 +72,9 @@ scrb_bus_t ddrb_scrb_bus_q(); scrb_bus_t ddrc_scrb_bus_q(); scrb_bus_t ddrd_scrb_bus_q(); -//---------------------------- +//---------------------------- // End Internal signals -//---------------------------- +//---------------------------- //reset synchronizers @@ -85,9 +85,9 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR0_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in lib_pipe #(.WIDTH(1), .STAGES(4)) SLR1_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in_bus(aresetn), .out_bus(slr1_sync_aresetn)); lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in_bus(aresetn), .out_bus(slr2_sync_aresetn)); -//---------------------------- -// flop the dma_pcis interface input of CL -//---------------------------- +//---------------------------- +// flop the dma_pcis interface input of CL +//---------------------------- // AXI4 Register Slice for dma_pcis interface axi_register_slice PCI_AXL_REG_SLC ( @@ -95,7 +95,7 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .aresetn (slr0_sync_aresetn), .s_axi_awid (sh_cl_dma_pcis_bus.awid), .s_axi_awaddr (sh_cl_dma_pcis_bus.awaddr), - .s_axi_awlen (sh_cl_dma_pcis_bus.awlen), + .s_axi_awlen (sh_cl_dma_pcis_bus.awlen), .s_axi_awvalid (sh_cl_dma_pcis_bus.awvalid), .s_axi_awsize (sh_cl_dma_pcis_bus.awsize), .s_axi_awready (sh_cl_dma_pcis_bus.awready), @@ -110,7 +110,7 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .s_axi_bready (sh_cl_dma_pcis_bus.bready), .s_axi_arid (sh_cl_dma_pcis_bus.arid), .s_axi_araddr (sh_cl_dma_pcis_bus.araddr), - .s_axi_arlen (sh_cl_dma_pcis_bus.arlen), + .s_axi_arlen (sh_cl_dma_pcis_bus.arlen), .s_axi_arvalid (sh_cl_dma_pcis_bus.arvalid), .s_axi_arsize (sh_cl_dma_pcis_bus.arsize), .s_axi_arready (sh_cl_dma_pcis_bus.arready), @@ -120,33 +120,33 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .s_axi_rlast (sh_cl_dma_pcis_bus.rlast), .s_axi_rvalid (sh_cl_dma_pcis_bus.rvalid), .s_axi_rready (sh_cl_dma_pcis_bus.rready), - + .m_axi_awid (sh_cl_dma_pcis_q.awid), - .m_axi_awaddr (sh_cl_dma_pcis_q.awaddr), + .m_axi_awaddr (sh_cl_dma_pcis_q.awaddr), .m_axi_awlen (sh_cl_dma_pcis_q.awlen), .m_axi_awvalid (sh_cl_dma_pcis_q.awvalid), .m_axi_awsize (sh_cl_dma_pcis_q.awsize), .m_axi_awready (sh_cl_dma_pcis_q.awready), - .m_axi_wdata (sh_cl_dma_pcis_q.wdata), + .m_axi_wdata (sh_cl_dma_pcis_q.wdata), .m_axi_wstrb (sh_cl_dma_pcis_q.wstrb), - .m_axi_wvalid (sh_cl_dma_pcis_q.wvalid), + .m_axi_wvalid (sh_cl_dma_pcis_q.wvalid), .m_axi_wlast (sh_cl_dma_pcis_q.wlast), - .m_axi_wready (sh_cl_dma_pcis_q.wready), - .m_axi_bresp (sh_cl_dma_pcis_q.bresp), - .m_axi_bvalid (sh_cl_dma_pcis_q.bvalid), + .m_axi_wready (sh_cl_dma_pcis_q.wready), + .m_axi_bresp (sh_cl_dma_pcis_q.bresp), + .m_axi_bvalid (sh_cl_dma_pcis_q.bvalid), .m_axi_bid (sh_cl_dma_pcis_q.bid), - .m_axi_bready (sh_cl_dma_pcis_q.bready), - .m_axi_arid (sh_cl_dma_pcis_q.arid), - .m_axi_araddr (sh_cl_dma_pcis_q.araddr), - .m_axi_arlen (sh_cl_dma_pcis_q.arlen), - .m_axi_arsize (sh_cl_dma_pcis_q.arsize), + .m_axi_bready (sh_cl_dma_pcis_q.bready), + .m_axi_arid (sh_cl_dma_pcis_q.arid), + .m_axi_araddr (sh_cl_dma_pcis_q.araddr), + .m_axi_arlen (sh_cl_dma_pcis_q.arlen), + .m_axi_arsize (sh_cl_dma_pcis_q.arsize), .m_axi_arvalid (sh_cl_dma_pcis_q.arvalid), .m_axi_arready (sh_cl_dma_pcis_q.arready), - .m_axi_rid (sh_cl_dma_pcis_q.rid), - .m_axi_rdata (sh_cl_dma_pcis_q.rdata), - .m_axi_rresp (sh_cl_dma_pcis_q.rresp), - .m_axi_rlast (sh_cl_dma_pcis_q.rlast), - .m_axi_rvalid (sh_cl_dma_pcis_q.rvalid), + .m_axi_rid (sh_cl_dma_pcis_q.rid), + .m_axi_rdata (sh_cl_dma_pcis_q.rdata), + .m_axi_rresp (sh_cl_dma_pcis_q.rresp), + .m_axi_rlast (sh_cl_dma_pcis_q.rlast), + .m_axi_rvalid (sh_cl_dma_pcis_q.rvalid), .m_axi_rready (sh_cl_dma_pcis_q.rready) ); @@ -155,11 +155,11 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in //----------------------------------------------------- assign sh_cl_dma_pcis_q.rid[15:6] = 10'b0 ; assign sh_cl_dma_pcis_q.bid[15:6] = 10'b0 ; - -//---------------------------- -// axi interconnect for DDR address decodes -//---------------------------- -(* dont_touch = "true" *) cl_axi_interconnect AXI_CROSSBAR + +//---------------------------- +// axi interconnect for DDR address decodes +//---------------------------- +(* dont_touch = "true" *) cl_axi_interconnect AXI_CROSSBAR (.ACLK(aclk), .ARESETN(slr1_sync_aresetn), @@ -324,8 +324,8 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .M03_AXI_wstrb(lcl_cl_sh_ddrd_q.wstrb), .M03_AXI_wvalid(lcl_cl_sh_ddrd_q.wvalid), - - + + .S00_AXI_araddr({sh_cl_dma_pcis_q.araddr[63:37], 1'b0, sh_cl_dma_pcis_q.araddr[35:0]}), .S00_AXI_arburst(2'b1), .S00_AXI_arcache(4'b11), @@ -366,10 +366,10 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .S00_AXI_wstrb(sh_cl_dma_pcis_q.wstrb), .S00_AXI_wvalid(sh_cl_dma_pcis_q.wvalid), - .S01_AXI_araddr(cl_axi_mstr_bus.araddr), + .S01_AXI_araddr({cl_axi_mstr_bus.araddr[63:37], 1'b0, cl_axi_mstr_bus.araddr[35:0]}), .S01_AXI_arburst(2'b1), .S01_AXI_arcache(4'b11), - .S01_AXI_arid(cl_axi_mstr_bus.arid), + .S01_AXI_arid(cl_axi_mstr_bus.arid[5:0]), .S01_AXI_arlen(cl_axi_mstr_bus.arlen), .S01_AXI_arlock(1'b0), .S01_AXI_arprot(3'b10), @@ -378,10 +378,10 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .S01_AXI_arregion(4'b0), .S01_AXI_arsize(cl_axi_mstr_bus.arsize), .S01_AXI_arvalid(cl_axi_mstr_bus.arvalid), - .S01_AXI_awaddr(cl_axi_mstr_bus.awaddr), + .S01_AXI_awaddr({cl_axi_mstr_bus.awaddr[63:37], 1'b0, cl_axi_mstr_bus.awaddr[35:0]}), .S01_AXI_awburst(2'b1), .S01_AXI_awcache(4'b11), - .S01_AXI_awid(cl_axi_mstr_bus.awid), + .S01_AXI_awid(cl_axi_mstr_bus.awid[5:0]), .S01_AXI_awlen(cl_axi_mstr_bus.awlen), .S01_AXI_awlock(1'b0), .S01_AXI_awprot(3'b10), @@ -390,12 +390,12 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .S01_AXI_awregion(4'b0), .S01_AXI_awsize(cl_axi_mstr_bus.awsize), .S01_AXI_awvalid(cl_axi_mstr_bus.awvalid), - .S01_AXI_bid(cl_axi_mstr_bus.bid), + .S01_AXI_bid(cl_axi_mstr_bus.bid[5:0]), .S01_AXI_bready(cl_axi_mstr_bus.bready), .S01_AXI_bresp(cl_axi_mstr_bus.bresp), .S01_AXI_bvalid(cl_axi_mstr_bus.bvalid), .S01_AXI_rdata(cl_axi_mstr_bus.rdata), - .S01_AXI_rid(cl_axi_mstr_bus.rid), + .S01_AXI_rid(cl_axi_mstr_bus.rid[5:0]), .S01_AXI_rlast(cl_axi_mstr_bus.rlast), .S01_AXI_rready(cl_axi_mstr_bus.rready), .S01_AXI_rresp(cl_axi_mstr_bus.rresp), @@ -406,13 +406,13 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .S01_AXI_wstrb(cl_axi_mstr_bus.wstrb), .S01_AXI_wvalid(cl_axi_mstr_bus.wvalid)); -//---------------------------- -// flop the output of interconnect for DDRC -//---------------------------- +//---------------------------- +// flop the output of interconnect for DDRC +//---------------------------- axi_register_slice DDR_C_TST_AXI4_REG_SLC ( .aclk (aclk), .aresetn (slr1_sync_aresetn), - + .s_axi_awid (cl_sh_ddr_q.awid), .s_axi_awaddr ({cl_sh_ddr_q.awaddr[63:36], 2'b0, cl_sh_ddr_q.awaddr[33:0]}), .s_axi_awlen (cl_sh_ddr_q.awlen), @@ -439,55 +439,55 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .s_axi_rresp (cl_sh_ddr_q.rresp), .s_axi_rlast (cl_sh_ddr_q.rlast), .s_axi_rvalid (cl_sh_ddr_q.rvalid), - .s_axi_rready (cl_sh_ddr_q.rready), - .m_axi_awid (cl_sh_ddr_q2.awid), - .m_axi_awaddr (cl_sh_ddr_q2.awaddr), - .m_axi_awlen (cl_sh_ddr_q2.awlen), + .s_axi_rready (cl_sh_ddr_q.rready), + .m_axi_awid (cl_sh_ddr_q2.awid), + .m_axi_awaddr (cl_sh_ddr_q2.awaddr), + .m_axi_awlen (cl_sh_ddr_q2.awlen), .m_axi_awsize (cl_sh_ddr_q2.awsize), .m_axi_awvalid (cl_sh_ddr_q2.awvalid), .m_axi_awready (cl_sh_ddr_q2.awready), - .m_axi_wdata (cl_sh_ddr_q2.wdata), - .m_axi_wstrb (cl_sh_ddr_q2.wstrb), - .m_axi_wlast (cl_sh_ddr_q2.wlast), - .m_axi_wvalid (cl_sh_ddr_q2.wvalid), - .m_axi_wready (cl_sh_ddr_q2.wready), - .m_axi_bid (cl_sh_ddr_q2.bid), - .m_axi_bresp (cl_sh_ddr_q2.bresp), - .m_axi_bvalid (cl_sh_ddr_q2.bvalid), - .m_axi_bready (cl_sh_ddr_q2.bready), - .m_axi_arid (cl_sh_ddr_q2.arid), - .m_axi_araddr (cl_sh_ddr_q2.araddr), - .m_axi_arlen (cl_sh_ddr_q2.arlen), + .m_axi_wdata (cl_sh_ddr_q2.wdata), + .m_axi_wstrb (cl_sh_ddr_q2.wstrb), + .m_axi_wlast (cl_sh_ddr_q2.wlast), + .m_axi_wvalid (cl_sh_ddr_q2.wvalid), + .m_axi_wready (cl_sh_ddr_q2.wready), + .m_axi_bid (cl_sh_ddr_q2.bid), + .m_axi_bresp (cl_sh_ddr_q2.bresp), + .m_axi_bvalid (cl_sh_ddr_q2.bvalid), + .m_axi_bready (cl_sh_ddr_q2.bready), + .m_axi_arid (cl_sh_ddr_q2.arid), + .m_axi_araddr (cl_sh_ddr_q2.araddr), + .m_axi_arlen (cl_sh_ddr_q2.arlen), .m_axi_arsize (cl_sh_ddr_q2.arsize), .m_axi_arvalid (cl_sh_ddr_q2.arvalid), .m_axi_arready (cl_sh_ddr_q2.arready), - .m_axi_rid (cl_sh_ddr_q2.rid), - .m_axi_rdata (cl_sh_ddr_q2.rdata), - .m_axi_rresp (cl_sh_ddr_q2.rresp), - .m_axi_rlast (cl_sh_ddr_q2.rlast), - .m_axi_rvalid (cl_sh_ddr_q2.rvalid), + .m_axi_rid (cl_sh_ddr_q2.rid), + .m_axi_rdata (cl_sh_ddr_q2.rdata), + .m_axi_rresp (cl_sh_ddr_q2.rresp), + .m_axi_rlast (cl_sh_ddr_q2.rlast), + .m_axi_rvalid (cl_sh_ddr_q2.rvalid), .m_axi_rready (cl_sh_ddr_q2.rready) ); -//---------------------------- -// ATG/scrubber for DDRC -//---------------------------- +//---------------------------- +// ATG/scrubber for DDRC +//---------------------------- - lib_pipe #(.WIDTH(32+32+1+1), .STAGES(NUM_CFG_STGS_SH_DDR_ATG)) PIPE_CFG_REQ_DDR_C (.clk (aclk), - .rst_n (aresetn), + lib_pipe #(.WIDTH(32+32+1+1), .STAGES(NUM_CFG_STGS_SH_DDR_ATG)) PIPE_CFG_REQ_DDR_C (.clk (aclk), + .rst_n (aresetn), .in_bus({ddrc_tst_cfg_bus.addr, ddrc_tst_cfg_bus.wdata, ddrc_tst_cfg_bus.wr, ddrc_tst_cfg_bus.rd}), .out_bus({ddrc_tst_cfg_bus_q.addr, ddrc_tst_cfg_bus_q.wdata, ddrc_tst_cfg_bus_q.wr, ddrc_tst_cfg_bus_q.rd}) ); - - lib_pipe #(.WIDTH(32+1), .STAGES(NUM_CFG_STGS_SH_DDR_ATG)) PIPE_CFG_ACK_DDR_C (.clk (aclk), - .rst_n (aresetn), + + lib_pipe #(.WIDTH(32+1), .STAGES(NUM_CFG_STGS_SH_DDR_ATG)) PIPE_CFG_ACK_DDR_C (.clk (aclk), + .rst_n (aresetn), .in_bus({ddrc_tst_cfg_bus_q.ack, ddrc_tst_cfg_bus_q.rdata}), .out_bus({ddrc_tst_cfg_bus.ack, ddrc_tst_cfg_bus.rdata}) ); - lib_pipe #(.WIDTH(2+3+64), .STAGES(NUM_CFG_STGS_SH_DDR_ATG)) PIPE_SCRB_DDR_C (.clk(aclk), + lib_pipe #(.WIDTH(2+3+64), .STAGES(NUM_CFG_STGS_SH_DDR_ATG)) PIPE_SCRB_DDR_C (.clk(aclk), .rst_n(aresetn), .in_bus({ddrc_scrb_bus.enable, ddrc_scrb_bus_q.done, ddrc_scrb_bus_q.state, ddrc_scrb_bus_q.addr}), .out_bus({ddrc_scrb_bus_q.enable, ddrc_scrb_bus.done, ddrc_scrb_bus.state, ddrc_scrb_bus.addr}) @@ -496,7 +496,7 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .SCRB_BURST_LEN_MINUS1(SCRB_BURST_LEN_MINUS1), .SCRB_MAX_ADDR(SCRB_MAX_ADDR), .NO_SCRB_INST(NO_SCRB_INST)) CL_TST_DDR_C ( - + .clk(aclk), .rst_n(slr1_sync_aresetn), @@ -505,10 +505,10 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .cfg_wr(ddrc_tst_cfg_bus_q.wr), .cfg_rd(ddrc_tst_cfg_bus_q.rd), .tst_cfg_ack(ddrc_tst_cfg_bus_q.ack), - .tst_cfg_rdata(ddrc_tst_cfg_bus_q.rdata), + .tst_cfg_rdata(ddrc_tst_cfg_bus_q.rdata), .slv_awid(cl_sh_ddr_q2.awid[6:0]), - .slv_awaddr(cl_sh_ddr_q2.awaddr), + .slv_awaddr(cl_sh_ddr_q2.awaddr), .slv_awlen(cl_sh_ddr_q2.awlen), .slv_awvalid(cl_sh_ddr_q2.awvalid), .slv_awsize(cl_sh_ddr_q2.awsize), @@ -529,12 +529,12 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .slv_bready(cl_sh_ddr_q2.bready), .slv_arid(cl_sh_ddr_q2.arid[6:0]), - .slv_araddr(cl_sh_ddr_q2.araddr), + .slv_araddr(cl_sh_ddr_q2.araddr), .slv_arlen(cl_sh_ddr_q2.arlen), .slv_arvalid(cl_sh_ddr_q2.arvalid), .slv_arsize(cl_sh_ddr_q2.arsize), .slv_aruser(11'b0), - .slv_arready(cl_sh_ddr_q2.arready), + .slv_arready(cl_sh_ddr_q2.arready), .slv_rid(cl_sh_ddr_q2.rid[6:0]), .slv_rdata(cl_sh_ddr_q2.rdata), @@ -544,9 +544,9 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .slv_rvalid(cl_sh_ddr_q2.rvalid), .slv_rready(cl_sh_ddr_q2.rready), - + .awid(cl_sh_ddr_q3.awid[8:0]), - .awaddr(cl_sh_ddr_q3.awaddr), + .awaddr(cl_sh_ddr_q3.awaddr), .awlen(cl_sh_ddr_q3.awlen), .awvalid(cl_sh_ddr_q3.awvalid), .awsize(cl_sh_ddr_q3.awsize), @@ -590,14 +590,14 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .scrb_dbg_addr (ddrc_scrb_bus_q.addr) ); -//---------------------------- -// flop the output of ATG/Scrubber for DDRC -//---------------------------- +//---------------------------- +// flop the output of ATG/Scrubber for DDRC +//---------------------------- axi_register_slice DDR_C_TST_AXI4_REG_SLC_1 ( .aclk (aclk), .aresetn (slr1_sync_aresetn), - + .s_axi_awid (cl_sh_ddr_q3.awid), .s_axi_awaddr (cl_sh_ddr_q3.awaddr), .s_axi_awlen (cl_sh_ddr_q3.awlen), @@ -625,41 +625,41 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .s_axi_rlast (cl_sh_ddr_q3.rlast), .s_axi_rvalid (cl_sh_ddr_q3.rvalid), .s_axi_rready (cl_sh_ddr_q3.rready), - - .m_axi_awid (cl_sh_ddr_bus.awid), - .m_axi_awaddr (cl_sh_ddr_bus.awaddr), - .m_axi_awlen (cl_sh_ddr_bus.awlen), + + .m_axi_awid (cl_sh_ddr_bus.awid), + .m_axi_awaddr (cl_sh_ddr_bus.awaddr), + .m_axi_awlen (cl_sh_ddr_bus.awlen), .m_axi_awsize (cl_sh_ddr_bus.awsize), .m_axi_awvalid (cl_sh_ddr_bus.awvalid), .m_axi_awready (cl_sh_ddr_bus.awready), - .m_axi_wdata (cl_sh_ddr_bus.wdata), - .m_axi_wstrb (cl_sh_ddr_bus.wstrb), - .m_axi_wlast (cl_sh_ddr_bus.wlast), - .m_axi_wvalid (cl_sh_ddr_bus.wvalid), - .m_axi_wready (cl_sh_ddr_bus.wready), - .m_axi_bid (cl_sh_ddr_bus.bid), - .m_axi_bresp (cl_sh_ddr_bus.bresp), - .m_axi_bvalid (cl_sh_ddr_bus.bvalid), - .m_axi_bready (cl_sh_ddr_bus.bready), - .m_axi_arid (cl_sh_ddr_bus.arid), - .m_axi_araddr (cl_sh_ddr_bus.araddr), - .m_axi_arlen (cl_sh_ddr_bus.arlen), + .m_axi_wdata (cl_sh_ddr_bus.wdata), + .m_axi_wstrb (cl_sh_ddr_bus.wstrb), + .m_axi_wlast (cl_sh_ddr_bus.wlast), + .m_axi_wvalid (cl_sh_ddr_bus.wvalid), + .m_axi_wready (cl_sh_ddr_bus.wready), + .m_axi_bid (cl_sh_ddr_bus.bid), + .m_axi_bresp (cl_sh_ddr_bus.bresp), + .m_axi_bvalid (cl_sh_ddr_bus.bvalid), + .m_axi_bready (cl_sh_ddr_bus.bready), + .m_axi_arid (cl_sh_ddr_bus.arid), + .m_axi_araddr (cl_sh_ddr_bus.araddr), + .m_axi_arlen (cl_sh_ddr_bus.arlen), .m_axi_arsize (cl_sh_ddr_bus.arsize), .m_axi_arvalid (cl_sh_ddr_bus.arvalid), .m_axi_arready (cl_sh_ddr_bus.arready), - .m_axi_rid (cl_sh_ddr_bus.rid), - .m_axi_rdata (cl_sh_ddr_bus.rdata), - .m_axi_rresp (cl_sh_ddr_bus.rresp), - .m_axi_rlast (cl_sh_ddr_bus.rlast), - .m_axi_rvalid (cl_sh_ddr_bus.rvalid), + .m_axi_rid (cl_sh_ddr_bus.rid), + .m_axi_rdata (cl_sh_ddr_bus.rdata), + .m_axi_rresp (cl_sh_ddr_bus.rresp), + .m_axi_rlast (cl_sh_ddr_bus.rlast), + .m_axi_rvalid (cl_sh_ddr_bus.rvalid), .m_axi_rready (cl_sh_ddr_bus.rready) ); -//---------------------------- -// flop the output of interconnect for DDRA +//---------------------------- +// flop the output of interconnect for DDRA // back to back for SLR crossing -//---------------------------- +//---------------------------- //back to back register slices for SLR crossing src_register_slice DDR_A_TST_AXI4_REG_SLC_1 ( .aclk (aclk), @@ -702,9 +702,9 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .s_axi_rresp (lcl_cl_sh_ddra_q.rresp), .s_axi_rlast (lcl_cl_sh_ddra_q.rlast), .s_axi_rvalid (lcl_cl_sh_ddra_q.rvalid), - .s_axi_rready (lcl_cl_sh_ddra_q.rready), - .m_axi_awid (lcl_cl_sh_ddra_q2.awid), - .m_axi_awaddr (lcl_cl_sh_ddra_q2.awaddr), + .s_axi_rready (lcl_cl_sh_ddra_q.rready), + .m_axi_awid (lcl_cl_sh_ddra_q2.awid), + .m_axi_awaddr (lcl_cl_sh_ddra_q2.awaddr), .m_axi_awlen (lcl_cl_sh_ddra_q2.awlen), .m_axi_awsize (lcl_cl_sh_ddra_q2.awsize), .m_axi_awburst (), @@ -712,35 +712,35 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .m_axi_awcache (), .m_axi_awprot (), .m_axi_awregion (), - .m_axi_awqos (), + .m_axi_awqos (), .m_axi_awvalid (lcl_cl_sh_ddra_q2.awvalid), .m_axi_awready (lcl_cl_sh_ddra_q2.awready), - .m_axi_wdata (lcl_cl_sh_ddra_q2.wdata), - .m_axi_wstrb (lcl_cl_sh_ddra_q2.wstrb), - .m_axi_wlast (lcl_cl_sh_ddra_q2.wlast), - .m_axi_wvalid (lcl_cl_sh_ddra_q2.wvalid), - .m_axi_wready (lcl_cl_sh_ddra_q2.wready), - .m_axi_bid (lcl_cl_sh_ddra_q2.bid), - .m_axi_bresp (lcl_cl_sh_ddra_q2.bresp), - .m_axi_bvalid (lcl_cl_sh_ddra_q2.bvalid), - .m_axi_bready (lcl_cl_sh_ddra_q2.bready), - .m_axi_arid (lcl_cl_sh_ddra_q2.arid), - .m_axi_araddr (lcl_cl_sh_ddra_q2.araddr), - .m_axi_arlen (lcl_cl_sh_ddra_q2.arlen), + .m_axi_wdata (lcl_cl_sh_ddra_q2.wdata), + .m_axi_wstrb (lcl_cl_sh_ddra_q2.wstrb), + .m_axi_wlast (lcl_cl_sh_ddra_q2.wlast), + .m_axi_wvalid (lcl_cl_sh_ddra_q2.wvalid), + .m_axi_wready (lcl_cl_sh_ddra_q2.wready), + .m_axi_bid (lcl_cl_sh_ddra_q2.bid), + .m_axi_bresp (lcl_cl_sh_ddra_q2.bresp), + .m_axi_bvalid (lcl_cl_sh_ddra_q2.bvalid), + .m_axi_bready (lcl_cl_sh_ddra_q2.bready), + .m_axi_arid (lcl_cl_sh_ddra_q2.arid), + .m_axi_araddr (lcl_cl_sh_ddra_q2.araddr), + .m_axi_arlen (lcl_cl_sh_ddra_q2.arlen), .m_axi_arsize (lcl_cl_sh_ddra_q2.arsize), .m_axi_arburst (), .m_axi_arlock (), .m_axi_arcache (), .m_axi_arprot (), .m_axi_arregion (), - .m_axi_arqos (), + .m_axi_arqos (), .m_axi_arvalid (lcl_cl_sh_ddra_q2.arvalid), .m_axi_arready (lcl_cl_sh_ddra_q2.arready), - .m_axi_rid (lcl_cl_sh_ddra_q2.rid), - .m_axi_rdata (lcl_cl_sh_ddra_q2.rdata), - .m_axi_rresp (lcl_cl_sh_ddra_q2.rresp), - .m_axi_rlast (lcl_cl_sh_ddra_q2.rlast), - .m_axi_rvalid (lcl_cl_sh_ddra_q2.rvalid), + .m_axi_rid (lcl_cl_sh_ddra_q2.rid), + .m_axi_rdata (lcl_cl_sh_ddra_q2.rdata), + .m_axi_rresp (lcl_cl_sh_ddra_q2.rresp), + .m_axi_rlast (lcl_cl_sh_ddra_q2.rlast), + .m_axi_rvalid (lcl_cl_sh_ddra_q2.rvalid), .m_axi_rready (lcl_cl_sh_ddra_q2.rready) ); dest_register_slice DDR_A_TST_AXI4_REG_SLC_2 ( @@ -784,9 +784,9 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .s_axi_rresp (lcl_cl_sh_ddra_q2.rresp), .s_axi_rlast (lcl_cl_sh_ddra_q2.rlast), .s_axi_rvalid (lcl_cl_sh_ddra_q2.rvalid), - .s_axi_rready (lcl_cl_sh_ddra_q2.rready), - .m_axi_awid (lcl_cl_sh_ddra_q3.awid), - .m_axi_awaddr (lcl_cl_sh_ddra_q3.awaddr), + .s_axi_rready (lcl_cl_sh_ddra_q2.rready), + .m_axi_awid (lcl_cl_sh_ddra_q3.awid), + .m_axi_awaddr (lcl_cl_sh_ddra_q3.awaddr), .m_axi_awlen (lcl_cl_sh_ddra_q3.awlen), .m_axi_awsize (lcl_cl_sh_ddra_q3.awsize), .m_axi_awburst (), @@ -794,20 +794,20 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .m_axi_awcache (), .m_axi_awprot (), .m_axi_awregion (), - .m_axi_awqos (), + .m_axi_awqos (), .m_axi_awvalid (lcl_cl_sh_ddra_q3.awvalid), .m_axi_awready (lcl_cl_sh_ddra_q3.awready), - .m_axi_wdata (lcl_cl_sh_ddra_q3.wdata), - .m_axi_wstrb (lcl_cl_sh_ddra_q3.wstrb), - .m_axi_wlast (lcl_cl_sh_ddra_q3.wlast), - .m_axi_wvalid (lcl_cl_sh_ddra_q3.wvalid), - .m_axi_wready (lcl_cl_sh_ddra_q3.wready), - .m_axi_bid (lcl_cl_sh_ddra_q3.bid), - .m_axi_bresp (lcl_cl_sh_ddra_q3.bresp), - .m_axi_bvalid (lcl_cl_sh_ddra_q3.bvalid), - .m_axi_bready (lcl_cl_sh_ddra_q3.bready), - .m_axi_arid (lcl_cl_sh_ddra_q3.arid), - .m_axi_araddr (lcl_cl_sh_ddra_q3.araddr), + .m_axi_wdata (lcl_cl_sh_ddra_q3.wdata), + .m_axi_wstrb (lcl_cl_sh_ddra_q3.wstrb), + .m_axi_wlast (lcl_cl_sh_ddra_q3.wlast), + .m_axi_wvalid (lcl_cl_sh_ddra_q3.wvalid), + .m_axi_wready (lcl_cl_sh_ddra_q3.wready), + .m_axi_bid (lcl_cl_sh_ddra_q3.bid), + .m_axi_bresp (lcl_cl_sh_ddra_q3.bresp), + .m_axi_bvalid (lcl_cl_sh_ddra_q3.bvalid), + .m_axi_bready (lcl_cl_sh_ddra_q3.bready), + .m_axi_arid (lcl_cl_sh_ddra_q3.arid), + .m_axi_araddr (lcl_cl_sh_ddra_q3.araddr), .m_axi_arlen (lcl_cl_sh_ddra_q3.arlen), .m_axi_arsize (lcl_cl_sh_ddra_q3.arsize), .m_axi_arburst (), @@ -815,34 +815,34 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .m_axi_arcache (), .m_axi_arprot (), .m_axi_arregion (), - .m_axi_arqos (), + .m_axi_arqos (), .m_axi_arvalid (lcl_cl_sh_ddra_q3.arvalid), .m_axi_arready (lcl_cl_sh_ddra_q3.arready), - .m_axi_rid (lcl_cl_sh_ddra_q3.rid), - .m_axi_rdata (lcl_cl_sh_ddra_q3.rdata), - .m_axi_rresp (lcl_cl_sh_ddra_q3.rresp), - .m_axi_rlast (lcl_cl_sh_ddra_q3.rlast), - .m_axi_rvalid (lcl_cl_sh_ddra_q3.rvalid), + .m_axi_rid (lcl_cl_sh_ddra_q3.rid), + .m_axi_rdata (lcl_cl_sh_ddra_q3.rdata), + .m_axi_rresp (lcl_cl_sh_ddra_q3.rresp), + .m_axi_rlast (lcl_cl_sh_ddra_q3.rlast), + .m_axi_rvalid (lcl_cl_sh_ddra_q3.rvalid), .m_axi_rready (lcl_cl_sh_ddra_q3.rready) ); -//---------------------------- -// ATG/scrubber for DDRA -//---------------------------- - lib_pipe #(.WIDTH(32+32+1+1), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_CFG_REQ_DDR_A (.clk (aclk), - .rst_n (aresetn), +//---------------------------- +// ATG/scrubber for DDRA +//---------------------------- + lib_pipe #(.WIDTH(32+32+1+1), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_CFG_REQ_DDR_A (.clk (aclk), + .rst_n (aresetn), .in_bus({ddra_tst_cfg_bus.addr, ddra_tst_cfg_bus.wdata, ddra_tst_cfg_bus.wr, ddra_tst_cfg_bus.rd}), .out_bus({ddra_tst_cfg_bus_q.addr, ddra_tst_cfg_bus_q.wdata, ddra_tst_cfg_bus_q.wr, ddra_tst_cfg_bus_q.rd}) ); - - lib_pipe #(.WIDTH(32+1), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_CFG_ACK_DDR_A (.clk (aclk), - .rst_n (aresetn), + + lib_pipe #(.WIDTH(32+1), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_CFG_ACK_DDR_A (.clk (aclk), + .rst_n (aresetn), .in_bus({ddra_tst_cfg_bus_q.ack, ddra_tst_cfg_bus_q.rdata}), .out_bus({ddra_tst_cfg_bus.ack, ddra_tst_cfg_bus.rdata}) ); - lib_pipe #(.WIDTH(2+3+64), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_SCRB_DDR_A (.clk(aclk), + lib_pipe #(.WIDTH(2+3+64), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_SCRB_DDR_A (.clk(aclk), .rst_n(aresetn), .in_bus({ddra_scrb_bus.enable, ddra_scrb_bus_q.done, ddra_scrb_bus_q.state, ddra_scrb_bus_q.addr}), .out_bus({ddra_scrb_bus_q.enable, ddra_scrb_bus.done, ddra_scrb_bus.state, ddra_scrb_bus.addr}) @@ -852,7 +852,7 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .SCRB_BURST_LEN_MINUS1(SCRB_BURST_LEN_MINUS1), .SCRB_MAX_ADDR(SCRB_MAX_ADDR), .NO_SCRB_INST(NO_SCRB_INST)) CL_TST_DDR_A ( - + .clk(aclk), .rst_n(slr2_sync_aresetn), @@ -864,7 +864,7 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .tst_cfg_rdata(ddra_tst_cfg_bus_q.rdata), .slv_awid(lcl_cl_sh_ddra_q3.awid[6:0]), - .slv_awaddr(lcl_cl_sh_ddra_q3.awaddr), + .slv_awaddr(lcl_cl_sh_ddra_q3.awaddr), .slv_awlen(lcl_cl_sh_ddra_q3.awlen), .slv_awsize(lcl_cl_sh_ddra_q3.awsize), .slv_awvalid(lcl_cl_sh_ddra_q3.awvalid), @@ -885,12 +885,12 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .slv_bready(lcl_cl_sh_ddra_q3.bready), .slv_arid(lcl_cl_sh_ddra_q3.arid[6:0]), - .slv_araddr(lcl_cl_sh_ddra_q3.araddr), + .slv_araddr(lcl_cl_sh_ddra_q3.araddr), .slv_arlen(lcl_cl_sh_ddra_q3.arlen), .slv_arsize(lcl_cl_sh_ddra_q3.arsize), .slv_arvalid(lcl_cl_sh_ddra_q3.arvalid), .slv_aruser(11'b0), - .slv_arready(lcl_cl_sh_ddra_q3.arready), + .slv_arready(lcl_cl_sh_ddra_q3.arready), .slv_rid(lcl_cl_sh_ddra_q3.rid[6:0]), .slv_rdata(lcl_cl_sh_ddra_q3.rdata), @@ -900,9 +900,9 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .slv_rvalid(lcl_cl_sh_ddra_q3.rvalid), .slv_rready(lcl_cl_sh_ddra_q3.rready), - + .awid(lcl_cl_sh_ddra.awid[8:0]), - .awaddr(lcl_cl_sh_ddra.awaddr), + .awaddr(lcl_cl_sh_ddra.awaddr), .awlen(lcl_cl_sh_ddra.awlen), .awsize(lcl_cl_sh_ddra.awsize), .awvalid(lcl_cl_sh_ddra.awvalid), @@ -948,10 +948,10 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in assign lcl_cl_sh_ddra.wid[15:9] = 7'b0; assign lcl_cl_sh_ddra.arid[15:9] = 7'b0; -//---------------------------- +//---------------------------- // flop the output of interconnect for DDRB // back to back for SLR crossing -//---------------------------- +//---------------------------- //back to back register slices for SLR crossing src_register_slice DDR_B_TST_AXI4_REG_SLC_1 ( @@ -995,9 +995,9 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .s_axi_rresp (lcl_cl_sh_ddrb_q.rresp), .s_axi_rlast (lcl_cl_sh_ddrb_q.rlast), .s_axi_rvalid (lcl_cl_sh_ddrb_q.rvalid), - .s_axi_rready (lcl_cl_sh_ddrb_q.rready), - .m_axi_awid (lcl_cl_sh_ddrb_q2.awid), - .m_axi_awaddr (lcl_cl_sh_ddrb_q2.awaddr), + .s_axi_rready (lcl_cl_sh_ddrb_q.rready), + .m_axi_awid (lcl_cl_sh_ddrb_q2.awid), + .m_axi_awaddr (lcl_cl_sh_ddrb_q2.awaddr), .m_axi_awlen (lcl_cl_sh_ddrb_q2.awlen), .m_axi_awsize (lcl_cl_sh_ddrb_q2.awsize), .m_axi_awburst (), @@ -1005,35 +1005,35 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .m_axi_awcache (), .m_axi_awprot (), .m_axi_awregion (), - .m_axi_awqos (), + .m_axi_awqos (), .m_axi_awvalid (lcl_cl_sh_ddrb_q2.awvalid), .m_axi_awready (lcl_cl_sh_ddrb_q2.awready), - .m_axi_wdata (lcl_cl_sh_ddrb_q2.wdata), - .m_axi_wstrb (lcl_cl_sh_ddrb_q2.wstrb), - .m_axi_wlast (lcl_cl_sh_ddrb_q2.wlast), - .m_axi_wvalid (lcl_cl_sh_ddrb_q2.wvalid), - .m_axi_wready (lcl_cl_sh_ddrb_q2.wready), - .m_axi_bid (lcl_cl_sh_ddrb_q2.bid), - .m_axi_bresp (lcl_cl_sh_ddrb_q2.bresp), - .m_axi_bvalid (lcl_cl_sh_ddrb_q2.bvalid), - .m_axi_bready (lcl_cl_sh_ddrb_q2.bready), - .m_axi_arid (lcl_cl_sh_ddrb_q2.arid), - .m_axi_araddr (lcl_cl_sh_ddrb_q2.araddr), - .m_axi_arlen (lcl_cl_sh_ddrb_q2.arlen), + .m_axi_wdata (lcl_cl_sh_ddrb_q2.wdata), + .m_axi_wstrb (lcl_cl_sh_ddrb_q2.wstrb), + .m_axi_wlast (lcl_cl_sh_ddrb_q2.wlast), + .m_axi_wvalid (lcl_cl_sh_ddrb_q2.wvalid), + .m_axi_wready (lcl_cl_sh_ddrb_q2.wready), + .m_axi_bid (lcl_cl_sh_ddrb_q2.bid), + .m_axi_bresp (lcl_cl_sh_ddrb_q2.bresp), + .m_axi_bvalid (lcl_cl_sh_ddrb_q2.bvalid), + .m_axi_bready (lcl_cl_sh_ddrb_q2.bready), + .m_axi_arid (lcl_cl_sh_ddrb_q2.arid), + .m_axi_araddr (lcl_cl_sh_ddrb_q2.araddr), + .m_axi_arlen (lcl_cl_sh_ddrb_q2.arlen), .m_axi_arsize (lcl_cl_sh_ddrb_q2.arsize), .m_axi_arburst (), .m_axi_arlock (), .m_axi_arcache (), .m_axi_arprot (), .m_axi_arregion (), - .m_axi_arqos (), + .m_axi_arqos (), .m_axi_arvalid (lcl_cl_sh_ddrb_q2.arvalid), .m_axi_arready (lcl_cl_sh_ddrb_q2.arready), - .m_axi_rid (lcl_cl_sh_ddrb_q2.rid), - .m_axi_rdata (lcl_cl_sh_ddrb_q2.rdata), - .m_axi_rresp (lcl_cl_sh_ddrb_q2.rresp), - .m_axi_rlast (lcl_cl_sh_ddrb_q2.rlast), - .m_axi_rvalid (lcl_cl_sh_ddrb_q2.rvalid), + .m_axi_rid (lcl_cl_sh_ddrb_q2.rid), + .m_axi_rdata (lcl_cl_sh_ddrb_q2.rdata), + .m_axi_rresp (lcl_cl_sh_ddrb_q2.rresp), + .m_axi_rlast (lcl_cl_sh_ddrb_q2.rlast), + .m_axi_rvalid (lcl_cl_sh_ddrb_q2.rvalid), .m_axi_rready (lcl_cl_sh_ddrb_q2.rready) ); dest_register_slice DDR_B_TST_AXI4_REG_SLC_2 ( @@ -1077,9 +1077,9 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .s_axi_rresp (lcl_cl_sh_ddrb_q2.rresp), .s_axi_rlast (lcl_cl_sh_ddrb_q2.rlast), .s_axi_rvalid (lcl_cl_sh_ddrb_q2.rvalid), - .s_axi_rready (lcl_cl_sh_ddrb_q2.rready), - .m_axi_awid (lcl_cl_sh_ddrb_q3.awid), - .m_axi_awaddr (lcl_cl_sh_ddrb_q3.awaddr), + .s_axi_rready (lcl_cl_sh_ddrb_q2.rready), + .m_axi_awid (lcl_cl_sh_ddrb_q3.awid), + .m_axi_awaddr (lcl_cl_sh_ddrb_q3.awaddr), .m_axi_awlen (lcl_cl_sh_ddrb_q3.awlen), .m_axi_awsize (lcl_cl_sh_ddrb_q3.awsize), .m_axi_awburst (), @@ -1087,55 +1087,55 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .m_axi_awcache (), .m_axi_awprot (), .m_axi_awregion (), - .m_axi_awqos (), + .m_axi_awqos (), .m_axi_awvalid (lcl_cl_sh_ddrb_q3.awvalid), .m_axi_awready (lcl_cl_sh_ddrb_q3.awready), - .m_axi_wdata (lcl_cl_sh_ddrb_q3.wdata), - .m_axi_wstrb (lcl_cl_sh_ddrb_q3.wstrb), - .m_axi_wlast (lcl_cl_sh_ddrb_q3.wlast), - .m_axi_wvalid (lcl_cl_sh_ddrb_q3.wvalid), - .m_axi_wready (lcl_cl_sh_ddrb_q3.wready), - .m_axi_bid (lcl_cl_sh_ddrb_q3.bid), - .m_axi_bresp (lcl_cl_sh_ddrb_q3.bresp), - .m_axi_bvalid (lcl_cl_sh_ddrb_q3.bvalid), - .m_axi_bready (lcl_cl_sh_ddrb_q3.bready), - .m_axi_arid (lcl_cl_sh_ddrb_q3.arid), - .m_axi_araddr (lcl_cl_sh_ddrb_q3.araddr), - .m_axi_arlen (lcl_cl_sh_ddrb_q3.arlen), + .m_axi_wdata (lcl_cl_sh_ddrb_q3.wdata), + .m_axi_wstrb (lcl_cl_sh_ddrb_q3.wstrb), + .m_axi_wlast (lcl_cl_sh_ddrb_q3.wlast), + .m_axi_wvalid (lcl_cl_sh_ddrb_q3.wvalid), + .m_axi_wready (lcl_cl_sh_ddrb_q3.wready), + .m_axi_bid (lcl_cl_sh_ddrb_q3.bid), + .m_axi_bresp (lcl_cl_sh_ddrb_q3.bresp), + .m_axi_bvalid (lcl_cl_sh_ddrb_q3.bvalid), + .m_axi_bready (lcl_cl_sh_ddrb_q3.bready), + .m_axi_arid (lcl_cl_sh_ddrb_q3.arid), + .m_axi_araddr (lcl_cl_sh_ddrb_q3.araddr), + .m_axi_arlen (lcl_cl_sh_ddrb_q3.arlen), .m_axi_arsize (lcl_cl_sh_ddrb_q3.arsize), .m_axi_arburst (), .m_axi_arlock (), .m_axi_arcache (), .m_axi_arprot (), .m_axi_arregion (), - .m_axi_arqos (), + .m_axi_arqos (), .m_axi_arvalid (lcl_cl_sh_ddrb_q3.arvalid), .m_axi_arready (lcl_cl_sh_ddrb_q3.arready), - .m_axi_rid (lcl_cl_sh_ddrb_q3.rid), - .m_axi_rdata (lcl_cl_sh_ddrb_q3.rdata), - .m_axi_rresp (lcl_cl_sh_ddrb_q3.rresp), - .m_axi_rlast (lcl_cl_sh_ddrb_q3.rlast), - .m_axi_rvalid (lcl_cl_sh_ddrb_q3.rvalid), + .m_axi_rid (lcl_cl_sh_ddrb_q3.rid), + .m_axi_rdata (lcl_cl_sh_ddrb_q3.rdata), + .m_axi_rresp (lcl_cl_sh_ddrb_q3.rresp), + .m_axi_rlast (lcl_cl_sh_ddrb_q3.rlast), + .m_axi_rvalid (lcl_cl_sh_ddrb_q3.rvalid), .m_axi_rready (lcl_cl_sh_ddrb_q3.rready) ); -//---------------------------- -// ATG/scrubber for DDRB -//---------------------------- - lib_pipe #(.WIDTH(32+32+1+1), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_CFG_REQ_DDR_B (.clk (aclk), - .rst_n (aresetn), +//---------------------------- +// ATG/scrubber for DDRB +//---------------------------- + lib_pipe #(.WIDTH(32+32+1+1), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_CFG_REQ_DDR_B (.clk (aclk), + .rst_n (aresetn), .in_bus({ddrb_tst_cfg_bus.addr, ddrb_tst_cfg_bus.wdata, ddrb_tst_cfg_bus.wr, ddrb_tst_cfg_bus.rd}), .out_bus({ddrb_tst_cfg_bus_q.addr, ddrb_tst_cfg_bus_q.wdata, ddrb_tst_cfg_bus_q.wr, ddrb_tst_cfg_bus_q.rd}) ); - - lib_pipe #(.WIDTH(32+1), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_CFG_ACK_DDR_B (.clk (aclk), - .rst_n (aresetn), + + lib_pipe #(.WIDTH(32+1), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_CFG_ACK_DDR_B (.clk (aclk), + .rst_n (aresetn), .in_bus({ddrb_tst_cfg_bus_q.ack, ddrb_tst_cfg_bus_q.rdata}), .out_bus({ddrb_tst_cfg_bus.ack, ddrb_tst_cfg_bus.rdata}) ); - lib_pipe #(.WIDTH(2+3+64), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_SCRB_DDR_B (.clk(aclk), + lib_pipe #(.WIDTH(2+3+64), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_SCRB_DDR_B (.clk(aclk), .rst_n(aresetn), .in_bus({ddrb_scrb_bus.enable, ddrb_scrb_bus_q.done, ddrb_scrb_bus_q.state, ddrb_scrb_bus_q.addr}), .out_bus({ddrb_scrb_bus_q.enable, ddrb_scrb_bus.done, ddrb_scrb_bus.state, ddrb_scrb_bus.addr}) @@ -1145,7 +1145,7 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .SCRB_BURST_LEN_MINUS1(SCRB_BURST_LEN_MINUS1), .SCRB_MAX_ADDR(SCRB_MAX_ADDR), .NO_SCRB_INST(NO_SCRB_INST)) CL_TST_DDR_B ( - + .clk(aclk), .rst_n(slr1_sync_aresetn), @@ -1157,7 +1157,7 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .tst_cfg_rdata(ddrb_tst_cfg_bus_q.rdata), .slv_awid(lcl_cl_sh_ddrb_q3.awid[6:0]), - .slv_awaddr(lcl_cl_sh_ddrb_q3.awaddr), + .slv_awaddr(lcl_cl_sh_ddrb_q3.awaddr), .slv_awlen(lcl_cl_sh_ddrb_q3.awlen), .slv_awsize(lcl_cl_sh_ddrb_q3.awsize), .slv_awvalid(lcl_cl_sh_ddrb_q3.awvalid), @@ -1178,12 +1178,12 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .slv_bready(lcl_cl_sh_ddrb_q3.bready), .slv_arid(lcl_cl_sh_ddrb_q3.arid[6:0]), - .slv_araddr(lcl_cl_sh_ddrb_q3.araddr), + .slv_araddr(lcl_cl_sh_ddrb_q3.araddr), .slv_arlen(lcl_cl_sh_ddrb_q3.arlen), .slv_arsize(lcl_cl_sh_ddrb_q3.arsize), .slv_arvalid(lcl_cl_sh_ddrb_q3.arvalid), .slv_aruser(11'b0), - .slv_arready(lcl_cl_sh_ddrb_q3.arready), + .slv_arready(lcl_cl_sh_ddrb_q3.arready), .slv_rid(lcl_cl_sh_ddrb_q3.rid[6:0]), .slv_rdata(lcl_cl_sh_ddrb_q3.rdata), @@ -1193,9 +1193,9 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .slv_rvalid(lcl_cl_sh_ddrb_q3.rvalid), .slv_rready(lcl_cl_sh_ddrb_q3.rready), - + .awid(lcl_cl_sh_ddrb.awid[8:0]), - .awaddr(lcl_cl_sh_ddrb.awaddr), + .awaddr(lcl_cl_sh_ddrb.awaddr), .awlen(lcl_cl_sh_ddrb.awlen), .awsize(lcl_cl_sh_ddrb.awsize), .awvalid(lcl_cl_sh_ddrb.awvalid), @@ -1242,10 +1242,10 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in assign lcl_cl_sh_ddrb.arid[15:9] = 7'b0; -//---------------------------- -// flop the output of interconnect for DDRD +//---------------------------- +// flop the output of interconnect for DDRD // back to back for SLR crossing -//---------------------------- +//---------------------------- //back to back register slices for SLR crossing src_register_slice DDR_D_TST_AXI4_REG_SLC_1 ( @@ -1289,9 +1289,9 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .s_axi_rresp (lcl_cl_sh_ddrd_q.rresp), .s_axi_rlast (lcl_cl_sh_ddrd_q.rlast), .s_axi_rvalid (lcl_cl_sh_ddrd_q.rvalid), - .s_axi_rready (lcl_cl_sh_ddrd_q.rready), - .m_axi_awid (lcl_cl_sh_ddrd_q2.awid), - .m_axi_awaddr (lcl_cl_sh_ddrd_q2.awaddr), + .s_axi_rready (lcl_cl_sh_ddrd_q.rready), + .m_axi_awid (lcl_cl_sh_ddrd_q2.awid), + .m_axi_awaddr (lcl_cl_sh_ddrd_q2.awaddr), .m_axi_awlen (lcl_cl_sh_ddrd_q2.awlen), .m_axi_awsize (lcl_cl_sh_ddrd_q2.awsize), .m_axi_awburst (), @@ -1299,20 +1299,20 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .m_axi_awcache (), .m_axi_awprot (), .m_axi_awregion (), - .m_axi_awqos (), + .m_axi_awqos (), .m_axi_awvalid (lcl_cl_sh_ddrd_q2.awvalid), .m_axi_awready (lcl_cl_sh_ddrd_q2.awready), - .m_axi_wdata (lcl_cl_sh_ddrd_q2.wdata), - .m_axi_wstrb (lcl_cl_sh_ddrd_q2.wstrb), - .m_axi_wlast (lcl_cl_sh_ddrd_q2.wlast), - .m_axi_wvalid (lcl_cl_sh_ddrd_q2.wvalid), - .m_axi_wready (lcl_cl_sh_ddrd_q2.wready), - .m_axi_bid (lcl_cl_sh_ddrd_q2.bid), - .m_axi_bresp (lcl_cl_sh_ddrd_q2.bresp), - .m_axi_bvalid (lcl_cl_sh_ddrd_q2.bvalid), - .m_axi_bready (lcl_cl_sh_ddrd_q2.bready), - .m_axi_arid (lcl_cl_sh_ddrd_q2.arid), - .m_axi_araddr (lcl_cl_sh_ddrd_q2.araddr), + .m_axi_wdata (lcl_cl_sh_ddrd_q2.wdata), + .m_axi_wstrb (lcl_cl_sh_ddrd_q2.wstrb), + .m_axi_wlast (lcl_cl_sh_ddrd_q2.wlast), + .m_axi_wvalid (lcl_cl_sh_ddrd_q2.wvalid), + .m_axi_wready (lcl_cl_sh_ddrd_q2.wready), + .m_axi_bid (lcl_cl_sh_ddrd_q2.bid), + .m_axi_bresp (lcl_cl_sh_ddrd_q2.bresp), + .m_axi_bvalid (lcl_cl_sh_ddrd_q2.bvalid), + .m_axi_bready (lcl_cl_sh_ddrd_q2.bready), + .m_axi_arid (lcl_cl_sh_ddrd_q2.arid), + .m_axi_araddr (lcl_cl_sh_ddrd_q2.araddr), .m_axi_arlen (lcl_cl_sh_ddrd_q2.arlen), .m_axi_arsize (lcl_cl_sh_ddrd_q2.arsize), .m_axi_arburst (), @@ -1320,14 +1320,14 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .m_axi_arcache (), .m_axi_arprot (), .m_axi_arregion (), - .m_axi_arqos (), + .m_axi_arqos (), .m_axi_arvalid (lcl_cl_sh_ddrd_q2.arvalid), .m_axi_arready (lcl_cl_sh_ddrd_q2.arready), - .m_axi_rid (lcl_cl_sh_ddrd_q2.rid), - .m_axi_rdata (lcl_cl_sh_ddrd_q2.rdata), - .m_axi_rresp (lcl_cl_sh_ddrd_q2.rresp), - .m_axi_rlast (lcl_cl_sh_ddrd_q2.rlast), - .m_axi_rvalid (lcl_cl_sh_ddrd_q2.rvalid), + .m_axi_rid (lcl_cl_sh_ddrd_q2.rid), + .m_axi_rdata (lcl_cl_sh_ddrd_q2.rdata), + .m_axi_rresp (lcl_cl_sh_ddrd_q2.rresp), + .m_axi_rlast (lcl_cl_sh_ddrd_q2.rlast), + .m_axi_rvalid (lcl_cl_sh_ddrd_q2.rvalid), .m_axi_rready (lcl_cl_sh_ddrd_q2.rready) ); dest_register_slice DDR_D_TST_AXI4_REG_SLC_2 ( @@ -1371,9 +1371,9 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .s_axi_rresp (lcl_cl_sh_ddrd_q2.rresp), .s_axi_rlast (lcl_cl_sh_ddrd_q2.rlast), .s_axi_rvalid (lcl_cl_sh_ddrd_q2.rvalid), - .s_axi_rready (lcl_cl_sh_ddrd_q2.rready), - .m_axi_awid (lcl_cl_sh_ddrd_q3.awid), - .m_axi_awaddr (lcl_cl_sh_ddrd_q3.awaddr), + .s_axi_rready (lcl_cl_sh_ddrd_q2.rready), + .m_axi_awid (lcl_cl_sh_ddrd_q3.awid), + .m_axi_awaddr (lcl_cl_sh_ddrd_q3.awaddr), .m_axi_awlen (lcl_cl_sh_ddrd_q3.awlen), .m_axi_awsize (lcl_cl_sh_ddrd_q3.awsize), .m_axi_awburst (), @@ -1381,55 +1381,55 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .m_axi_awcache (), .m_axi_awprot (), .m_axi_awregion (), - .m_axi_awqos (), + .m_axi_awqos (), .m_axi_awvalid (lcl_cl_sh_ddrd_q3.awvalid), .m_axi_awready (lcl_cl_sh_ddrd_q3.awready), - .m_axi_wdata (lcl_cl_sh_ddrd_q3.wdata), - .m_axi_wstrb (lcl_cl_sh_ddrd_q3.wstrb), - .m_axi_wlast (lcl_cl_sh_ddrd_q3.wlast), - .m_axi_wvalid (lcl_cl_sh_ddrd_q3.wvalid), - .m_axi_wready (lcl_cl_sh_ddrd_q3.wready), - .m_axi_bid (lcl_cl_sh_ddrd_q3.bid), - .m_axi_bresp (lcl_cl_sh_ddrd_q3.bresp), - .m_axi_bvalid (lcl_cl_sh_ddrd_q3.bvalid), - .m_axi_bready (lcl_cl_sh_ddrd_q3.bready), - .m_axi_arid (lcl_cl_sh_ddrd_q3.arid), - .m_axi_araddr (lcl_cl_sh_ddrd_q3.araddr), - .m_axi_arlen (lcl_cl_sh_ddrd_q3.arlen), + .m_axi_wdata (lcl_cl_sh_ddrd_q3.wdata), + .m_axi_wstrb (lcl_cl_sh_ddrd_q3.wstrb), + .m_axi_wlast (lcl_cl_sh_ddrd_q3.wlast), + .m_axi_wvalid (lcl_cl_sh_ddrd_q3.wvalid), + .m_axi_wready (lcl_cl_sh_ddrd_q3.wready), + .m_axi_bid (lcl_cl_sh_ddrd_q3.bid), + .m_axi_bresp (lcl_cl_sh_ddrd_q3.bresp), + .m_axi_bvalid (lcl_cl_sh_ddrd_q3.bvalid), + .m_axi_bready (lcl_cl_sh_ddrd_q3.bready), + .m_axi_arid (lcl_cl_sh_ddrd_q3.arid), + .m_axi_araddr (lcl_cl_sh_ddrd_q3.araddr), + .m_axi_arlen (lcl_cl_sh_ddrd_q3.arlen), .m_axi_arsize (lcl_cl_sh_ddrd_q3.arsize), .m_axi_arburst (), .m_axi_arlock (), .m_axi_arcache (), .m_axi_arprot (), .m_axi_arregion (), - .m_axi_arqos (), + .m_axi_arqos (), .m_axi_arvalid (lcl_cl_sh_ddrd_q3.arvalid), .m_axi_arready (lcl_cl_sh_ddrd_q3.arready), - .m_axi_rid (lcl_cl_sh_ddrd_q3.rid), - .m_axi_rdata (lcl_cl_sh_ddrd_q3.rdata), - .m_axi_rresp (lcl_cl_sh_ddrd_q3.rresp), - .m_axi_rlast (lcl_cl_sh_ddrd_q3.rlast), - .m_axi_rvalid (lcl_cl_sh_ddrd_q3.rvalid), + .m_axi_rid (lcl_cl_sh_ddrd_q3.rid), + .m_axi_rdata (lcl_cl_sh_ddrd_q3.rdata), + .m_axi_rresp (lcl_cl_sh_ddrd_q3.rresp), + .m_axi_rlast (lcl_cl_sh_ddrd_q3.rlast), + .m_axi_rvalid (lcl_cl_sh_ddrd_q3.rvalid), .m_axi_rready (lcl_cl_sh_ddrd_q3.rready) ); -//---------------------------- -// ATG/scrubber for DDRD -//---------------------------- - lib_pipe #(.WIDTH(32+32+1+1), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_CFG_REQ_DDR_D (.clk (aclk), - .rst_n (aresetn), +//---------------------------- +// ATG/scrubber for DDRD +//---------------------------- + lib_pipe #(.WIDTH(32+32+1+1), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_CFG_REQ_DDR_D (.clk (aclk), + .rst_n (aresetn), .in_bus({ddrd_tst_cfg_bus.addr, ddrd_tst_cfg_bus.wdata, ddrd_tst_cfg_bus.wr, ddrd_tst_cfg_bus.rd}), .out_bus({ddrd_tst_cfg_bus_q.addr, ddrd_tst_cfg_bus_q.wdata, ddrd_tst_cfg_bus_q.wr, ddrd_tst_cfg_bus_q.rd}) ); - - lib_pipe #(.WIDTH(32+1), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_CFG_ACK_DDR_D (.clk (aclk), - .rst_n (aresetn), + + lib_pipe #(.WIDTH(32+1), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_CFG_ACK_DDR_D (.clk (aclk), + .rst_n (aresetn), .in_bus({ddrd_tst_cfg_bus_q.ack, ddrd_tst_cfg_bus_q.rdata}), .out_bus({ddrd_tst_cfg_bus.ack, ddrd_tst_cfg_bus.rdata}) ); - lib_pipe #(.WIDTH(2+3+64), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_SCRB_DDR_D (.clk(aclk), + lib_pipe #(.WIDTH(2+3+64), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_SCRB_DDR_D (.clk(aclk), .rst_n(aresetn), .in_bus({ddrd_scrb_bus.enable, ddrd_scrb_bus_q.done, ddrd_scrb_bus_q.state, ddrd_scrb_bus_q.addr}), .out_bus({ddrd_scrb_bus_q.enable, ddrd_scrb_bus.done, ddrd_scrb_bus.state, ddrd_scrb_bus.addr}) @@ -1439,7 +1439,7 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .SCRB_BURST_LEN_MINUS1(SCRB_BURST_LEN_MINUS1), .SCRB_MAX_ADDR(SCRB_MAX_ADDR), .NO_SCRB_INST(NO_SCRB_INST)) CL_TST_DDR_D ( - + .clk(aclk), .rst_n(slr0_sync_aresetn), @@ -1451,7 +1451,7 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .tst_cfg_rdata(ddrd_tst_cfg_bus_q.rdata), .slv_awid(lcl_cl_sh_ddrd_q3.awid[6:0]), - .slv_awaddr(lcl_cl_sh_ddrd_q3.awaddr), + .slv_awaddr(lcl_cl_sh_ddrd_q3.awaddr), .slv_awlen(lcl_cl_sh_ddrd_q3.awlen), .slv_awsize(lcl_cl_sh_ddrd_q3.awsize), .slv_awvalid(lcl_cl_sh_ddrd_q3.awvalid), @@ -1472,12 +1472,12 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .slv_bready(lcl_cl_sh_ddrd_q3.bready), .slv_arid(lcl_cl_sh_ddrd_q3.arid[6:0]), - .slv_araddr(lcl_cl_sh_ddrd_q3.araddr), + .slv_araddr(lcl_cl_sh_ddrd_q3.araddr), .slv_arlen(lcl_cl_sh_ddrd_q3.arlen), - .slv_arsize(lcl_cl_sh_ddrd_q3.arsize), + .slv_arsize(lcl_cl_sh_ddrd_q3.arsize), .slv_arvalid(lcl_cl_sh_ddrd_q3.arvalid), .slv_aruser(11'b0), - .slv_arready(lcl_cl_sh_ddrd_q3.arready), + .slv_arready(lcl_cl_sh_ddrd_q3.arready), .slv_rid(lcl_cl_sh_ddrd_q3.rid[6:0]), .slv_rdata(lcl_cl_sh_ddrd_q3.rdata), @@ -1487,9 +1487,9 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in .slv_rvalid(lcl_cl_sh_ddrd_q3.rvalid), .slv_rready(lcl_cl_sh_ddrd_q3.rready), - + .awid(lcl_cl_sh_ddrd.awid[8:0]), - .awaddr(lcl_cl_sh_ddrd.awaddr), + .awaddr(lcl_cl_sh_ddrd.awaddr), .awlen(lcl_cl_sh_ddrd.awlen), .awvalid(lcl_cl_sh_ddrd.awvalid), .awsize(lcl_cl_sh_ddrd.awsize), diff --git a/hdk/cl/examples/cl_dram_dma/design/cl_mstr_axi_tst.sv b/hdk/cl/examples/cl_dram_dma/design/cl_mstr_axi_tst.sv deleted file mode 100644 index 7d445c9b..00000000 --- a/hdk/cl/examples/cl_dram_dma/design/cl_mstr_axi_tst.sv +++ /dev/null @@ -1,468 +0,0 @@ -// Amazon FPGA Hardware Development Kit -// -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. -// -// Licensed under the Amazon Software License (the "License"). You may not use -// this file except in compliance with the License. A copy of the License is -// located at -// -// http://aws.amazon.com/asl/ -// -// or in the "license" file accompanying this file. This file is distributed on -// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or -// implied. See the License for the specific language governing permissions and -// limitations under the License. - -// AXI Transaction Generator - -module cl_mstr_axi_tst #(parameter DATA_WIDTH = 512, - parameter ADDR_WIDTH = 64, - parameter A_ID_WIDTH = 5, - parameter D_ID_WIDTH = 5, - parameter LEN_WIDTH = 8, - parameter A_USER_WIDTH = 10, - parameter W_USER_WIDTH = 10, - parameter B_USER_WIDTH = 10, - parameter R_USER_WIDTH = 10, - parameter RST_SYNC = 1 - ) - ( - input clk, - input rst_n, - - input [31:0] cfg_addr, - input [31:0] cfg_wdata, - input cfg_wr, - input cfg_rd, - output logic tst_cfg_ack, - output logic [31:0] tst_cfg_rdata, - - output logic [A_ID_WIDTH-1:0] awid, - output logic [ADDR_WIDTH-1:0] awaddr, - output logic [LEN_WIDTH-1:0] awlen, - output logic awvalid, - output logic [A_USER_WIDTH-1:0] awuser, - input awready, - - output logic [5:0] wid, - output logic [DATA_WIDTH-1:0] wdata, - output logic [(DATA_WIDTH/8)-1:0] wstrb, - output logic wlast, - output logic wvalid, - output logic [W_USER_WIDTH-1:0] wuser, - input wready, - - input [D_ID_WIDTH-1:0] bid, - input [1:0] bresp, - input bvalid, - input [B_USER_WIDTH-1:0] buser, - output logic bready, - - output logic [A_ID_WIDTH-1:0] arid, - output logic [ADDR_WIDTH-1:0] araddr, - output logic [LEN_WIDTH-1:0] arlen, - output logic arvalid, - output logic [A_USER_WIDTH-1:0] aruser, - input arready, - - input [D_ID_WIDTH-1:0] rid, - input [DATA_WIDTH-1:0] rdata, - input [1:0] rresp, - input rlast, - input rvalid, - input [R_USER_WIDTH-1:0] ruser, - output logic rready - ); - -`include "cl_common_defines.vh" // CL Defines for all examples - - // Registers - - // Write Address Channel - // 0x0 : Write Address Control - // 0 : Set AW Valid (Write), AWVALID (Read) - // 1 : AW Done (W1C) - // 0x4 : Write Address [31:0] - // 0x8 : Write Address [63:32] - // 0xC : AW Length and ID - // 15:00 : AW Length - // 31:16 : AW ID - // 0x10 : AW User - - // Write Data Channel - // 0x20 : Write Data Control - // 0 : Set W Valid (Write), WVALID (Read) - // 1 : W Done (W1C) - // 3:2 : RSVD - // 4 : WLAST - // 0x24 : Write Data Index (Auto Increment on Write Data Write) - // 0x28 : Write Data - // 0x2C : Write Strobe [31:00] - // 0x30 : Write Strobe [63:32] - // 0x34 : Write ID - // 0x38 : Write User - - // Write Resp Channel - // 0x40 : B Channel Control (BRESP) - // 0 : Set B Ready (Write), BREADY (Read) - // 1 : B Done (W1C) - // 3:2 : B RESP (RO) - // 0x44 : B ID (RO) - // 0x48 : B User (RO) - - // Read Address Channel - // 0x60 : Read Address Control - // 0 : Set AR Valid (Write), ARVALID (Read) - // 1 : AR Done (W1C) - // 0x64 : Read Address [31:00] - // 0x68 : Read Address [63:32] - // 0x6C : AR Length and ID - // 15:00 : AR Length - // 31:16 : AR ID - // 0x70 : AR User - - // Read Data Channel - // 0x80 : Read Channel Control (RRESP, RLAST) - // 0 : Set R Ready (Write), RREADY (Read) - // 1 : R Done (W1C) - // 3:2 : R RESP (RO) - // 4 : R LAST (RO) - // 0x84 : Read Data Index (Auto Increment on Read Data Read) - // 0x88 : Read Data - // 0x8C : Read ID (RO) - // 0x90 : Read User (RO) - - parameter NUM_DW = DATA_WIDTH / 32; - - logic pre_sync_rst_n; - logic sync_rst_n; - - // Synchronize RST - generate - if (RST_SYNC != 0) - always_ff @(negedge rst_n or posedge clk) - if (!rst_n) - begin - pre_sync_rst_n <= 0; - sync_rst_n <= 0; - end - else - begin - pre_sync_rst_n <= 1; - sync_rst_n <= pre_sync_rst_n; - end - else - assign sync_rst_n = rst_n; - endgenerate - - logic cfg_wr_stretch; - logic cfg_rd_stretch; - - logic [7:0] cfg_addr_q; //Only care about lower 8-bits of address, upper bits are decoded somewhere else - logic [31:0] cfg_wdata_q; - - logic cfg_aw_done; - logic [63:0] cfg_aw_addr; - logic [LEN_WIDTH-1:0] cfg_aw_len; - logic [A_ID_WIDTH-1:0] cfg_aw_id; - logic [A_USER_WIDTH-1:0] cfg_aw_user; - logic cfg_w_done; - logic [DATA_WIDTH-1:0] cfg_w_data; - logic [15:0] cfg_w_index; - logic [31:0] cfg_w_data_mx; - logic [D_ID_WIDTH-1:0] cfg_w_id; - logic [W_USER_WIDTH-1:0] cfg_w_user; - logic [63:0] cfg_w_strb; - logic cfg_w_last; - logic cfg_b_done; - logic [1:0] cfg_b_resp; - logic [D_ID_WIDTH-1:0] cfg_b_id; - logic [B_USER_WIDTH-1:0] cfg_b_user; - logic cfg_ar_done; - logic [63:0] cfg_ar_addr; - logic [LEN_WIDTH-1:0] cfg_ar_len; - logic [A_ID_WIDTH-1:0] cfg_ar_id; - logic [A_USER_WIDTH-1:0] cfg_ar_user; - logic cfg_r_done; - logic [DATA_WIDTH-1:0] cfg_r_data; - logic cfg_r_last; - logic [1:0] cfg_r_resp; - logic [D_ID_WIDTH-1:0] cfg_r_id; - logic [R_USER_WIDTH-1:0] cfg_r_user; - logic [31:0] cfg_r_data_mx; - logic [15:0] cfg_r_index; - - //Commands are single cycle pulse, stretch here - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - begin - cfg_wr_stretch <= 0; - cfg_rd_stretch <= 0; - cfg_addr_q <= 0; - cfg_wdata_q <= 0; - end - else - begin - cfg_wr_stretch <= cfg_wr || (cfg_wr_stretch && !tst_cfg_ack); - cfg_rd_stretch <= cfg_rd || (cfg_rd_stretch && !tst_cfg_ack); - if (cfg_wr||cfg_rd) - begin - cfg_addr_q <= cfg_addr[7:0]; - cfg_wdata_q <= cfg_wdata; - end - end // else: !if(!sync_rst_n) - - //Ack for cycle - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - tst_cfg_ack <= 0; - else - tst_cfg_ack <= ((cfg_wr_stretch||cfg_rd_stretch) && !tst_cfg_ack); - - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) begin - cfg_aw_addr <= '{default:'0}; - cfg_aw_len <= '{default:'0}; - cfg_aw_id <= '{default:'0}; - cfg_aw_user <= '{default:'0}; - - cfg_w_last <= 1'b0; - cfg_w_strb <= '{default:'0}; - cfg_w_id <= '{default:'0}; - cfg_w_user <= '{default:'0}; - - cfg_ar_addr <= '{default:'0}; - cfg_ar_len <= '{default:'0}; - cfg_ar_id <= '{default:'0}; - cfg_ar_user <= '{default:'0}; - - end // if (!sync_rst_n) - else if (cfg_wr_stretch) begin - if (cfg_addr_q == 8'h04) - cfg_aw_addr[31:0] <= cfg_wdata_q; - else if (cfg_addr_q == 8'h08) - cfg_aw_addr[63:32] <= cfg_wdata_q; - else if (cfg_addr_q == 8'h0C) - {cfg_aw_id, cfg_aw_len} <= cfg_wdata_q; - else if (cfg_addr_q == 8'h10) - cfg_aw_user <= cfg_wdata_q; - - - else if (cfg_addr_q == 8'h20) - cfg_w_last <= cfg_wdata_q[4]; - else if (cfg_addr_q == 8'h2C) - cfg_w_strb[31:0] <= cfg_wdata_q; - else if (cfg_addr_q == 8'h30) - cfg_w_strb[63:32] <= cfg_wdata_q; - else if (cfg_addr_q == 8'h34) - cfg_w_id <= cfg_wdata_q; - else if (cfg_addr_q == 8'h38) - cfg_w_user <= cfg_wdata_q; - - - else if (cfg_addr_q == 8'h64) - cfg_ar_addr[31:0] <= cfg_wdata_q; - else if (cfg_addr_q == 8'h68) - cfg_ar_addr[63:32] <= cfg_wdata_q; - else if (cfg_addr_q == 8'h6C) - {cfg_ar_id, cfg_ar_len} <= cfg_wdata_q; - else if (cfg_addr_q == 8'h70) - cfg_ar_user <= cfg_wdata_q; - - end // if (cfg_wr_stretch) - - //Readback mux - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - tst_cfg_rdata <= 0; - else - case (cfg_addr_q) - 8'h00 : tst_cfg_rdata <= {cfg_aw_done, awvalid}; - 8'h04 : tst_cfg_rdata <= cfg_aw_addr[31:0]; - 8'h08 : tst_cfg_rdata <= cfg_aw_addr[63:32]; - 8'h0C : tst_cfg_rdata <= {cfg_aw_id, cfg_aw_len}; - 8'h10 : tst_cfg_rdata <= cfg_aw_user; - - 8'h20 : tst_cfg_rdata <= {cfg_w_last, 2'b00, cfg_w_done, wvalid}; - 8'h24 : tst_cfg_rdata <= cfg_w_index; - 8'h28 : tst_cfg_rdata <= cfg_w_data_mx; - 8'h2C : tst_cfg_rdata <= cfg_w_strb[31:0]; - 8'h30 : tst_cfg_rdata <= cfg_w_strb[63:32]; - 8'h34 : tst_cfg_rdata <= cfg_w_id; - 8'h38 : tst_cfg_rdata <= cfg_w_user; - - 8'h40 : tst_cfg_rdata <= {cfg_b_resp, cfg_b_done, bready}; - 8'h44 : tst_cfg_rdata <= cfg_b_id; - 8'h48 : tst_cfg_rdata <= cfg_b_user; - - 8'h60 : tst_cfg_rdata <= {cfg_ar_done, arvalid}; - 8'h64 : tst_cfg_rdata <= cfg_ar_addr[31:0]; - 8'h68 : tst_cfg_rdata <= cfg_ar_addr[63:32]; - 8'h6C : tst_cfg_rdata <= {cfg_ar_id, cfg_ar_len}; - 8'h70 : tst_cfg_rdata <= cfg_ar_user; - - 8'h80 : tst_cfg_rdata <= {cfg_r_last, cfg_r_resp, cfg_r_done, rready}; - 8'h84 : tst_cfg_rdata <= cfg_r_index; - 8'h88 : tst_cfg_rdata <= cfg_r_data_mx; - 8'h8C : tst_cfg_rdata <= cfg_r_id; - 8'h90 : tst_cfg_rdata <= cfg_r_user; - - //default: tst_cfg_rdata <= 32'hdeaddead; - default: tst_cfg_rdata <= `UNIMPLEMENTED_REG_VALUE; - endcase // case (cfg_addr_q) - - - ///////////////////////// AW Channel /////////////////////////// - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - awvalid <= 1'b0; - else - awvalid <= cfg_wr_stretch && cfg_wdata_q[0] && (cfg_addr_q == 8'h00) ? 1'b1 : - awvalid && awready ? 1'b0 : - awvalid; - - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - cfg_aw_done <= 1'b0; - else - cfg_aw_done <= awvalid && awready ? 1'b1 : - cfg_wr_stretch && cfg_wdata_q[1] && (cfg_addr_q == 8'h00) ? 1'b0 : - cfg_aw_done; - - assign awaddr = cfg_aw_addr; - assign awlen = cfg_aw_len; - assign awid = cfg_aw_id; - assign awuser = cfg_aw_user; - - ///////////////////////// W Channel /////////////////////////// - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - wvalid <= 1'b0; - else - wvalid <= cfg_wr_stretch && cfg_wdata_q[0] && (cfg_addr_q == 8'h20) ? 1'b1 : - wvalid && wready ? 1'b0 : - wvalid; - - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - cfg_w_done <= 1'b0; - else - cfg_w_done <= wvalid && wready ? 1'b1 : - cfg_wr_stretch && cfg_wdata_q[1] && (cfg_addr_q == 8'h20) ? 1'b0 : - cfg_w_done; - - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - cfg_w_data <= '{default:'0}; - else - for (int idx = 0; idx < NUM_DW; idx ++) - if ((idx == cfg_w_index) && cfg_wr_stretch && (cfg_addr_q == 8'h28)) - cfg_w_data[32*idx +: 32] <= cfg_wdata_q; - else - cfg_w_data[32*idx +: 32] <= cfg_w_data[32*idx +: 32]; - - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - cfg_w_index <= '{default:'0}; - else - cfg_w_index <= cfg_wr_stretch && (cfg_addr_q == 8'h24) ? cfg_wdata_q : - cfg_wr_stretch && (cfg_addr_q == 8'h28) ? (cfg_w_index + 1) : cfg_w_index; - - always_comb - begin - cfg_w_data_mx = 0; - for (int idx = 0; idx < NUM_DW; idx ++) - if (idx == cfg_w_index) - cfg_w_data_mx = cfg_w_data[32*idx +: 32]; - end - - assign wid = cfg_w_id; - assign wuser = cfg_w_user; - assign wdata = cfg_w_data; - assign wstrb = cfg_w_strb; - assign wlast = cfg_w_last; - - ///////////////////////// B Channel /////////////////////////// - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - bready <= 1'b0; - else - bready <= cfg_wr_stretch && cfg_wdata_q[0] && (cfg_addr_q == 8'h40) ? 1'b1 : - bvalid && bready ? 1'b0 : - bready; - - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - cfg_b_done <= 1'b0; - else - cfg_b_done <= bvalid && bready ? 1'b1 : - cfg_wr_stretch && cfg_wdata_q[1] && (cfg_addr_q == 8'h40) ? 1'b0 : - cfg_b_done; - - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - {cfg_b_resp, cfg_b_id, cfg_b_user} <= '{default:'0}; - else - {cfg_b_resp, cfg_b_id, cfg_b_user} <= bvalid && bready ? {bresp, bid, buser} : {cfg_b_resp, cfg_b_id, cfg_b_user}; - - ///////////////////////// AR Channel /////////////////////////// - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - arvalid <= 1'b0; - else - arvalid <= cfg_wr_stretch && cfg_wdata_q[0] && (cfg_addr_q == 8'h60) ? 1'b1 : - arvalid && arready ? 1'b0 : - arvalid; - - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - cfg_ar_done <= 1'b0; - else - cfg_ar_done <= arvalid && arready ? 1'b1 : - cfg_wr_stretch && cfg_wdata_q[1] && (cfg_addr_q == 8'h60) ? 1'b0 : - cfg_ar_done; - - assign araddr = cfg_ar_addr; - assign arlen = cfg_ar_len; - assign arid = cfg_ar_id; - assign aruser = cfg_ar_user; - - ///////////////////////// R Channel /////////////////////////// - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - rready <= 1'b0; - else - rready <= cfg_wr_stretch && cfg_wdata_q[0] && (cfg_addr_q == 8'h80) ? 1'b1 : - rvalid && rready ? 1'b0 : - rready; - - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - cfg_r_done <= 1'b0; - else - cfg_r_done <= rvalid && rready ? 1'b1 : - cfg_wr_stretch && cfg_wdata_q[1] && (cfg_addr_q == 8'h80) ? 1'b0 : - cfg_r_done; - - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - {cfg_r_data, cfg_r_last, cfg_r_resp, cfg_r_id, cfg_r_user} <= '{default:'0}; - else - {cfg_r_data, cfg_r_last, cfg_r_resp, cfg_r_id, cfg_r_user} <= rvalid && rready ? {rdata, rlast, rresp, rid, ruser} : {cfg_r_data, cfg_r_last, cfg_r_resp, cfg_r_id, cfg_r_user}; - - always_ff @(negedge sync_rst_n or posedge clk) - if (!sync_rst_n) - cfg_r_index <= '{default:'0}; - else - cfg_r_index <= cfg_wr_stretch && (cfg_addr_q == 8'h84) ? cfg_wdata_q : - cfg_rd_stretch && (cfg_addr_q == 8'h88) ? (cfg_r_index + 1) : cfg_r_index; - - always_comb begin - cfg_r_data_mx = 0; - for (int idx = 0; idx < NUM_DW; idx ++) - if (idx == cfg_r_index) - cfg_r_data_mx = cfg_r_data[32*idx +: 32]; - end - -endmodule // cl_mstr_axi_tst - diff --git a/hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma.c b/hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma.c index 9b9dd3e6..060cdbdf 100644 --- a/hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma.c +++ b/hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma.c @@ -167,7 +167,7 @@ int dma_example(int slot_id, size_t buffer_size) { return (rc != 0 ? 1 : 0); } -int interrupt_example(int slot_id, int interrupt_number){ +int interrupt_example(int slot_id, int interrupt_number) { pci_bar_handle_t pci_bar_handle = PCI_BAR_HANDLE_INIT; struct pollfd fds[1]; uint32_t fd, rd, read_data; @@ -181,23 +181,26 @@ int interrupt_example(int slot_id, int interrupt_number){ int poll_limit = 20; uint32_t interrupt_reg_offset = 0xd00; + int device_num = 0; + rc = fpga_pci_get_dma_device_num(FPGA_DMA_XDMA, slot_id, &device_num); + fail_on((rc = (rc != 0)? 1:0), out, "Unable to get xdma device number."); - rc = sprintf(event_file_name, "/dev/xdma%i_events_%i", slot_id, interrupt_number); + rc = sprintf(event_file_name, "/dev/xdma%i_events_%i", device_num, interrupt_number); fail_on((rc = (rc < 0)? 1:0), out, "Unable to format event file name."); - printf("Starting MSI-X Interrupt test \n"); + log_info("Starting MSI-X Interrupt test"); rc = fpga_pci_attach(slot_id, pf_id, bar_id, fpga_attach_flags, &pci_bar_handle); fail_on(rc, out, "Unable to attach to the AFI on slot id %d", slot_id); - printf("Polling device file: %s for interrupt events \n", event_file_name); + log_info("Polling device file: %s for interrupt events", event_file_name); if((fd = open(event_file_name, O_RDONLY)) == -1) { - printf("Error - invalid device\n"); + log_error("Error - invalid device\n"); fail_on((rc = 1), out, "Unable to open event device"); } fds[0].fd = fd; fds[0].events = POLLIN; - printf("Triggering MSI-X Interrupt %d\n", interrupt_number); + log_info("Triggering MSI-X Interrupt %d", interrupt_number); rc = fpga_pci_poke(pci_bar_handle, interrupt_reg_offset , 1 << interrupt_number); fail_on(rc, out, "Unable to write to the fpga !"); @@ -211,7 +214,7 @@ int interrupt_example(int slot_id, int interrupt_number){ rc = pread(fd, &events_user, sizeof(events_user), 0); fail_on((rc = (rc < 0)? 1:0), out, "call to pread failed."); - printf("Interrupt present for Interrupt %i, events %i. It worked!\n", + log_info("Interrupt present for Interrupt %i, events %i. It worked!", interrupt_number, events_user); //Clear the interrupt register @@ -219,7 +222,7 @@ int interrupt_example(int slot_id, int interrupt_number){ fail_on(rc, out, "Unable to write to the fpga !"); } else{ - printf("No interrupt generated- something went wrong.\n"); + log_error("No interrupt generated- something went wrong."); fail_on((rc = 1), out, "Interrupt generation failed"); } close(fd); @@ -256,7 +259,7 @@ int axi_mstr_example(int slot_id) { rc = fpga_pci_attach(slot_id, pf_id, bar_id, fpga_attach_flags, &pci_bar_handle); fail_on(rc, out, "Unable to attach to the AFI on slot id %d", slot_id); - printf("Starting AXI Master to DDR test \n"); + log_info("Starting AXI Master to DDR test"); /* DDR A Access */ ddr_hi_addr = 0x00000001; @@ -346,7 +349,7 @@ int axi_mstr_ddr_access(int slot_id, pci_bar_handle_t pci_bar_handle, uint32_t d fail_on(rc, out, "Unable to read AXI Master CRDR from the fpga !"); if(read_data == ddr_data) { rc = 0; - printf("Resulting value at address 0x%x%x matched expected value 0x%x. It worked!\n", ddr_hi_addr, ddr_lo_addr, ddr_data); + log_info("Resulting value at address 0x%x%x matched expected value 0x%x. It worked!", ddr_hi_addr, ddr_lo_addr, ddr_data); } else{ rc = 1; diff --git a/hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma_common.c b/hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma_common.c index bb545464..7096379a 100644 --- a/hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma_common.c +++ b/hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma_common.c @@ -123,6 +123,16 @@ int check_slot_config(int slot_id) "not the expected values."); } + char dbdf[16]; + snprintf(dbdf, + sizeof(dbdf), + PCI_DEV_FMT, + info.spec.map[FPGA_APP_PF].domain, + info.spec.map[FPGA_APP_PF].bus, + info.spec.map[FPGA_APP_PF].dev, + info.spec.map[FPGA_APP_PF].func); + log_info("Operating on slot %d with id: %s", slot_id, dbdf); + out: return rc; } diff --git a/hdk/cl/examples/cl_sde/verif/scripts/Makefile b/hdk/cl/examples/cl_sde/verif/scripts/Makefile index 9e72dfbc..793c0d20 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/Makefile +++ b/hdk/cl/examples/cl_sde/verif/scripts/Makefile @@ -12,8 +12,13 @@ # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or # implied. See the License for the specific language governing permissions and # limitations under the License. -# -## + +ifndef VIVADO_TOOL_VERSION +$(error Environment variable VIVADO_TOOL_VERSION not set. please source hdk_setup.sh) +else +$(info VIVADO_TOOL_VERSION = $(VIVADO_TOOL_VERSION)) +endif + export TEST ?= test_null export C_TEST ?= test_null @@ -36,30 +41,27 @@ endif export SIM_ROOT = $(CL_ROOT)/verif/sim/$(SIMULATOR) - ifeq ($(C_TEST),test_null) export SIM_DIR = $(SIM_ROOT)/$(TEST) else export SIM_DIR = $(SIM_ROOT)/$(C_TEST) endif - - + + export SCRIPTS_DIR = $(PWD) export XILINX_IP = $(HDK_SHELL_DESIGN_DIR)/ip export SH_LIB_DIR = $(HDK_SHELL_DESIGN_DIR)/lib export SH_INF_DIR = $(HDK_SHELL_DESIGN_DIR)/interfaces export SH_SH_DIR = $(HDK_SHELL_DESIGN_DIR)/sh_ddr/sim -SV_TEST_LIST = test_hello_world +SV_TEST_LIST = test_null.sv C_FILES = $(C_TEST_NAME) $(C_SDK_USR_UTILS_DIR)/sh_dpi_tasks.c $(C_COMMON_DIR)/src/fpga_pci_sv.c -C_TEST_LIST = test_hello_world.c - ifeq ($(XCHK), 1) all: make_sim_dir compile_chk run else all: make_sim_dir compile run endif - include $(HDK_COMMON_DIR)/verif/tb/scripts/Makefile.common.inc +include $(HDK_COMMON_DIR)/verif/tb/scripts/Makefile.common.inc diff --git a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.questa b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.questa index 8d84c562..566d0eee 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.questa +++ b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.questa @@ -24,12 +24,24 @@ compile: $(COMPLIB_DIR) mkdir -p $(SIM_DIR) - cd ${SIM_DIR} && ln -s -f ../questa_complib/modelsim.ini - cd $(SIM_DIR) && vlog $(C_TEST_NAME) -ccflags "-I$(C_INC_DIR)" + cd ${SIM_DIR} && ln -s -f ../questa_complib/modelsim.ini + cd $(SIM_DIR) && vlog $(C_FILES) -ccflags "-I$(C_SDK_USR_INC_DIR)" -ccflags "-I$(C_SDK_USR_UTILS_DIR)" -ccflags "-I$(C_COMMON_DIR)/include" -ccflags "-I$(C_COMMON_DIR)/src" -ccflags "-DSV_TEST" -ccflags "-DSCOPE" -ccflags "-DQUESTA_SIM" -ccflags "-DINT_MAIN" -ccflags "-I$(C_INC_DIR)" cd $(SIM_DIR) && vlog -mfcu -sv -64 -timescale 1ps/1ps -93 -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/secureip -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f run: - cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_12 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_13 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_11 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_11 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -do "run -all; quit -f" tb glbl $(TEST) +ifeq ($(VIVADO_TOOL_VERSION), v2017.4) +ifeq ($(TEST),test_null) + cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_15 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_16 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_14 -L $(COMPLIB_DIR)/fifo_generator_v13_2_1 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_14 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST) +else + cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_15 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_16 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_14 -L $(COMPLIB_DIR)/fifo_generator_v13_2_1 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_14 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST) +endif +else +ifeq ($(TEST),test_null) + cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_17 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_18 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_16 -L $(COMPLIB_DIR)/fifo_generator_v13_2_2 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_16 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST) +else + cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_17 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_18 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_16 -L $(COMPLIB_DIR)/fifo_generator_v13_2_2 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_16 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST) +endif +endif $(COMPLIB_DIR): cd $(SIM_ROOT)/.. && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl diff --git a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.vcs b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.vcs index ff0b346d..61f241f9 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.vcs +++ b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.vcs @@ -22,65 +22,16 @@ ## 2. make all VCS=1 -> Runs the test ################################################################## -LOG_EXISTS=$(shell [ -e $(SIM_DIR)/$(LOG_NAME) ] && echo 1 || echo 0 ) -PASS_EXISTS=$(shell grep 'TEST PASSED' $(SIM_DIR)/$(LOG_NAME) | wc -l) - compile: $(COMPLIB_DIR) mkdir -p $(SIM_DIR) - cd $(SIM_DIR) && ln -s -f $(VCS_COMPLIB_DIR)/synopsys_sim.setup -ifeq ($(MAKE_DEBUG), 1) - cd $(SIM_DIR) && echo "vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFAULT_DEFINES) $(DEFINES) +lint=TFIPC-L" > compile.vlogan.log - cd $(SIM_DIR) && echo "vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS \"-I$(C_INC_DIR)\" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log" > compile.vcs.log -else - cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFAULT_DEFINES) $(DEFINES) +lint=TFIPC-L - cd $(SIM_DIR) && vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS "-I$(C_INC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log -endif + cd $(SIM_DIR) && ln -s -f ../vcs_complib/synopsys_sim.setup + cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFINES) +lint=TFIPC-L + cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log run: -ifeq ($(MAKE_DEBUG), 1) - cd $(SIM_DIR) && echo "./simv -l $(LOG_NAME) $(PLUSARGS) $(REGRESS_PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd" > $(LOG_NAME) -else - cd $(SIM_DIR) && ./simv -l $(LOG_NAME) $(PLUSARGS) $(REGRESS_PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd -endif - -check: -ifeq ($(REGRESS), 1) - @if [ $(LOG_EXISTS) -eq "1" ]; then \ - if [ $(PASS_EXISTS) -eq "1" ]; then \ - echo "$(LOG_NAME) -- PASSED" >> $(RESULTS_FILE); \ - else \ - echo "$(LOG_NAME) -- FAILED -- Did not find 'TEST PASSED' message in log file" >> $(RESULTS_FILE); \ - fi \ - else \ - echo "$(LOG_NAME) -- FAILED -- Did not find $(LOG_NAME) file" >> $(RESULTS_FILE); \ - fi -endif + cd $(SIM_DIR) && ./simv -l -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd -run_check: run check - $(COMPLIB_DIR): - cd $(SIM_ROOT)/.. && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl - cd $(SIM_ROOT)/.. && vivado -mode batch -source create_libs.tcl - cd $(SIM_ROOT)/.. && rm -rf create_libs.tcl - -regress_clean: -ifeq ($(REGRESS), 1) - @rm -rf $(SIM_ROOT) - @rm -rf $(RESULTS_FILE) - @touch $(RESULTS_FILE) -endif - -regress_sort: - @sort -o $(RESULTS_FILE) $(RESULTS_FILE) - -regress_post_clean: - @rm -rf $(SIM_DIR)/*/AN.DB - @rm -rf $(SIM_DIR)/*/csrc - @rm -rf $(SIM_DIR)/*/simv - @rm -rf $(SIM_DIR)/*/simv.daidir - @rm -rf $(SIM_DIR)/*/synopsys_sim.setup - @rm -rf $(SIM_DIR)/*/tr_db.log - @rm -rf $(SIM_DIR)/*/ucli.key - @rm -rf $(SIM_DIR)/*/vc_hdrs.h - @rm -rf $(SIM_DIR)/*/.vlogansetup.args - @rm -rf $(SIM_DIR)/*/.vpd + cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl + cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl + cd $(SIM_ROOT) && rm -rf create_libs.tcl diff --git a/hdk/cl/examples/cl_sde/verif/scripts/top.questa.f b/hdk/cl/examples/cl_sde/verif/scripts/top.questa.f index a3817c39..f83d5176 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/top.questa.f +++ b/hdk/cl/examples/cl_sde/verif/scripts/top.questa.f @@ -14,6 +14,11 @@ # limitations under the License. +define+QUESTA_SIM ++define+CARD_1=card ++define+CL_NAME=cl_sde ++define+SIMULATION ++define+NO_SDE_DEBUG_ILA ++define+DISABLE_VJTAG_DEBUG +libext+.v +libext+.sv @@ -23,11 +28,12 @@ -y ${CL_ROOT}/design -y ${SH_LIB_DIR} -y ${SH_INF_DIR} --y ${SH_SH_DIR} +-y ${HDK_SHELL_DESIGN_DIR}/sh_ddr/sim -y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl -y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim +incdir+${CL_ROOT}/../common/design ++incdir+${CL_ROOT}/design +incdir+${CL_ROOT}/verif/sv +incdir+${SH_LIB_DIR} +incdir+${SH_INF_DIR} @@ -35,12 +41,14 @@ +incdir+${HDK_COMMON_DIR}/verif/include +incdir+${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog +incdir+${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl ++incdir+${HDK_SHELL_DESIGN_DIR}/sh_ddr/sim ++incdir+${HDK_SHELL_DESIGN_DIR}/interfaces ${CL_ROOT}/../common/design/cl_common_defines.vh -${CL_ROOT}/design/cl_hello_world_defines.vh +${CL_ROOT}/design/cl_sde_defines.vh ${HDK_SHELL_DESIGN_DIR}/ip/ila_vio_counter/sim/ila_vio_counter.v ${HDK_SHELL_DESIGN_DIR}/ip/ila_0/sim/ila_0.v -${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl/bd_a493.v +${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/sim/bd_a493.v ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/sim/bd_a493_xsdbm_0.v ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/xsdbm_v3_0_vl_rfs.v ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/ltlib_v1_0_vl_rfs.v @@ -50,12 +58,56 @@ ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim/cl_debug_bridge.v ${HDK_SHELL_DESIGN_DIR}/ip/vio_0/sim/vio_0.v ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/sim/axi_register_slice_light.v +${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v -${CL_ROOT}/design/cl_hello_world.sv -${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v +${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_rfs.v +${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v ${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0.v +${CL_ROOT}/ip/ila_axi4/sim/ila_axi4.v +${CL_ROOT}/ip/ila_axi4_512/sim/ila_axi4_512.v +${CL_ROOT}/ip/ila_axis/sim/ila_axis.v +${CL_ROOT}/ip/ila_sde_c2h_buf/sim/ila_sde_c2h_buf.v +${CL_ROOT}/ip/ila_sde_c2h_dm/sim/ila_sde_c2h_dm.v +${CL_ROOT}/ip/ila_sde_h2c_buf/sim/ila_sde_h2c_buf.v +${CL_ROOT}/ip/ila_sde_h2c_dm/sim/ila_sde_h2c_dm.v +${CL_ROOT}/ip/ila_sde_ps/sim/ila_sde_ps.v +${CL_ROOT}/ip/ila_sde_wb/sim/ila_sde_wb.v +${CL_ROOT}/lib/axis_flop_fifo.sv +${CL_ROOT}/lib/bram_1w1r.sv +${CL_ROOT}/lib/flop_fifo_in.sv +${CL_ROOT}/lib/ft_fifo_p.v +${CL_ROOT}/lib/ft_fifo.v +${CL_ROOT}/lib/ram_fifo_ft.sv +${CL_ROOT}/lib/rr_arb.sv +${CL_ROOT}/design/cl_id_defines.vh +${CL_ROOT}/design/sde_pkg.sv +${CL_ROOT}/design/cl_pkt_tst.sv +${CL_ROOT}/design/ila_axi4_wrapper.sv +${CL_ROOT}/design/axi_prot_chk.sv +${CL_ROOT}/design/cl_tst.sv +${CL_ROOT}/design/cl_sde_srm.sv +${CL_ROOT}/design/sde_c2h_axis.sv +${CL_ROOT}/design/sde_c2h_buf.sv +${CL_ROOT}/design/sde_c2h_cfg.sv +${CL_ROOT}/design/sde_c2h_data.sv +${CL_ROOT}/design/sde_c2h.sv +${CL_ROOT}/design/sde_h2c_axis.sv +${CL_ROOT}/design/sde_h2c_buf.sv +${CL_ROOT}/design/sde_h2c_cfg.sv +${CL_ROOT}/design/sde_h2c_data.sv +${CL_ROOT}/design/sde_h2c.sv +${CL_ROOT}/design/sde_pm.sv +${CL_ROOT}/design/sde_ps_acc.sv +${CL_ROOT}/design/sde_ps.sv +${CL_ROOT}/design/sde_wb.sv +${CL_ROOT}/design/sde_desc.sv +${CL_ROOT}/design/sde.sv +${HDK_COMMON_DIR}/verif/models/base/gen_buf_t.sv +${HDK_COMMON_DIR}/verif/models/stream_bfm/stream_bfm.sv +${CL_ROOT}/design/cl_sde.sv -f ${HDK_COMMON_DIR}/verif/tb/filelists/tb.${SIMULATOR}.f - +${HDK_COMMON_DIR}/verif/tb/sv/dma_classes.sv +${HDK_COMMON_DIR}/verif/tb/sv/perf_mon.sv ${TEST_NAME} diff --git a/hdk/cl/examples/cl_sde/verif/scripts/top.vcs.f b/hdk/cl/examples/cl_sde/verif/scripts/top.vcs.f index 065b2833..9782d48f 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/top.vcs.f +++ b/hdk/cl/examples/cl_sde/verif/scripts/top.vcs.f @@ -18,10 +18,13 @@ +define+CL_NAME=cl_sde +define+SIMULATION +define+NO_SDE_DEBUG_ILA ++define+DISABLE_VJTAG_DEBUG + +libext+.v +libext+.sv +libext+.svh +-y ${CL_ROOT}/../common/design -y ${CL_ROOT}/design -y ${SH_LIB_DIR} -y ${SH_INF_DIR} @@ -31,74 +34,80 @@ +incdir+${CL_ROOT}/../common/design +incdir+${CL_ROOT}/design -+incdir+${CL_ROOT}/verif/sv ++incdir+${CL_ROOT}/verif/tests +incdir+${SH_LIB_DIR} +incdir+${SH_INF_DIR} ++incdir+${SH_SH_DIR} +incdir+${HDK_COMMON_DIR}/verif/include +incdir+${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog +incdir+${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl +incdir+${HDK_SHELL_DESIGN_DIR}/sh_ddr/sim +incdir+${HDK_SHELL_DESIGN_DIR}/interfaces -${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim/cl_debug_bridge.v -${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl/bd_a493.v +${CL_ROOT}/../common/design/cl_common_defines.vh +${CL_ROOT}/design/cl_sde_defines.vh +${HDK_SHELL_DESIGN_DIR}/ip/ila_vio_counter/sim/ila_vio_counter.v +${HDK_SHELL_DESIGN_DIR}/ip/ila_0/sim/ila_0.v +${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/sim/bd_a493.v ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/sim/bd_a493_xsdbm_0.v ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/xsdbm_v3_0_vl_rfs.v ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/ltlib_v1_0_vl_rfs.v ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/sim/bd_a493_lut_buffer_0.v ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/hdl/lut_buffer_v2_0_vl_rfs.v ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl/bd_a493_wrapper.v +${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim/cl_debug_bridge.v ${HDK_SHELL_DESIGN_DIR}/ip/vio_0/sim/vio_0.v ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/sim/axi_register_slice_light.v +${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v -${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v +${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_rfs.v +${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v ${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0.v - -+define+DISABLE_VJTAG_DEBUG +${CL_ROOT}/ip/ila_axi4/sim/ila_axi4.v +${CL_ROOT}/ip/ila_axi4_512/sim/ila_axi4_512.v +${CL_ROOT}/ip/ila_axis/sim/ila_axis.v +${CL_ROOT}/ip/ila_sde_c2h_buf/sim/ila_sde_c2h_buf.v +${CL_ROOT}/ip/ila_sde_c2h_dm/sim/ila_sde_c2h_dm.v +${CL_ROOT}/ip/ila_sde_h2c_buf/sim/ila_sde_h2c_buf.v +${CL_ROOT}/ip/ila_sde_h2c_dm/sim/ila_sde_h2c_dm.v +${CL_ROOT}/ip/ila_sde_ps/sim/ila_sde_ps.v +${CL_ROOT}/ip/ila_sde_wb/sim/ila_sde_wb.v +${CL_ROOT}/lib/axis_flop_fifo.sv +${CL_ROOT}/lib/bram_1w1r.sv +${CL_ROOT}/lib/flop_fifo_in.sv +${CL_ROOT}/lib/ft_fifo_p.v +${CL_ROOT}/lib/ft_fifo.v +${CL_ROOT}/lib/ram_fifo_ft.sv +${CL_ROOT}/lib/rr_arb.sv +${CL_ROOT}/design/cl_id_defines.vh ${CL_ROOT}/design/sde_pkg.sv -${CL_ROOT}/design/sde.sv -${CL_ROOT}/design/sde_c2h.sv +${CL_ROOT}/design/cl_pkt_tst.sv +${CL_ROOT}/design/ila_axi4_wrapper.sv +${CL_ROOT}/design/axi_prot_chk.sv +${CL_ROOT}/design/cl_tst.sv +${CL_ROOT}/design/cl_sde_srm.sv ${CL_ROOT}/design/sde_c2h_axis.sv ${CL_ROOT}/design/sde_c2h_buf.sv ${CL_ROOT}/design/sde_c2h_cfg.sv ${CL_ROOT}/design/sde_c2h_data.sv -${CL_ROOT}/design/sde_h2c.sv +${CL_ROOT}/design/sde_c2h.sv ${CL_ROOT}/design/sde_h2c_axis.sv ${CL_ROOT}/design/sde_h2c_buf.sv +${CL_ROOT}/design/sde_h2c_cfg.sv ${CL_ROOT}/design/sde_h2c_data.sv -${CL_ROOT}/design/sde_wb.sv -${CL_ROOT}/design/sde_desc.sv +${CL_ROOT}/design/sde_h2c.sv ${CL_ROOT}/design/sde_pm.sv +${CL_ROOT}/design/sde_ps_acc.sv ${CL_ROOT}/design/sde_ps.sv +${CL_ROOT}/design/sde_wb.sv +${CL_ROOT}/design/sde_desc.sv +${CL_ROOT}/design/sde.sv +${HDK_COMMON_DIR}/verif/models/base/gen_buf_t.sv +${HDK_COMMON_DIR}/verif/models/stream_bfm/stream_bfm.sv ${CL_ROOT}/design/cl_sde.sv -${CL_ROOT}/../../cl_pkt_tst.sv -${CL_ROOT}/../../cl_tst.sv - -# Chimera design lib (Not GitHub design lib) -# ${CL_ROOT}/../../../lib/rr_arb.sv - --y ${CL_ROOT}/../../../lib/ -+incdir+${CL_ROOT}/../../../lib/ - --y ${CL_ROOT}/../../../sh/ -#${CL_ROOT}/../../../v4_venom_cl/v4_venom_cl.srcs/sources_1/ip/ila_axi4/sim/ila_axi4.v -#${CL_ROOT}/../../../v4_venom_cl/v4_venom_cl.srcs/sources_1/ip/ila_axis/sim/ila_axis.v -#${CL_ROOT}/../../../v4_venom_cl/v4_venom_cl.srcs/sources_1/ip/ila_sde_ps/sim/ila_sde_ps.v -#${CL_ROOT}/../../../v4_venom_cl/v4_venom_cl.srcs/sources_1/ip/ila_sde_c2h_dm/sim/ila_sde_c2h_dm.v -#${CL_ROOT}/../../../v4_venom_cl/v4_venom_cl.srcs/sources_1/ip/ila_sde_c2h_buf/sim/ila_sde_c2h_buf.v -#${CL_ROOT}/../../../v4_venom_cl/v4_venom_cl.srcs/sources_1/ip/ila_sde_h2c_dm/sim/ila_sde_h2c_dm.v -#${CL_ROOT}/../../../v4_venom_cl/v4_venom_cl.srcs/sources_1/ip/ila_sde_h2c_buf/sim/ila_sde_h2c_buf.v -#${CL_ROOT}/../../../v4_venom_cl/v4_venom_cl.srcs/sources_1/ip/ila_sde_wb/sim/ila_sde_wb.v -f ${HDK_COMMON_DIR}/verif/tb/filelists/tb.${SIMULATOR}.f - -#TB Stuff -${CL_ROOT}/../../../../../verif/models/base/gen_buf_t.sv -${CL_ROOT}/../../../../../verif/models/stream_bfm/stream_bfm.sv -${CL_ROOT}/verif/sv/dma_classes.sv -${CL_ROOT}/verif/sv/perf_mon.sv -+incdir+${CL_ROOT}/verif/tests/ - +${HDK_COMMON_DIR}/verif/tb/sv/dma_classes.sv +${HDK_COMMON_DIR}/verif/tb/sv/perf_mon.sv ${TEST_NAME} - diff --git a/hdk/cl/examples/cl_sde/verif/scripts/top.vivado.f b/hdk/cl/examples/cl_sde/verif/scripts/top.vivado.f index c15b6e43..d1fa79da 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/top.vivado.f +++ b/hdk/cl/examples/cl_sde/verif/scripts/top.vivado.f @@ -63,6 +63,8 @@ ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v +${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_rfs.v +${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v ${SH_LIB_DIR}/../ip/axi_clock_converter_0/sim/axi_clock_converter_0.v ${CL_ROOT}/ip/ila_axi4/sim/ila_axi4.v ${CL_ROOT}/ip/ila_axi4_512/sim/ila_axi4_512.v diff --git a/hdk/docs/AWS_Shell_ERRATA.md b/hdk/docs/AWS_Shell_ERRATA.md index d646e072..40a21318 100644 --- a/hdk/docs/AWS_Shell_ERRATA.md +++ b/hdk/docs/AWS_Shell_ERRATA.md @@ -17,10 +17,8 @@ * AFI must be re-loaded after an instance re-boot. ## Unsupported Features (Planned for future releases) -* FPGA to FPGA communication over PCIe for F1.16xl -* FPGA to FPGA over serial ring links for F1.16xl +* FPGA to FPGA over serial ring links for F1.16xl and F1.4xl * Aurora and Reliable Aurora modules for the FPGA-to-FPGA -* Preserving the DRAM content between different AFI loads (by the same running instance) * Cadence Xcelium simulations tools ## Known Bugs/Issues diff --git a/hdk/docs/IPI_GUI_Examples.md b/hdk/docs/IPI_GUI_Examples.md index 688b9979..8c56ff98 100644 --- a/hdk/docs/IPI_GUI_Examples.md +++ b/hdk/docs/IPI_GUI_Examples.md @@ -762,7 +762,7 @@ This will run both synthesis and implementation. ## CL Example Software -The runtime software must be complied for the AFI to run on F1. Note the EDMA driver must be installed before running on F1. +The runtime software must be complied for the AFI to run on F1. Note the [XDMA driver must be installed](../../sdk/linux_kernel_drivers/xdma/xdma_install.md) before running on F1. Use the software in cl/examples/cl\_dram\_dma diff --git a/hdk/docs/RTL_Simulating_CL_Designs.md b/hdk/docs/RTL_Simulating_CL_Designs.md index 103122fd..1ed026b1 100644 --- a/hdk/docs/RTL_Simulating_CL_Designs.md +++ b/hdk/docs/RTL_Simulating_CL_Designs.md @@ -2,7 +2,16 @@ # Introduction -Developers tend to simulate their designs to validate the RTL design and functionality, before hitting the build stage and registering it with AWS EC2 as Amazon FPGA Image (AFI). AWS FPGA HDK comes with a shell simulation model that supports RTL-level simulation using Xilinx' Vivado XSIM, MentorGraphics' Questa, Cadence and Synopsys' VCS RTL simulators (See [ERRATA](../../ERRATA.md) for currently unsupported simulator versions). Developers can write their tests in SystemVerilog and/or C languages. If a developer chooses to use the supplied C framework, he/she can use the same C code for simulation and for runtime on your FPGA-enabled instance like F1. +Developers tend to simulate their designs to validate the RTL design and functionality, before hitting the build stage and registering it with AWS EC2 as Amazon FPGA Image (AFI). AWS FPGA HDK comes with a shell simulation model that supports RTL-level simulation using Xilinx' Vivado XSIM, MentorGraphics' Questa, Cadence Incisive and Synopsys' VCS RTL simulators. See table below for supported simulator versions. + +| 3rd party simulator Tool | 2017.4 Vivado tool | 2018.2 Vivado tool | +|--------------------------|--------------------|--------------------| +| Xilinx Vivado XSIM | Vivado v2017.4.op (64-bit) | Vivado v2018.2_AR71275_op (64-bit) | +| Synopsys VCS | vcs-mx/L-2016.06-1 | vcs-mx/N-2017.12-SP1-1 | +| Mentor Graphics Questa | 10.6b | 10.6c_1 | +| Cadence Incisive Enterprise Simulator(IES) | 15.20.063 | 15.20.063 | + +Developers can write their tests in SystemVerilog and/or C languages. If a developer chooses to use the supplied C framework, he/she can use the same C code for simulation and for runtime on your FPGA-enabled instance like F1. Testbench Top-Level Diagram diff --git a/hdk/docs/SDxPatch_AR71715_and_XRT_installation_instructions.md b/hdk/docs/SDxPatch_AR71715_and_XRT_installation_instructions.md new file mode 100644 index 00000000..acc53a99 --- /dev/null +++ b/hdk/docs/SDxPatch_AR71715_and_XRT_installation_instructions.md @@ -0,0 +1,68 @@ +# Installing SDX 2018.2 tool patch AR71715 + +## AWS FPGA Developer AMI + + On an instance using FPGA Developer AMI + + * Checkout latest AWS FPGA Developer Kit. + * Source [hdk_setup.sh](../../hdk_setup.sh) or [sdaccel_setup.sh](../../sdaccel_setup.sh) + * This will automatically download and install the patch. + * You can verify the patch is installed by running the below command and checking the contents. + + ``` + ls -lrt $XILINX_SDX/patches/AR71715 + + ``` + +## On premise machine + + * **You will need root permissions to be able to install the patch.** + * Checkout latest AWS FPGA Developer Kit version. + * Source [hdk_setup.sh](../../hdk_setup.sh) or [sdaccel_setup.sh](../../sdaccel_setup.sh) + * This will automatically download and install the patch. + * You can verify the patch is installed by running the below command and checking the contents. + + ``` + ls -lrt $XILINX_SDX/patches/AR71715 + + ``` + + ## Manual install + + ### Pre-requisites + + * **You will need root permissions to be able to install the patch.** + * Set environment variable `XILINX_SDX` to your SDx installation directory. + + ### Download and Install + + * Run following commands to download and install the patch + + ``` + curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Patches/AR71715.zip -o AR71715.zip + sudo mkdir -p $XILINX_SDX/patches + sudo unzip AR71715.zip -d $XILINX_SDX/patches/AR71715 + sudo cp $XILINX_SDX/scripts/ocl/ocl_util.tcl $tool_dir/scripts/ocl/ocl_util.tcl.bkp + sudo cp -f $XILINX_SDX/patches/AR71715/sdx/scripts/ocl/ocl_util.tcl $XILINX_SDX/scripts/ocl/ocl_util.tcl + chmod -R 755 $XILINX_SDX/patches/AR71715 + + ``` + + +# Installing Xilinx Runtime (XRT) 2018.2_XDF.RC4 + + Instructions to install XRT on Centos/RedHat & Ubuntu/Debian can be found [here](https://www.xilinx.com/html_docs/xilinx2018_2_xdf/sdaccel_doc/ejy1538090924727.html). + + Xilinx Runtime (XRT) 2018.2_XDF.RC4 release can be found [here](https://github.com/Xilinx/XRT/tree/2018.2_XDF.RC4) + + ### Centos/RedHat Linux + + Run following commands to download and install XRT 2018.2_XDF.RC4 for 'Centos/RHEL' based distributions + + ``` + curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Patches/xrt_201802.2.1.0_7.5.1804-xrt.rpm -o xrt_201802.2.1.0_7.5.1804-xrt.rpm + curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Patches/xrt_201802.2.1.0_7.5.1804-aws.rpm -o xrt_201802.2.1.0_7.5.1804-aws.rpm + sudo yum reinstall -y xrt_201802.2.1.0_7.5.1804-xrt.rpm + sudo yum reinstall -y xrt_201802.2.1.0_7.5.1804-aws.rpm + + ``` diff --git a/hdk/docs/afi_power.md b/hdk/docs/afi_power.md index 5c5537b8..3d4766c4 100644 --- a/hdk/docs/afi_power.md +++ b/hdk/docs/afi_power.md @@ -1,7 +1,16 @@ # AFI Power +There are 2 power related scenarios that need to be avoided: +1. Exceeding the Maximum FPGA power +1. Ramping too quickly between low power and high power states + +## Exceeding Maximum FPGA power The Xilinx UltraScale+ FPGA devices used on the F1 instances have a maximum power limit that must be maintained. If a loaded AFI consumes maximum power, the F1 instance will automatically gate the input clocks provided to the AFI in order to prevent errors within the FPGA. This is called an afi-power-violation. Specifically, when power (Vccint) is greater than 85 watts, the CL will have a power warning bit set. Above that level, the CL is in danger of being clock gated due to an afi-power-violation. -## Preventing power violations +## Ramping too Quickly Between Low Power and High Power States +Even though your design may have a max power which is lower than the previously described limit, you might see issues if you rapidly switch between low power and high power states. A common scenario is upon startup the design goes from a low power reset state to the max power state instantly. In failing cases the host will appear to lose contact with the FPGA card and can only recover with an instance stop/restart. To prevent this from happening care must be taken to sequence the design such that it slowly increases the power requirements to max power instead of instantaneously doing so. + +# Measuring FPGA Power - Live or Offline via Vivado +## Live Measurement of FPGA Power In order to help developers understand how much power their AFIs actually use in the field, AWS now presents power metrics in the fpga-describe-local-image tool. These metrics are updated every minute, and will reflect the most recently measured FPGA power, the average power over the run of the AFI, and the maximum power consumption detected in the run of the AFI. The current and average power consumption will be available on the first power update after the AFI is loaded, while the max power measurements will start after this first update (max power will not include the time immediately after the FPGA is loaded). For example, @@ -17,6 +26,7 @@ Power consumption (Vccint): Power consumption may drift slightly over time, and may vary from instance to instance. In order to prevent a power violation, it's important to take into account this natural variation, and design with margin accordingly. +## Lowering Power Based on High Power Events Reported by the Shell In order to help developers avoid these overpower events, the F1 system indicates a afi-power-warning on the CL interface (sh_cl_pwr_state[1:0]) when the FPGA power levels are above 85 watts, and the CL is in danger of having it's clocks disabled. This should allow the CL to self-throttle, or reduce power-hungry optimizations, and avoid having its input clocks disabled. Power state of the FPGA: sh_cl_pwr_state[1:0] @@ -30,7 +40,7 @@ The fpga-describe-local-image command will show that the AFI load has failed due ``` # fpga-describe-local-image -S 0 - AFI 0 none load-failed 7 afi-power-violation 17 0x04261818 + AFI 0 none load-failed 7 afi-power-violation 17 0x071417d3 AFIDEVICE 0 0x1d0f 0xf000 0000:00:1d.0 ``` @@ -62,4 +72,24 @@ Using a lower clock frequency from the [supported clock recipe](./clock_recipes. ## Recovering from clock gating When an afi-power-violation occurs, the FPGA can still be loaded and cleared, but the clocks cannot be re-enabled without reloading the FPGA. Any AFI load or clear will restore full functionality to the FPGA. +# Power Savings Techniques +Here are some low power design techniques that can be used to lower the overall power or minimize instantaneous power ramps. + +Power is consumed whenever a node in the design switches high or low. Reducing the switching activity will reduce the power requirements. + +**Clock Nets:** The largest component of switching activity are the clock nets in the design. Power is consumed on both transition edges of the clock. Some common techniques to reduce clock power are: +1. Clocking design at lower frequencies will lower clock power linearly. This isn’t always possible. +1. If the entire design doesn’t need to be clocked at full frequency, create lower frequency clocks for the slower logic. +1. If parts of the logic don’t need to always be clocked, you can gate the clocks to them (AND the clock with an enable signal). The gated clock net will draw no power when it’s gated off. + +**Outputs of Sequential Elements:** Outputs of FF’s and RAMs cause downstream logic to consume power every time they switch. There are many times when these sequential elements don’t need to switch every cycle. Some common techniques to reduce sequential element power are: +1. Add enables to as many FF’s as possible. This will cause the FF’s output to switch less often, lowering power on all downstream nodes. +1. Add chip-selects or read-enables to your RAMs. Same concept as #1. +1. Shift-register structures (LFSR’s, CRC, random number generators, etc.) burn power because their outputs switch. Add enables to these FF’s to switch them only when needed. + +**Architectural Power Savings**: A global power savings technique is to control power at the top-level Architectural Level. There is typically a block diagram of the overall design. By gating the clocks to top-level blocks and/or creating enables for the sequential elements in the design, these blocks can be put into low power modes when they aren't being used. It's critical to only enable the blocks that are required for the job. + +**Reducing Instantaneous Swings in Power**: Care must be taken to ensure there aren't large swings between low power and high power states. Sequencing the enables to the top-level architectural blocks will allow the design to slowly ramp to max power levels. + + diff --git a/hdk/hdk_version.txt b/hdk/hdk_version.txt index ef1122a9..c9931a08 100644 --- a/hdk/hdk_version.txt +++ b/hdk/hdk_version.txt @@ -1 +1 @@ -HDK_VERSION=1.4.5 +HDK_VERSION=1.4.6 diff --git a/hdk/tests/simulation_tests/run_sim.sh b/hdk/tests/simulation_tests/run_sim.sh index d7f11092..9c34a7cc 100755 --- a/hdk/tests/simulation_tests/run_sim.sh +++ b/hdk/tests/simulation_tests/run_sim.sh @@ -17,8 +17,8 @@ # Exit on any error set -e - # Process command line args + while [[ $# -gt 1 ]] do key="$1" @@ -34,6 +34,11 @@ case $key in shift shift ;; + --simulator) + simulator="$2" + shift + shift + ;; --test-type) test_type="$2" shift @@ -48,46 +53,171 @@ done # Run the test pushd $test_dir - -case "$test_type" in - sv) - make TEST="$test_name" - ;; - sv_fast) - make TEST="$test_name" AXI_MEMORY_MODEL=1 - ;; - sv_fast_ecc_direct) - make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_DIRECT=1 ECC_ADDR_HI=1000 ECC_ADDR_LO=0 - ;; - sv_fast_ecc_rnd) - make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=100 - ;; - sv_fast_ecc_rnd_100) - make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=100 - ;; - sv_fast_ecc_rnd_50) - make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=50 - ;; - sv_fast_ecc_rnd_10) - make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=10 - ;; - sv_fast_ecc_rnd_0) - make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=0 - ;; - sv_ddr_bkdr) - make TEST="$test_name" DDR_BKDR=1 - ;; - vhdl) - make TEST="$test_name" - ;; - c) - make C_TEST="$test_name" - ;; - *) - echo -e >&2 "ERROR: Invalid option: $1\n" - exit 1 - ;; +case "$simulator" in + vcs) + case "$test_type" in + sv) + make TEST="$test_name" VCS=1 + ;; + sv_fast) + make TEST="$test_name" AXI_MEMORY_MODEL=1 VCS=1 + ;; + sv_fast_ecc_direct) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_DIRECT=1 ECC_ADDR_HI=1000 ECC_ADDR_LO=0 VCS=1 + ;; + sv_fast_ecc_rnd) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=100 VCS=1 + ;; + sv_fast_ecc_rnd_100) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=100 VCS=1 + ;; + sv_fast_ecc_rnd_50) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=50 VCS=1 + ;; + sv_fast_ecc_rnd_10) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=10 VCS=1 + ;; + sv_fast_ecc_rnd_0) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=0 VCS=1 + ;; + sv_ddr_bkdr) + make TEST="$test_name" DDR_BKDR=1 VCS=1 + ;; + vhdl) + make TEST="$test_name" VCS=1 + ;; + c) + make C_TEST="$test_name" VCS=1 + ;; + *) + echo -e >&2 "ERROR: Invalid option: $1\n" + exit 1 + ;; + esac + ;; + ies) + case "$test_type" in + sv) + make TEST="$test_name" IES=1 + ;; + sv_fast) + make TEST="$test_name" AXI_MEMORY_MODEL=1 IES=1 + ;; + sv_fast_ecc_direct) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_DIRECT=1 ECC_ADDR_HI=1000 ECC_ADDR_LO=0 IES=1 + ;; + sv_fast_ecc_rnd) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=100 IES=1 + ;; + sv_fast_ecc_rnd_100) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=100 IES=1 + ;; + sv_fast_ecc_rnd_50) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=50 IES=1 + ;; + sv_fast_ecc_rnd_10) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=10 IES=1 + ;; + sv_fast_ecc_rnd_0) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=0 IES=1 + ;; + sv_ddr_bkdr) + make TEST="$test_name" DDR_BKDR=1 IES=1 + ;; + vhdl) + make TEST="$test_name" IES=1 + ;; + c) + make C_TEST="$test_name" IES=1 + ;; + *) + echo -e >&2 "ERROR: Invalid option: $1\n" + exit 1 + ;; + esac + ;; + questa) + case "$test_type" in + sv) + make TEST="$test_name" QUESTA=1 + ;; + sv_fast) + make TEST="$test_name" AXI_MEMORY_MODEL=1 QUESTA=1 + ;; + sv_fast_ecc_direct) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_DIRECT=1 ECC_ADDR_HI=1000 ECC_ADDR_LO=0 QUESTA=1 + ;; + sv_fast_ecc_rnd) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=100 QUESTA=1 + ;; + sv_fast_ecc_rnd_100) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=100 QUESTA=1 + ;; + sv_fast_ecc_rnd_50) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=50 QUESTA=1 + ;; + sv_fast_ecc_rnd_10) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=10 QUESTA=1 + ;; + sv_fast_ecc_rnd_0) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=0 QUESTA=1 + ;; + sv_ddr_bkdr) + make TEST="$test_name" DDR_BKDR=1 QUESTA=1 + ;; + vhdl) + make TEST="$test_name" QUESTA=1 + ;; + c) + make C_TEST="$test_name" QUESTA=1 + ;; + *) + echo -e >&2 "ERROR: Invalid option: $1\n" + exit 1 + ;; + esac + ;; + *) + case "$test_type" in + sv) + make TEST="$test_name" + ;; + sv_fast) + make TEST="$test_name" AXI_MEMORY_MODEL=1 + ;; + sv_fast_ecc_direct) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_DIRECT=1 ECC_ADDR_HI=1000 ECC_ADDR_LO=0 + ;; + sv_fast_ecc_rnd) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=100 + ;; + sv_fast_ecc_rnd_100) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=100 + ;; + sv_fast_ecc_rnd_50) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=50 + ;; + sv_fast_ecc_rnd_10) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=10 + ;; + sv_fast_ecc_rnd_0) + make TEST="$test_name" AXI_MEMORY_MODEL=1 ECC_RAND=1 RND_ECC_WEIGHT=0 + ;; + sv_ddr_bkdr) + make TEST="$test_name" DDR_BKDR=1 + ;; + vhdl) + make TEST="$test_name" + ;; + c) + make C_TEST="$test_name" + ;; + *) + echo -e >&2 "ERROR: Invalid option: $1\n" + exit 1 + ;; + esac + ;; esac - # Exit out of the test dir popd diff --git a/hdk/tests/simulation_tests/test_sims.py b/hdk/tests/simulation_tests/test_sims.py index f1014b07..4d88f9a0 100644 --- a/hdk/tests/simulation_tests/test_sims.py +++ b/hdk/tests/simulation_tests/test_sims.py @@ -41,6 +41,8 @@ class TestSims(AwsFpgaTestBase): NOTE: Cannot have an __init__ method. ''' + ADD_SIMULATOR = True + @classmethod def setup_class(cls): ''' @@ -54,553 +56,554 @@ def setup_class(cls): assert os.path.exists(cls.RUN_SIM_SCRIPT) return - def run_sim(self, test_dir="", test_name="", test_type=""): + def run_sim(self, test_dir="", test_name="", test_type="", Simulator="" ): # Error on defaults if not(test_dir and test_name and test_type): self.fail("Please enter non empty test_dir, test_name and test_type when calling run_sim") - command_line = [self.RUN_SIM_SCRIPT, '--test-name', test_name, '--test-dir', test_dir, '--test-type', test_type] + command_line = [self.RUN_SIM_SCRIPT, '--test-name', test_name, '--test-dir', test_dir, '--test-type', test_type, '--simulator', Simulator] (rc, stdout_lines, stderr_lines) = self.run_cmd(" ".join(command_line)) assert rc == 0, "Sim failed" # cl_dram_dma sv - def test_cl_dram_dma__dram_dma__sv(self): + def test_cl_dram_dma__dram_dma__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma__sv_fast(self): + def test_cl_dram_dma__dram_dma__sv_fast(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma' test_type = 'sv_fast' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma__sv_fast_ecc_direct(self): + def test_cl_dram_dma__dram_dma__sv_fast_ecc_direct(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_ecc_direct' test_type = 'sv_fast_ecc_direct' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_ecc_direct__sv_fast_ecc_direct(self): + def test_cl_dram_dma__dram_dma_ecc_direct__sv_fast_ecc_direct(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_ecc_direct' test_type = 'sv_fast_ecc_direct' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_ecc_direct__sv_fast_ecc_rnd(self): + def test_cl_dram_dma__dram_dma_ecc_direct__sv_fast_ecc_rnd(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_ecc_direct' test_type = 'sv_fast_ecc_rnd' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_ecc_rand__sv_fast_ecc_rnd_100(self): + def test_cl_dram_dma__dram_dma_ecc_rand__sv_fast_ecc_rnd_100(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_ecc_rand' test_type = 'sv_fast_ecc_rnd_100' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_ecc_rand__sv_fast_ecc_rnd_50(self): + def test_cl_dram_dma__dram_dma_ecc_rand__sv_fast_ecc_rnd_50(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_ecc_rand' test_type = 'sv_fast_ecc_rnd_50' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_ecc_rand__sv_fast_ecc_rnd_10(self): + def test_cl_dram_dma__dram_dma_ecc_rand__sv_fast_ecc_rnd_10(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_ecc_rand' test_type = 'sv_fast_ecc_rnd_10' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_ecc_rand__sv_fast_ecc_rnd_0(self): + def test_cl_dram_dma__dram_dma_ecc_rand__sv_fast_ecc_rnd_0(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_ecc_rand' test_type = 'sv_fast_ecc_rnd_0' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma__sv_fast_ecc_rnd(self): + def test_cl_dram_dma__dram_dma__sv_fast_ecc_rnd(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_ecc_direct' test_type = 'sv_fast_ecc_rnd' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_axi_mstr__sv(self): + def test_cl_dram_dma__dram_dma_axi_mstr__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_axi_mstr' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_rnd__sv(self): + def test_cl_dram_dma__dram_dma_rnd__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_rnd' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_rnd__sv_fast(self): + def test_cl_dram_dma__dram_dma_rnd__sv_fast(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_rnd' test_type = 'sv_fast' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_rnd__sv_fast_ecc_direct(self): + def test_cl_dram_dma__dram_dma_rnd__sv_fast_ecc_direct(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_rnd' test_type = 'sv_fast_ecc_direct' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_rnd__sv_fast_ecc_rnd(self): + def test_cl_dram_dma__dram_dma_rnd__sv_fast_ecc_rnd(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_rnd' test_type = 'sv_fast_ecc_rnd' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_4k_crossing__sv(self): + def test_cl_dram_dma__dram_dma_4k_crossing__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_4k_crossing' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_4k_crossing__sv_fast(self): + def test_cl_dram_dma__dram_dma_4k_crossing__sv_fast(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_4k_crossing' test_type = 'sv_fast' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_4k_crossing__sv_fast_ecc_direct(self): + def test_cl_dram_dma__dram_dma_4k_crossing__sv_fast_ecc_direct(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_4k_crossing' test_type = 'sv_fast_ecc_direct' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_4k_crossing__sv_fast_ecc_rnd(self): + def test_cl_dram_dma__dram_dma_4k_crossing__sv_fast_ecc_rnd(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_4k_crossing' test_type = 'sv_fast_ecc_rnd' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_single_beat_4k__sv(self): + def test_cl_dram_dma__dram_dma_single_beat_4k__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_single_beat_4k' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_single_beat_4k__sv_fast(self): + def test_cl_dram_dma__dram_dma_single_beat_4k__sv_fast(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_single_beat_4k' test_type = 'sv_fast' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_single_beat_4k__sv_fast_ecc_direct(self): + def test_cl_dram_dma__dram_dma_single_beat_4k__sv_fast_ecc_direct(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_single_beat_4k' test_type = 'sv_fast_ecc_direct' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_single_beat_4k__sv_fast_ecc_rnd(self): + def test_cl_dram_dma__dram_dma_single_beat_4k__sv_fast_ecc_rnd(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_single_beat_4k' test_type = 'sv_fast_ecc_rnd' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dma_pcis_concurrent__sv(self): + def test_cl_dram_dma__dma_pcis_concurrent__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dma_pcis_concurrent' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dma_pcis_concurrent__sv_fast(self): + def test_cl_dram_dma__dma_pcis_concurrent__sv_fast(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dma_pcis_concurrent' test_type = 'sv_fast' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dma_pcis_concurrent__sv_fast_ecc_direct(self): + def test_cl_dram_dma__dma_pcis_concurrent__sv_fast_ecc_direct(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dma_pcis_concurrent' test_type = 'sv_fast_ecc_direct' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) - def test_cl_dram_dma__dma_pcis_concurrent__sv_fast_ecc_rnd(self): + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) + + def test_cl_dram_dma__dma_pcis_concurrent__sv_fast_ecc_rnd(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dma_pcis_concurrent' test_type = 'sv_fast_ecc_rnd' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dma_pcim_concurrent__sv(self): + def test_cl_dram_dma__dma_pcim_concurrent__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dma_pcim_concurrent' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dma_pcim_concurrent__sv_fast(self): + def test_cl_dram_dma__dma_pcim_concurrent__sv_fast(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dma_pcim_concurrent' test_type = 'sv_fast' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) - def test_cl_dram_dma__dma_pcim_concurrent__sv_fast_ecc_direct(self): + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) + def test_cl_dram_dma__dma_pcim_concurrent__sv_fast_ecc_direct(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dma_pcim_concurrent' test_type = 'sv_fast_ecc_direct' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dma_pcim_concurrent__sv_fast_ecc_rnd(self): + def test_cl_dram_dma__dma_pcim_concurrent__sv_fast_ecc_rnd(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dma_pcim_concurrent' test_type = 'sv_fast_ecc_rnd' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dma_sda_concurrent__sv(self): + def test_cl_dram_dma__dma_sda_concurrent__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dma_sda_concurrent' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dma_sda_concurrent__sv_fast(self): + def test_cl_dram_dma__dma_sda_concurrent__sv_fast(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dma_sda_concurrent' test_type = 'sv_fast' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dma_sda_concurrent__sv_fast_ecc_direct(self): + def test_cl_dram_dma__dma_sda_concurrent__sv_fast_ecc_direct(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dma_sda_concurrent' test_type = 'sv_fast_ecc_direct' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) - def test_cl_dram_dma__dma_sda_concurrent__sv_fast_ecc_rnd(self): + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) + def test_cl_dram_dma__dma_sda_concurrent__sv_fast_ecc_rnd(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dma_sda_concurrent' test_type = 'sv_fast_ecc_rnd' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__ddr__sv(self): + def test_cl_dram_dma__ddr__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_ddr' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__clk_recipe__sv(self): + def test_cl_dram_dma__clk_recipe__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_clk_recipe' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__int__sv(self): + def test_cl_dram_dma__int__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_int' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke__sv(self): + def test_cl_dram_dma__peek_poke__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke__sv_fast(self): + def test_cl_dram_dma__peek_poke__sv_fast(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke' test_type = 'sv_fast' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke__sv_fast_ecc_direct(self): + def test_cl_dram_dma__peek_poke__sv_fast_ecc_direct(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke' test_type = 'sv_fast_ecc_direct' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke__sv_fast_ecc_rnd(self): + def test_cl_dram_dma__peek_poke__sv_fast_ecc_rnd(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke' test_type = 'sv_fast_ecc_rnd' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke_wc__sv(self): + def test_cl_dram_dma__peek_poke_wc__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke_wc' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke_wc__sv_fast(self): + def test_cl_dram_dma__peek_poke_wc__sv_fast(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke_wc' test_type = 'sv_fast' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke_wc__sv_fast_ecc_direct(self): + def test_cl_dram_dma__peek_poke_wc__sv_fast_ecc_direct(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke_wc' test_type = 'sv_fast_ecc_direct' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke_wc__sv_fast_ecc_rnd(self): + def test_cl_dram_dma__peek_poke_wc__sv_fast_ecc_rnd(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke_wc' test_type = 'sv_fast_ecc_rnd' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke_len__sv(self): + def test_cl_dram_dma__peek_poke_len__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke_len' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke_len__sv_fast(self): + def test_cl_dram_dma__peek_poke_len__sv_fast(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke_len' test_type = 'sv_fast' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke_len__sv_fast_ecc_direct(self): + def test_cl_dram_dma__peek_poke_len__sv_fast_ecc_direct(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke_len' test_type = 'sv_fast_ecc_direct' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke_len__sv_fast_ecc_rnd(self): + def test_cl_dram_dma__peek_poke_len__sv_fast_ecc_rnd(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke_len' test_type = 'sv_fast_ecc_rnd' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke_pcis_axsize__sv(self): + def test_cl_dram_dma__peek_poke_pcis_axsize__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke_pcis_axsize' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke_pcis_axsize__sv_fast(self): + def test_cl_dram_dma__peek_poke_pcis_axsize__sv_fast(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke_pcis_axsize' test_type = 'sv_fast' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke_pcis_axsize__sv_fast_ecc_direct(self): + def test_cl_dram_dma__peek_poke_pcis_axsize__sv_fast_ecc_direct(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke_pcis_axsize' test_type = 'sv_fast_ecc_direct' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__peek_poke_pcis_axsize__sv_fast_ecc_rnd(self): + def test_cl_dram_dma__peek_poke_pcis_axsize__sv_fast_ecc_rnd(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_peek_poke_pcis_axsize' test_type = 'sv_fast_ecc_rnd' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__ddr_peek_poke__sv(self): + def test_cl_dram_dma__ddr_peek_poke__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_ddr_peek_poke' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__ddr_peek_bdr_walking_ones__sv(self): + def test_cl_dram_dma__ddr_peek_bdr_walking_ones__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_ddr_peek_bdr_walking_ones' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_dram_bdr_row_col_combo__sv(self): + def test_cl_dram_dma__dram_dma_dram_bdr_row_col_combo__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_ddr_peek_bdr_walking_ones' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_mem_model_bdr_wr__sv(self): + def test_cl_dram_dma__dram_dma_mem_model_bdr_wr__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_mem_model_bdr_wr' test_type = 'sv_fast' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_mem_model_bdr_rd__sv(self): + def test_cl_dram_dma__dram_dma_mem_model_bdr_rd__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_mem_model_bdr_rd' test_type = 'sv_fast' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_ddr_peek_bdr_walking_ones__sv(self): + def test_ddr_peek_bdr_walking_ones__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_ddr_peek_bdr_walking_ones' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) # cl_uram_example c - def test_cl_uram_example__uram_example__c(self): + def test_cl_uram_example__uram_example__c(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_uram_example/verif/scripts' test_name = 'test_uram_example' test_type = 'c' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) # cl_dram_dma c - def test_cl_dram_dma__sda__sv(self): + def test_cl_dram_dma__sda__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_sda' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) - def test_cl_dram_dma__dram_dma_hwsw_cosim__c(self): + def test_cl_dram_dma__dram_dma_hwsw_cosim__c(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts' test_name = 'test_dram_dma_hwsw_cosim' test_type = 'c' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) # cl_hello_world sv - def test_cl_hello_world__hello_world__sv(self): + def test_cl_hello_world__hello_world__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_hello_world/verif/scripts' test_name = 'test_hello_world' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) # cl_test_gl_cntr sv - def test_cl_hello_world__gl_cntr__sv(self): + def test_cl_hello_world__gl_cntr__sv(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_hello_world/verif/scripts' test_name = 'test_gl_cntr' test_type = 'sv' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) # cl_hello_world vhdl - def test_cl_hello_world__hello_world__vhdl(self): + def test_cl_hello_world__hello_world__vhdl(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_hello_world_vhdl/verif/scripts' test_name = 'test_hello_world' test_type = 'vhdl' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) # cl_hello_world c - def test_cl_hello_world__hello_world__c(self): + def test_cl_hello_world__hello_world__c(self, Simulator): test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_hello_world/verif/scripts' test_name = 'test_hello_world' test_type = 'c' - self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type) + self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, Simulator=Simulator) diff --git a/hdk/tests/test_load_afi.py b/hdk/tests/test_load_afi.py index 269efac3..78df42e1 100644 --- a/hdk/tests/test_load_afi.py +++ b/hdk/tests/test_load_afi.py @@ -126,8 +126,6 @@ def byte_swap(self, value): def load_agfi(self, cl, agfi, afi, slot): self.assert_afi_available(afi) - self.load_msix_workaround(slot) - self.fpga_load_local_image(agfi, slot) logger.info("Checking slot {} AFI Load status".format(slot)) @@ -257,7 +255,7 @@ def check_runtime_software(self, cl, slot): self.WORKSPACE, cl), echo=True) assert rc == 0, "Runtime example failed." - else: + else: assert False, "Invalid cl: {}".format(cl) def base_test(self, cl, agfi, afi, install_xdma_driver, slots_to_test, option_tag): diff --git a/sdaccel_runtime_setup.sh b/sdaccel_runtime_setup.sh new file mode 100644 index 00000000..972a1925 --- /dev/null +++ b/sdaccel_runtime_setup.sh @@ -0,0 +1,207 @@ +# Amazon FPGA Hardware Development Kit +# +# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. + +# Script must be sourced from a bash shell or it will not work +# When being sourced $0 will be the interactive shell and $BASH_SOURCE_ will contain the script being sourced +# When being run $0 and $_ will be the same. +script=${BASH_SOURCE[0]} +if [ $script == $0 ]; then + echo "ERROR: You must source this script" + exit 2 +fi + +full_script=$(readlink -f $script) +script_name=$(basename $full_script) +script_dir=$(dirname $full_script) +current_dir=$(pwd) + +source $script_dir/shared/bin/set_common_functions.sh +source $script_dir/shared/bin/set_common_env_vars.sh + +# Source sdk_setup.sh +info_msg "Sourcing sdk_setup.sh" +if ! source $AWS_FPGA_REPO_DIR/sdk_setup.sh; then + return 1 +fi + +if [ -z "$SDK_DIR" ]; then + err_msg "SDK_DIR environment variable is not set. Please use 'source sdk_setup.sh' from the aws-fpga directory." + return 1 +fi + +debug=0 +override=0 +function usage { + echo -e "USAGE: source [\$AWS_FPGA_REPO_DIR/]$script_name [-d|-debug] [-h|-help] [-o|-override]" +} + +function help { + info_msg "$script_name" + info_msg " " + info_msg "Checks & Sets up the runtime environment for AWS FPGA SDAccel Application usage." + info_msg " " + info_msg "sdaccel_runtime_check.sh script will:" + info_msg " (1) install FPGA Management Tools," + info_msg " (2) check if Xilinx Runtime (XRT) is installed" + info_msg " (3) check if correct version of Xilinx Runtime (XRT) is installed," + info_msg " (4) check if the required XOCL driver is running " + info_msg " (5) source runtime setup script " + echo " " + usage +} + +function xrt_install_instructions_2018_2 { + err_msg "AWS recommended XRT version release: https://github.com/Xilinx/XRT/releases/tag/2018.2_XDF.RC4" + err_msg "refer to following link for instructions to install XRT" + err_msg "https://www.xilinx.com/html_docs/xilinx2018_2_xdf/sdaccel_doc/ejy1538090924727.html" + err_msg "use following command to download and install latest validated XRT rpms for centos distributions" + err_msg "curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Patches/xrt_201802.2.1.0_7.5.1804-xrt.rpm -o xrt_201802.2.1.0_7.5.1804-xrt.rpm" + err_msg "curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Patches/xrt_201802.2.1.0_7.5.1804-aws.rpm -o xrt_201802.2.1.0_7.5.1804-aws.rpm" + err_msg "sudo yum reinstall -y xrt_*-xrt.rpm" + err_msg "sudo yum reinstall -y xrt_*-aws.rpm" +} + +function check_xdma_driver { + + if lsmod | grep -q 'xdma' ; then + err_msg "Found XDMA Driver running. Please remove xdma driver using below command" + err_msg " rmmod xdma" + return 1 + fi +} + +function check_edma_driver { + + if lsmod | grep -q 'edma' ; then + err_msg "Found EDMA Driver running. Please remove edma driver using below command" + err_msg " rmmod edma" + return 1 + fi +} + +function check_xocl_driver { + if lsmod | grep -q 'xocl' ; then + info_msg "Found 'xocl Driver is installed and running. ' " + else + err_msg " XOCL Driver not installed. Please install xocl driver using below instructions" + err_msg " If using 2017.4 Vivado toolset please source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh " + err_msg " if using 2018.2 Vivado toolset please reinstall rpm using instructions below " + xrt_install_instructions_2018_2 + return 1 + fi +} + +# Process command line args +args=( "$@" ) +for (( i = 0; i < ${#args[@]}; i++ )); do + arg=${args[$i]} + case $arg in + -d|-debug) + debug=1 + ;; + -h|-help) + help + return 0 + ;; + -o|-override) + override=1 + ;; + *) + err_msg "Invalid option: $arg\n" + usage + return 1 + esac +done + + +if ! is_vivado_available; then + if [[ -z "${VIVADO_TOOL_VERSION}" ]]; then + err_msg " You are not using FPGA Developer AMI and VIVADO_TOOL_VERSION ENV variable is Empty. " + err_msg " ENV Variable VIVADO_TOOL_VERSION is required to be set for runtime " + err_msg " If AFI was generated using V2018.2 tools use the command : export VIVADO_TOOL_VERSION=2018.2 " + err_msg " If AFI was generated using V2017.4 tools use the command : export VIVADO_TOOL_VERSION=2017.4 " + err_msg " If you are using the FPGA Developer AMI then please request support on AWS FPGA Developers Forum." + return 1 + else + info_msg " VIVADO tools not found. Reading VIVADO_TOOL_VERSION ENV variable to determine runtime version... " + VIVADO_TOOL_VERSION="${VIVADO_TOOL_VERSION}" + export VIVADO_TOOL_VERSION=${VIVADO_TOOL_VERSION:0:6} + fi +else + info_msg "You are using instance with installed vivado tools. determining VIVADO version for runtime setup..." + VIVADO_TOOL_VERSION=`vivado -version | grep Vivado | head -1 | sed 's:Vivado *::' | sed 's: .*$::' | sed 's:v::'` + export VIVADO_TOOL_VERSION=${VIVADO_TOOL_VERSION:0:6} +fi +info_msg "VIVADO_TOOL_VERSION is $VIVADO_TOOL_VERSION" + + + +check_xdma_driver +check_edma_driver + +if [[ "$VIVADO_TOOL_VERSION" =~ .*2018\.2.* ]]; then + info_msg "Xilinx Vivado version is 2018.2" + + if override; then + info_msg "XRT check overide selected." + source /opt/xilinx/xrt/setup.sh + return 0 + fi + + if [ -f "/opt/xilinx/xrt/include/version.h" ]; then + info_msg "XRT installed. proceeding to check version compatibility" + xrt_build_ver=$(grep 'xrt_build_version_hash\[\]' /opt/xilinx/xrt/include/version.h | sed 's/";//' | sed 's/^.*"//') + info_msg "Installed XRT version : $xrt_build_ver" + if grep -Fxq "$xrt_build_ver" $AWS_FPGA_REPO_DIR/SDAccel/sdaccel_xrt_version.txt + then + info_msg "XRT version $xrt_build_ver is supported." + info_msg " Now checking XOCL driver..." + check_xocl_driver + if [ -f "/opt/xilinx/xrt/setup.sh" ]; then + source /opt/xilinx/xrt/setup.sh + else + err_msg " Cannot find /opt/xilinx/xrt/setup.sh " + err_msg " Please check XRT is installed correctly " + return 1 + fi + info_msg " XRT Runtime setup Done " + else + err_msg "$xrt_build_ver does not match recommended version" + cat $AWS_FPGA_REPO_DIR/SDAccel/sdaccel_xrt_version.txt + xrt_install_instructions_2018_2 + return 1 + fi + else + err_msg "XRT not installed. Please install XRT" + xrt_install_instructions_2018_2 + return 1 + fi +else + info_msg "Xilinx Vivado version is $VIVADO_TOOL_VERSION " + #info_msg " checking for file: /opt/Xilinx/SDx/${VIVADO_TOOL_VERSION}.rte.dyn/setup.sh" + info_msg " Now checking XOCL driver..." + check_xocl_driver + if [ -f "/opt/Xilinx/SDx/${VIVADO_TOOL_VERSION}.rte.dyn/setup.sh" ]; then + info_msg " Sourcing /opt/Xilinx/SDx/${VIVADO_TOOL_VERSION}.rte.dyn/setup.sh" + source /opt/Xilinx/SDx/${VIVADO_TOOL_VERSION}.rte.dyn/setup.sh + info_msg "$VIVADO_TOOL_VERSION Runtime setup Done" + else + err_msg " /opt/Xilinx/SDx/${VIVADO_TOOL_VERSION}.rte.dyn/setup.sh Not found. " + err_msg "$VIVADO_TOOL_VERSION runtime environment not installed. Please source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh" + return 1 + fi +fi + +info_msg "SDAccel runtime check PASSED" diff --git a/sdaccel_setup.sh b/sdaccel_setup.sh index 62f8100a..5254f054 100644 --- a/sdaccel_setup.sh +++ b/sdaccel_setup.sh @@ -157,14 +157,17 @@ for (( i = 0; i < ${#args[@]}; i++ )); do esac done -# Install patches as required. -setup_patches - # Check XILINX_SDX is set if ! check_set_xilinx_sdx; then return 1 fi +info_msg " XILINX_SDX is set to $XILINX_SDX" +# Install patches as required. +info_msg " Checking & installing required patches" +setup_patches + + # Update Xilinx SDAccel Examples from GitHub info_msg "Using SDx $RELEASE_VER" if [[ $RELEASE_VER =~ .*2017\.4.* || $RELEASE_VER =~ .*2018\.2.* ]]; then diff --git a/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md b/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md index d557b0b2..44a30c62 100644 --- a/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md +++ b/sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md @@ -1,6 +1,6 @@ # SDE Hardware Guide -## Table of Contents: +# Table of Contents: * [Overview](#Overview) @@ -12,10 +12,22 @@ * [IOs](#IOs) + * [Design Configuration parameters](#DesignParam) + * [PF and Address Range](#PF_AddressRange) + + * [CSR Description and Address Mapping](#CSRRange) - * [Design parameters](#DesignParam) - + * [Descriptors and Write-Back Metadata](#Descriptors) + + * [Credit Mechanism](#Credit) + + * [Write-Back Mechanism](#WBM) + + * [Data Flow Model](#DataFlow) + + * [Error Conditions](#Error) + * [Implementation - Maximum Clock Frequency](#MaxClockFreq) * [Implementation - Resource Utilization](#ResourceUtil) @@ -26,12 +38,12 @@ -## Overview +# Overview The Streaming Data Engine (SDE) provides high-performance packet streaming connectivity between the Custom Logic (CL) and the host application. The SDE provides a streaming interface to the CL and uses the shell's PCIM AXI4 interface to move packets between the CL and the host application. The SDE is a parametrizable, soft IP block that is intended to be instanciated within the CL. Each instance of the SDE provides two AXI streaming compliant interfaces viz. one Card-to-Host (C2H) and one Host-to-Card (H2C) channel. -## Feature List +# Feature List 1. High Performance PPS for C2H and H2C. 2. 12GB/s Bandwidth per channel for C2H and H2C (4KB packet at 250MHz). 3. AXI Stream compliant on the CL facing side. @@ -47,42 +59,1202 @@ The Streaming Data Engine (SDE) provides high-performance packet streaming conne * One full-duplex streaming channel (one C2H and one H2C). * One Streaming C2H Channel only (No H2C Channel) * One Streaming H2C Channel only (No C2H Channel) -If more channels or other channel combinations are required, the SDE should be instanced multiple times and the AXI fabric (Crossbar/Interconnect) should be instanced to combine the PCIM and PCIS interfaces of individual SDE instances. -## Architecture +# Architecture ![alt tag](../images/SDE_Block_Diagram.jpg) -The SDE uses shell s PCIM AXI4 interface to move packets between the AXI Streaming interface and the host. It implements a store and forward mechanism. For C2H, the packets received from the AXI Streaming interface is stored in the C2H packet buffer and are then transmitted on the PCIM AXI4 interface. For H2C, the packets received from the PCIM AXI4 interface are stored in the H2C packet buffer and are then transmitted on the AXI Streaming interface. +The SDE uses shell's PCIM AXI4 interface to move packets between the AXI Streaming interface and the host. It implements a store and forward mechanism. For C2H, the packets received from the AXI Streaming interface is stored in the C2H packet buffer and are then transmitted on the PCIM AXI4 interface. For H2C, the packets received from the PCIM AXI4 interface are stored in the H2C packet buffer and are then transmitted on the AXI Streaming interface. SDE uses descriptors to perform the data movement and the bit-fields of the descriptors are defined to contain all required information for data transfer like buffer physical addresses, length etc. To achieve minimum latency, the SDE implements a descriptor RAM that can be written by software using the PCIS interface utilizing write-combine using PF0-BAR4. The SDE implements a credit based mechanism to allow the software to track the descriptor utilization. -In order to minimize latency and reduce the complexity of the software/driver, all the information that is polled by the driver/software (for example, descriptor credits, small packet credits, write-back ring write pointer, etc...) is stored in a contiguous host memory range. The SDE is architected to update these variables together by writing to the physical memory location using the PCIM interface. +In order to minimize latency and reduce the complexity of the software/driver, all the information that is polled by the driver/software (for example, descriptor credits, write-back ring write pointer, etc...) is stored in a contiguous host memory range. The SDE is architected to update these variables together by writing to the physical memory location using the PCIM interface. -## Designing with the SDE +# Designing with the SDE -### IOs +## IOs * PCIM AXI4 Master Interface: SDE uses this interface to write data to the host. * PCIS AXI4 Slave Interface: Software uses this interface to write descriptors and configuration data to the SDE. * H2C AXI Stream Master Interface: SDE uses this interface to transmit H2C packets to the CL. * C2H AXI Stream Slave Interface: SDE uses this interface to receive C2H packets from the CL. * Clocks and Reset: SDE uses a single clock and a single synchronous active-low reset. - -### PF and Address Range -SDE implements a 16KB address space on the PCIS interface and therefore can be accessed using the PF0-BAR4. SDE uses the lower 16 bits of the address bus of the PCIS interface. - -### Design parameters -The SDE can be parameterized when the SDE is instanced in the CL. Some of the important parameters are (The full list of parameters is available in the SDE Micro-architecture Specification) - +## Design Configuration parameters +The SDE can be parameterized when the SDE is instanced in the CL. These configuration parameters are static parameters and are expected to be set when the SDE is instanced in the CL. Some important parameters are summarized below. * C2H_ONLY: Disable SDE H2C logic (Can be set to 1 if only the C2H channel is required). * H2C_ONLY: Disable SDE C2H logic (Can be set to 1 if only the C2H channel is required). * C2H_DESC_TYPE & H2C_DESC_TYPE: Descriptor Type (0 - Regular, 1 - Compact) for C2H and H2C respectively. * C2H_DESC_RAM_DEPTH & H2C_DESC_RAM_DEPTH: Descriptor RAM depth. The maximum number of descriptors for C2H and H2C respectively. -* C2H_BUF_DEPTH & H2C_BUF_DEPTH: Buffer RAM depth. +* C2H_BUF_DEPTH & H2C_BUF_DEPTH: Buffer RAM depth. + +Full List of Parameters are listed in table below. **Supported values for each parameter are listed in Supported Configurations column.** + + +| **Name** | **Default** | **Supported Configurations** | **Description** | +|----------------------|-------------|------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| C2H_ONLY | 0 | 0, 1 | This should be set to 1 if only C2H is required and H2C is not required. NOTE: If C2H_ONLY = 1, H2C_ONLY should be 0. | +| H2C_ONLY | 0 | 0, 1 | This should be set to 1 if only H2C is required and C2H is not required. NOTE: If H2C_ONLY = 1, C2H_ONLY should be 0. | +| PCIS_DATA_WIDTH | 512 | Default only| PCIS AXI4 Data Bus Width | +| PCIS_ID_WIDTH | 16 | Default only | PCIS AXI4 ID Width | +| PCIS_LEN_WIDTH | 8 | Default only | PCIS AXI4 AWLEN and ARLEN Width | +| PCIS_ADDR_WIDTH | 64 | Default only | PCIS AXI4 AWADDR and ARADDR Width | +| PCIM_DATA_WIDTH | 512 | Default only | PCIM AXI4 Data Bus Width | +| PCIM_ID_WIDTH | 3 | Default only | PCIM AXI4 ID Width | +| PCIM_LEN_WIDTH | 8 | Default only | PCIM AXI4 AWLEN and ARLEN Width | +| PCIM_ADDR_WIDTH | 64 | Default only | PCIM AXI4 AWADDR and ARADDR Width | +| C2H_DESC_TYPE | 0 | 0, 1 | Descriptor Type (0 – Regular, 1 – Compact) | +| C2H_DESC_RAM_DEPTH | 64 | 64, 128 | Descriptor RAM Depth. This is the maximum number of descriptors | +| C2H_BUF_DEPTH | 512 | 64, 128, 256, 512 | C2H Buffer RAM Depth. This is the maximum number of data slices that the buffer can hold. C2H buffer width is equal to PCIM_DATA_WIDTH. C2H Buffer size is (C2H_BUF_DEPTH\*PCIM_DATA_WIDTH/8) bytes. | +| C2H_AXIS_DATA_WIDTH | 512 | Default only | AXIS Data Width | +| C2H_USER_BIT_WIDTH | 64 | Default only | User Bit Width | +| H2C_DESC_TYPE | 0 | 0, 1 | Descriptor Type (0 – Regular, 1 – Compact) | +| H2C_DESC_RAM_DEPTH | 64 | 64, 128 | Descriptor RAM Depth. This is the maximum number of descriptors | +| H2C_BUF_DEPTH | 512 | 64, 128, 256, 512 | H2C Buffer RAM Depth. This is the maximum number of data slices that the buffer can hold. Buffer width is equal to PCIM_DATA_WIDTH. H2C Buffer size is (H2C_BUF_DEPTH\*PCIM_DATA_WIDTH/8) bytes. | +| H2C_AXIS_DATA_WIDTH | 512 | Default only | AXIS Data Width | +| H2C_USER_BIT_WIDTH | 64 | Default only | User Bit Width | +| H2C_PKT_SIZE_BYTES | 64 | Default only | H2C Small Packet Size in Bytes | +| C2H_PCIM_DM_AWID | 0 | Default only | AWID for C2H Data Mover PCIM AXI4 Write Accesses | +| C2H_PCIM_WB_AWID | 1 | Default only | AWID for C2H Write-Back PCIM AXI4 Write Accesses | +| H2C_PCIM_WB_AWID | 2 | Default only | AWID for C2H Write-Back PCIM AXI4 Write Accesses | +| C2H_PCIM_DESC_ARID | 0 | Default only | ARID for C2H Descriptor PCIM AXI4 Read Accesses | +| H2C_PCIM_DESC_ARID | 1 | Default only | ARID for H2C Descriptor PCIM AXI4 Read Accesses | +| H2C_PCIM_DM_ARID | 2 | Default only | ARID for C2H Data Mover PCIM AXI4 Read Accesses | +| PCIM_NUM_OT_RD | 64 | Default only | PCIM Number of Outstanding Reads. This should be 64 when using the AWS shell in order to maximize H2C performance. | +| H2C_PCIM_MAX_RD_SIZE | 0 | Default only | H2C Maximum AXI Read request size (0 – 512B, 1 – 1KB, 2 – 2KB, 3 – 4KB). This should be 0 when using the AWS shell in order to maximize H2C performance. | +| C2H_PCIM_MAX_WR_SIZE | 0 | Default only | C2H Maximum AXI Write request size (0 – 512B, 1 – 1KB, 2 – 2KB, 3 – 4KB). This should be 3 when using the AWS shell in order to maximize C2H performance. | + + + +### PF and Address Mapping +SDE implements a 16KB address space on the PCIS interface and therefore can be accessed using the PF0-BAR4. SDE uses the lower 16 bits of the address bus of the PCIS interface. The SDE address window should be 16KB aligned. The following table describes address mapping within SDE. + +| **Address Range** | **Size (Bytes)** | **Name** | **Access Type** | **Description** | +|-------------------|------------------|-------------------------|----------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 0x0000 – 0x0FFC | 4K | C2H Descriptor RAM | Write Only (write-combine) | Software should use this address range when writing the C2H Descriptors. Software should only use 64 byte aligned addresses in this range to write partial or full descriptors. SDE will write the descriptors into the descriptor RAM in a FIFO pattern. Only write accesses of 1DW, 4DW or 8DW are allowed to this address range. Read accesses should not be performed and are not supported in this address range. | +| 0x1000 – 0x1FFC | 4K | H2C Descriptor RAM | Write Only (write-combine) | Software should use this address range when writing the H2C Descriptors. Software should only use 64 byte aligned addresses in this range to write partial or full descriptors. SDE will write the descriptors into the descriptor RAM in a FIFO pattern. Only write accesses of 1DW, 4DW or 8DW are allowed to this address range. Read accesses should not be performed and are not supported in this address range. | +| 0x2000 – 0x2FFC | 4K | RSVD | Do not use | Reserved for future use | +| 0x3000 – 0x3FFC | 4K | CSRs | Read-Write (DW accesses) | Software should use this address range when accessing CSRs. Software should use only 4 byte aligned address of the registers to access CSRs implemented in this range. Only 1 DW read or 1 DW write accesses are allowed in this range. | + + +### CSR Description and Address Mapping +----------------- + +The CSR address space starts at the CSR base address and is organized as shown +below + +| **Address Range** | **Size (Bytes)** | **Name** | **Description** | +|-------------------|------------------|-----------|------------------------------------------| +| 0x3000 – 0x31FC | 512 | PCIS CSRs | PCIS slave Config and Status Registers | +| 0x3200 – 0x33FC | 512 | PCIM CSRs | PCIM arbiter Config and Status Registers | +| 0x3400 – 0x39FC | 1536 | C2H CSRs | C2H Config and Status Registers | +| 0x3A00 – 0x3FFC | 1536 | H2C CSRs | H2C Config and Status Registers | + +PCIS CSRs +--------- + +1. **Software Reset Register** + + + Address – PCIS_BASE_ADDR + 0x3000 + + CSR Offset – CSR_BASE_ADDR + 0x000 + + PCIS CSR Offset – PCIS_CSR_BASE_ADDR + 0x000 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|------------------------------------------------------------------------------------------------------------------| +| SW_RST | 0 | RW | 0x0 | Software Reset. When Set, reset is asserted to all the functional blocks of the SDE except the PCIS Slave Block. | +| RSVD | 31:1 | RO | 0x0 | Reserved | + + +2. **SDE Info Register** + + + Address – PCIS_BASE_ADDR + 0x3004 + + CSR Offset – CSR_BASE_ADDR + 0x004 + + PCIS CSR Offset – PCIS_CSR_BASE_ADDR + 0x004 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|-----------------------------------------| +| C2H_PRESENT | 0 | RO | 0x0 | 1 = C2H Instanced 0 = C2H Not Instanced | +| RSVD | 15:1 | RO | 0x0 | Reserved | +| H2C_PRESENT | 16 | RO | 0x0 | 1 = H2C Instanced 0 = H2C Not Instanced | +| RSVD | 31:17 | RO | 0x0 | Reserved | + + +PCIM CSRs +--------- + +RSVD for future Use + + +C2H CSRs +-------- + + **C2H CSR Address Mapping** + +| **Address Range** | **Size (Bytes)** | **Name** | **Description** | +|-------------------|------------------|---------------------|--------------------------------------------| +| 0x3400 – 0x34FC | 256 | C2H Global CSRs | C2H Global Config and Status Registers | +| 0x3500 – 0x35FC | 256 | C2H Descriptor CSRs | C2H Descriptor Config and Status Registers | +| 0x3600 – 0x36FC | 256 | C2H Data Mover CSRs | C2H Data Mover Config and Status Registers | +| 0x3700 – 0x37FC | 256 | C2H Write-back CSRs | C2H Write-Back Config and Status Registers | +| 0x3800 – 0x38FC | 256 | C2H Buffer CSRs | C2H Buffer Config and Status Registers | +| 0x3900 – 0x39FC | 256 | C2H AXIS CSRs | C2H AXI-Stream Config and Status Registers | + + +C2H Global CSRs +------------------ + +RSVD for future use. + + +C2H Descriptor CSRs +------------------- + +1. **Descriptor Credit Consumed Counter** + + + Address – PCIS_BASE_ADDR + 0x3500 + + CSR Offset – CSR_BASE_ADDR + 0x500 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x100 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|-------------------------------------------------------| +| CDT_CONSUMED | 31:0 | RW0C | 0x0 | Descriptor Credit Consumed Counter. Write 0 to clear. | + + +2. **Descriptor Credit Limit Counter** + + + Address – PCIS_BASE_ADDR + 0x3504 + + CSR Offset – CSR_BASE_ADDR + 0x504 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x104 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|--------------------|---------------------------------------------------------------------------------------------------------------------------| +| CDT_LIMIT | 31:0 | RW0C | C2H_DESC_RAM_DEPTH | Descriptor Credit Limit Counter. Write 0 to clear. When cleared, the value of the counter is reset to C2H_DESC_RAM_DEPTH. | + + +3. **Completed Descriptors Counter** + + + Address – PCIS_BASE_ADDR + 0x3508 + + CSR Offset – CSR_BASE_ADDR + 0x508 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x108 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|-------------------------------------------------| +| COMP_COUNT | 31:0 | RW0C | 0x0 | Completed Descriptor Counter. Write 0 to clear. | + + +4. **Descriptor FIFO Pointers** + + Address – PCIS_BASE_ADDR + 0x350C + + CSR Offset – CSR_BASE_ADDR + 0x50C + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x10C + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-----------------|---------------|----------|-------------------|-----------------------------------| +| FIFO_WR_PTR | 14:0 | RO | 0x0 | Descriptor FIFO Write Pointer | +| FIFO_WR_PTR_MSB | 15 | RO | 0x0 | Descriptor FIFO Write Pointer MSB | +| FIFO_RD_PTR | 30:16 | RO | 0x0 | Descriptor FIFO Read Pointer | +| FIFO_RD_PTR_MSB | 31 | RO | 0x0 | Descriptor FIFO Read Pointer MSB | + + +5. **Descriptor RAM Address** + + Address – PCIS_BASE_ADDR + 0x3510 + + CSR Offset – CSR_BASE_ADDR + 0x510 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x110 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-----------------|---------------|----------|-------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------| +| DESC_RAM_ADDR | 15:0 | RW | 0x0 | Descriptor RAM Address | +| DESC_RAM_DW_IDX | 19:16 | RWC | 0x0 | Descriptor RAM Data DW Index. This bitfield is cleared when this register is written. This will auto-increment when DESC_RAM_DATA is read or written. | +| RSVD | 31:20 | RO | 0x0 | Reserved | + + +6. **Descriptor RAM Data** + + Address – PCIS_BASE_ADDR + 0x3514 + + CSR Offset – CSR_BASE_ADDR + 0x514 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x114 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|------------------|---------------|----------|-------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| DESC_RAM_DATA_DW | 31:0 | RW | 0x0 | Descriptor RAM Data. When writing the descriptor RAM, SDE initiates a write to the descriptor RAM after all the DWs that make up the descriptor are written to this register. When reading the descriptor RAM, SDE initiates a read from the descriptor RAM when this register is read and when the DESC_RAM_DW_IDX is 0. | + + +7. **Descriptor RAM Status** + + Address – PCIS_BASE_ADDR + 0x3518 + + CSR Offset – CSR_BASE_ADDR + 0x518 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x118 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-------------------|---------------|----------|-------------------|-------------------------------------------------------------------------------------------| +| DESC_OFLOW | 0 | RW1C | 0x0 | Desc RAM Overflow Indicates that a descriptor was written when the descriptor RAM is full | +| DESC_OOO_ERROR | 1 | RW1C | 0x0 | Desc Out of Order Error | +| DESC_UNALIN_ERROR | 2 | RW1C | 0x0 | Desc Unaligned Address Error | +| DESC_FULL | 3 | RO | 0x0 | Desc RAM Full | +| DESC_EMPTY | 4 | RO | 0x0 | Desc RAM Empty | +| RSVD | 31:5 | RO | 0x0 | Reserved | + + +8. **Descriptor Info** + + Address – PCIS_BASE_ADDR + 0x3520 + + CSR Offset – CSR_BASE_ADDR + 0x520 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x120 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|------------------------------------------------------| +| DESC_TYPE | 0 | RO | 0x0 | Descriptor/Write-Back Type 0 – Regular 1 – Compact | +| RSVD | 15:1 | RO | 0x0 | RSVD | +| DESC_RAM_DEPTH | 31:16 | RO | 0x0 | Descriptor RAM Depth. Maximum Number of descriptors. | + + +C2H Data Mover CSRs +------------------- + +1. **Data Mover Config Register 0** + + Address – PCIS_BASE_ADDR + 0x3600 + + CSR Offset – CSR_BASE_ADDR + 0x600 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x200 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|-----------------| +| RSVD | 31:0 | RW | 0x0 | Reserved | + +2. **Data Mover Status Register** + + Address – PCIS_BASE_ADDR + 0x3604 + + CSR Offset – CSR_BASE_ADDR + 0x604 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x204 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-----------------|---------------|----------|-------------------|------------------------------| +| DM_BRESP_ERR | 0 | RW1C | 0x0 | Data Mover Bresp Error | +| DM_DESC_LEN_ERR | 1 | RW1C | 0x0 | Descriptor Length equal to 0 | +| RSVD | 31:2 | RO | 0x0 | Reserved | + +C2H Write-Back CSRs +------------------- + +1. **Write-Back Config Register 0** + + Address – PCIS_BASE_ADDR + 0x3700 + + CSR Offset – CSR_BASE_ADDR + 0x700 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x300 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-----------------|---------------|----------|-------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| DESC_CNT_WB_EN | 0 | RW | 0x0 | Descriptor Count Write-Back Trigger Enable. When set, SDE schedules a status counter write-back when descriptor count increments | +| PKT_CNT_WB_EN | 1 | RW | 0x0 | Packet Count Write-Back Trigger Enable. When set, SDE schedules a status counter write-back when packet count increments. | +| DESC_CDT_WB_EN | 2 | RW | 0x0 | Descriptor Credit Write-Back Trigger Enable. When set, SDE schedules a status counter write-back when descriptor credit “limit” increments. | +| MD_PTR_EN | 3 | RW | 0x0 | Metadata Pointer Write-Back Trigger Enable. When this bit is not set, SDE will not perform ring occupancy check (ring full condition) i.e the SDE will disregard the Metadata Read Pointer register. | +| DESC_CDT_WC_EN | 4 | RW | 0x0 | Descriptor Credit “Limit” Write-Back Coalesce Enable | +| DESC_CNT_WC_EN | 5 | RW | 0x0 | Descriptor Count Write-Back Coalesce Enable | +| PKT_CNT_WC_EN | 6 | RW | 0x0 | Packet Count Write-Back Coalesce Enable | +| MD_WR_PTR_WC_EN | 7 | RW | 0x0 | Metadata Write Pointer Write-Back Coalesce Enable | +| WC_CNT_MINUS1 | 13:8 | RW | 0x0 | Write-Back Coalesce Count Minus 1. Number of writes to coalesce. | +| RSVD | 31:14 | RO | 0x0 | Reserved | + +2. **Status Counters Base Address Low** + + Address – PCIS_BASE_ADDR + 0x3704 + + CSR Offset – CSR_BASE_ADDR + 0x704 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x304 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-------------------|---------------|----------|-------------------|-------------------------------------------------------------------------------------------------------------------------------| +| STATUS_WB_ADDR_LO | 31:0 | RW | 0x0 | Status Counters Base Address [31:0] This address should be 64B aligned. The least significant 6 bits of the address should 0. | + +3. **Status Write-Back Address High** + + Address – PCIS_BASE_ADDR + 0x3708 + + CSR Offset – CSR_BASE_ADDR + 0x708 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x308 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-------------------|---------------|----------|-------------------|--------------------------------------| +| STATUS_WB_ADDR_HI | 15:0 | RW | 0x0 | Status Counters Base Address [47:32] | +| RSVD | 31:16 | RO | 0x0 | Reserved | + +4. **Write-Back Coalesce Timeout Count** + + Address – PCIS_BASE_ADDR + 0x370C + + CSR Offset – CSR_BASE_ADDR + 0x70C + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x30C + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|----------------------------------------| +| WC_TO_TICK_CNT | 19:0 | RW | 0x0 | Write-Back Coalesce Timeout Tick Count | +| WC_TO_CNT | 23:20 | RW | 0x0 | Write-Back Coalesce Timeout Count | +| RSVD | 31:24 | RO | 0x0 | Reserved | + +5. **Metadata Ring Base Address Low** + + Address – PCIS_BASE_ADDR + 0x3718 + + CSR Offset – CSR_BASE_ADDR + 0x718 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x318 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|-----------------------------------------------------------------------------------------------------------------------------| +| MD_WB_ADDR_LO | 31:0 | RW | 0x0 | Metadata Ring Base Address [31:0] This address should be 64B aligned. The least significant 6 bits of the address should 0. | + +6. **Metadata Ring Base Address High** + + Address – PCIS_BASE_ADDR + 0x371C + + CSR Offset – CSR_BASE_ADDR + 0x71C + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x31C + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|------------------------------------| +| MD_WB_ADDR_HI | 15:0 | RW | 0x0 | Metadata Ring Base Address [47:32] | +| RSVD | 31:16 | RO | 0x0 | Reserved | + +7. **Metadata Ring Size** + + Address – PCIS_BASE_ADDR + 0x3720 + + CSR Offset – CSR_BASE_ADDR + 0x720 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x320 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|--------------------|---------------|----------|-------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| MD_RING_SIZE_BYTES | 31:0 | RW | 0x0 | Metadata Ring Size (in Bytes). Should be integer multiple of Metadata Size (in Bytes). The maximum number of descriptors in the ring is 65536 and minimum number of descriptors in the ring is 2. For Regular Type metadata, the maximum Metadata ring size is 1MB. For Compact Type metadata, the maximum Metadata ring size is 512KB. | + +8. **Metadata Ring Read Pointer** + + Address – PCIS_BASE_ADDR + 0x3724 + + CSR Offset – CSR_BASE_ADDR + 0x724 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x324 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|----------------------------| +| MD_RD_PTR | 15:0 | RW | 0x0 | Metadata Ring Read Pointer | +| RSVD | 31:16 | RO | 0x0 | Reserved | + +9. **Metadata Ring Write Pointer** + + Address – PCIS_BASE_ADDR + 0x3728 + + CSR Offset – CSR_BASE_ADDR + 0x728 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x328 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|------------------------------------------------| +| MD_WR_PTR | 15:0 | RW0C | 0x0 | Metadata Ring Write Pointer. Write 0 to clear. | +| RSVD | 31:16 | RO | 0x0 | Reserved | + +10. **Write Back Status Register** + + Address – PCIS_BASE_ADDR + 0x372C + + CSR Offset – CSR_BASE_ADDR + 0x72C + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x32C + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|--------------------|---------------|----------|-------------------|------------------------------------------------| +| WB_STS_BRESP_ERROR | 0 | RW1C | 0x0 | Write Back BRESP Error for Status Write-Back | +| WB_MD_BRESP_ERROR | 1 | RW1C | 0x0 | Write Back BRESP Error for Metadata Write-Back | +| RSVD | 31:2 | RO | 0x0 | Reserved | + +11. **Status DW Register** + + Address – PCIS_BASE_ADDR + 0x3730 + + CSR Offset – CSR_BASE_ADDR + 0x730 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x330 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|------------------| +| DESC_ERROR | 0 | RO | 0x0 | Descriptor Error | +| DM_ERROR | 1 | RO | 0x0 | Data Mover Error | +| WB_ERROR | 2 | RO | 0x0 | Write Back Error | +| RSVD | 31:3 | RO | 0x0 | Reserved | + +C2H Buffer CSRs +------------------- + +1. **Buffer Config Register 0** + + Address – PCIS_BASE_ADDR + 0x3800 + + CSR Offset – CSR_BASE_ADDR + 0x800 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x400 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|-----------------| +| RSVD | 31:0 | RW | 0x0 | Reserved | + +2. **Buffer Status Register** + + Address – PCIS_BASE_ADDR + 0x3804 + + CSR Offset – CSR_BASE_ADDR + 0x804 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x404 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|-----------------| +| BUF_FULL | 0 | RO | 0x0 | Buffer Full | +| BUF_EMPTY | 1 | RO | 0x0 | Buffer Empty | +| AUX_FIFO_FULL | 2 | RO | 0x0 | Aux FIFO Full | +| AUX_FIFO_EMPTY | 3 | RO | 0x0 | Aux FIFO Empty | +| RSVD | 31:4 | RO | 0x0 | Reserved | + +3. **Buffer Input Packet Count Register** + + Address – PCIS_BASE_ADDR + 0x3808 + + CSR Offset – CSR_BASE_ADDR + 0x808 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x408 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|--------------------| +| IN_PKT_CNT | 31:0 | RW0C | 0x0 | Input Packet Count | + +4. **Buffer Output Packet Count Register** + + Address – PCIS_BASE_ADDR + 0x380C + + CSR Offset – CSR_BASE_ADDR + 0x80C + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x40C + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|---------------------| +| OUT_PKT_CNT | 31:0 | RW0C | 0x0 | Output Packet Count | + +5. **Buffer Pointer Register** + + Address – PCIS_BASE_ADDR + 0x3810 + + CSR Offset – CSR_BASE_ADDR + 0x810 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x410 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|----------------------------------------| +| BUF_WR_PTR | 15:0 | RO | 0x0 | Buffer Write Pointer (RAM entry based) | +| BUF_RD_ADDR | 31:16 | RO | 0x0 | Buffer Read Address (Byte based) | + +6. **Aux RAM Pointers** + + Address – PCIS_BASE_ADDR + 0x3814 + + CSR Offset – CSR_BASE_ADDR + 0x814 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x414 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|--------------------|---------------|----------|-------------------|---------------------------| +| AUX_RAM_WR_PTR | 14:0 | RO | 0x0 | Aux RAM Write Pointer | +| AUX_RAM_WR_PTR_MSB | 15 | RO | 0x0 | Aux RAM Write Pointer MSB | +| AUX_RAM_RD_PTR | 30:16 | RO | 0x0 | Aux RAM Read Pointer | +| AUX_RAM_RD_PTR_MSB | 31 | RO | 0x0 | Aux RAM Read Pointer MSB | + +7. **Number of Bytes in Buffer Register** + + Address – PCIS_BASE_ADDR + 0x3818 + + CSR Offset – CSR_BASE_ADDR + 0x818 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x418 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| NUM_BYTES | 15:0 | RO | 0x0 | Number of Bytes in Buffer When Aux FIFO is valid, this is the number of bytes until end of current packet When Aux FIFO is not valid, this is the number of bytes in the buffer | +| RSVD | 31:16 | RO | 0x0 | Reserved | + +C2H AXI-Stream CSRs +------------------- + +1. **Packet Count** + + Address – PCIS_BASE_ADDR + 0x3900 + + CSR Offset – CSR_BASE_ADDR + 0x900 + + C2H CSR Offset – C2H_CSR_BASE_ADDR + 0x500 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|--------------------------------------------------------------------------------------------------------------| +| PKT_CNT | 31:0 | RW0C | 0x0 | Number of packets transmitted on the AXIS interface. Increments after transmitting an EOP. Write 0 to clear. | + +H2C CSRs +-------- + +H2C CSR Address Mapping +------------------- + +| **Range** | **Size (Bytes)** | **Name** | **Description** | +|-----------------|------------------|---------------------|--------------------------------------------| +| 0x3A00 – 0x3AFC | 256 | H2C Global CSRs | H2C Global Config and Status Registers | +| 0x3B00 – 0x3BFC | 256 | H2C Descriptor CSRs | H2C Descriptor Config and Status Registers | +| 0x3C00 – 0x3CFC | 256 | H2C Data Mover CSRs | H2C Data Mover Config and Status Registers | +| 0x3D00 – 0x3DFC | 256 | H2C Write-back CSRs | H2C Write-Back Config and Status Registers | +| 0x3E00 – 0x3EFC | 256 | H2C Buffer CSRs | H2C Buffer Config and Status Registers | +| 0x3F00 – 0x3FFC | 256 | H2C AXIS CSRs | H2C AXI-Stream Config and Status Registers | + +H2C Global CSRs +------------------- + +RSVD for future use + +H2C Descriptor CSRs +------------------- + +1. **Descriptor Credit Consumed Counter** + + + Address – PCIS_BASE_ADDR + 0x3B00 + + CSR Offset – CSR_BASE_ADDR + 0xB00 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x100 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|-------------------------------------------------------| +| CDT_CONSUMED | 31:0 | RW0C | 0x0 | Descriptor Credit Consumed Counter. Write 0 to clear. | + +2. **Descriptor Credit Limit Counter** + + Address – PCIS_BASE_ADDR + 0x3B04 + + CSR Offset – CSR_BASE_ADDR + 0xB04 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x104 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|--------------------|---------------------------------------------------------------------------------------------------------------------------| +| CDT_LIMIT | 31:0 | RW0C | H2C_DESC_RAM_DEPTH | Descriptor Credit Limit Counter. Write 0 to clear. When cleared, the value of the counter is reset to H2C_DESC_RAM_DEPTH. | + +3. **Completed Descriptors Counter** + + Address – PCIS_BASE_ADDR + 0x3B08 + + CSR Offset – CSR_BASE_ADDR + 0xB08 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x108 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|-------------------------------------------------| +| COMP_COUNT | 31:0 | RW0C | 0x0 | Completed Descriptor Counter. Write 0 to clear. | + +4. **Descriptor FIFO Pointers** + + Address – PCIS_BASE_ADDR + 0x3B0C + + CSR Offset – CSR_BASE_ADDR + 0xB0C + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x10C + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-----------------|---------------|----------|-------------------|-----------------------------------| +| FIFO_WR_PTR | 14:0 | RO | 0x0 | Descriptor FIFO Write Pointer | +| FIFO_WR_PTR_MSB | 15 | RO | 0x0 | Descriptor FIFO Write Pointer MSB | +| FIFO_RD_PTR | 30:16 | RO | 0x0 | Descriptor FIFO Read Pointer | +| FIFO_RD_PTR_MSB | 31 | RO | 0x0 | Descriptor FIFO Read Pointer MSB | + +5. **Descriptor RAM Address** + + Address – PCIS_BASE_ADDR + 0x3B10 + + CSR Offset – CSR_BASE_ADDR + 0xB10 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x110 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-----------------|---------------|----------|-------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------| +| DESC_RAM_ADDR | 15:0 | RW | 0x0 | Descriptor RAM Address | +| DESC_RAM_DW_IDX | 19:16 | RWC | 0x0 | Descriptor RAM Data DW Index. This bitfield is cleared when this register is written. This will auto-increment when DESC_RAM_DATA is read or written. | +| RSVD | 31:20 | RO | 0x0 | Reserved | + +6. **Descriptor RAM Data** + + Address – PCIS_BASE_ADDR + 0x3B14 + + CSR Offset – CSR_BASE_ADDR + 0xB14 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x114 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|------------------|---------------|----------|-------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| DESC_RAM_DATA_DW | 31:0 | RW | 0x0 | Descriptor RAM Data. When writing the descriptor RAM, SDE initiates a write to the descriptor RAM after all the DWs that make up the descriptor are written to this register. When reading the descriptor RAM, SDE initiates a read from the descriptor RAM when this register is read and when the DESC_RAM_DW_IDX is 0. | + +7. **Descriptor RAM Status** + + Address – PCIS_BASE_ADDR + 0x3B18 + + CSR Offset – CSR_BASE_ADDR + 0xB18 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x118 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-------------------|---------------|----------|-------------------|-------------------------------------------------------------------------------------------| +| DESC_OFLOW | 0 | RW1C | 0x0 | Desc RAM Overflow Indicates that a descriptor was written when the descriptor RAM is full | +| DESC_OOO_ERROR | 1 | RW1C | 0x0 | Desc Out of Order Error | +| DESC_UNALIN_ERROR | 2 | RW1C | 0x0 | Desc Unaligned Address Error | +| DESC_FULL | 3 | RO | 0x0 | Desc RAM Full | +| DESC_EMPTY | 4 | RO | 0x0 | Desc RAM Empty | +| RSVD | 31:1 | RO | 0x0 | Reserved | + +8. **Descriptor Info** + + Address – PCIS_BASE_ADDR + 0x3B20 + + CSR Offset – CSR_BASE_ADDR + 0xB20 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x120 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|------------------------------------------------------| +| DESC_TYPE | 0 | RO | 0x0 | Descriptor/Write-Back Type 0 – Regular 1 – Compact | +| RSVD | 15:1 | RO | 0x0 | RSVD | +| DESC_RAM_DEPTH | 31:16 | RO | 0x0 | Descriptor RAM Depth. Maximum Number of descriptors. | + + +H2C Data Mover CSRs +------------------- + +1. **Data Mover Config Register 0** + + Address – PCIS_BASE_ADDR + 0x3C00 + + CSR Offset – CSR_BASE_ADDR + 0xC00 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x200 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|-----------------| +| RSVD | 31:0 | RW | 0x0 | Reserved | + +2. **Data Mover Status Register** + + Address – PCIS_BASE_ADDR + 0x3C04 + + CSR Offset – CSR_BASE_ADDR + 0xC04 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x204 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-----------------|---------------|----------|-------------------|------------------------------| +| DM_RRESP_ERR | 0 | RW1C | 0x0 | Data Mover Rresp Error | +| DM_DESC_LEN_ERR | 1 | RW1C | 0x0 | Descriptor Length equal to 0 | +| RSVD | 31:2 | RO | 0x0 | Reserved | + + +H2C Write-Back CSRs +------------------- + +1. **Write-Back Config Register 0** + + Address – PCIS_BASE_ADDR + 0x3D00 + + CSR Offset – CSR_BASE_ADDR + 0xD00 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x300 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|---------------------------------------------------------------------------------------------------------------------------------------------| +| DESC_CNT_WB_EN | 0 | RW | 0x0 | Descriptor Count Write-Back Trigger Enable. When set, SDE schedules a status counter write-back when descriptor count increments | +| PKT_CNT_WB_EN | 1 | RW | 0x0 | Packet Count Write-Back Trigger Enable. When set, SDE schedules a status counter write-back when packet count increments. | +| DESC_CDT_WB_EN | 2 | RW | 0x0 | Descriptor Credit Write-Back Trigger Enable. When set, SDE schedules a status counter write-back when descriptor credit “limit” increments. | +| RSVD | 3 | RO | 0x0 | Reserved | +| DESC_CDT_WC_EN | 4 | RW | 0x0 | Descriptor Credit “Limit” Write-Back Coalesce Enable | +| DESC_CNT_WC_EN | 5 | RW | 0x0 | Descriptor Count Write-Back Coalesce Enable. | +| PKT_CNT_WC_EN | 6 | RW | 0x0 | Packet Count Write-Back Coalesce Enable | +| RSVD | 7 | RO | 0x0 | Reserved | +| WC_CNT_MINUS1 | 13:8 | RW | 0x0 | Write-Back Coalesce Count Minus 1. Number of writes to coalesce. | +| RSVD | 31:14 | RO | 0x0 | Reserved | + +2. **Status Counters Base Address Low** + + Address – PCIS_BASE_ADDR + 0x3D04 + + CSR Offset – CSR_BASE_ADDR + 0xD04 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x304 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-------------------|---------------|----------|-------------------|-------------------------------------------------------------------------------------------------------------------------------| +| STATUS_WB_ADDR_LO | 31:0 | RW | 0x0 | Status Counters Base Address [31:0] This address should be 64B aligned. The least significant 6 bits of the address should 0. | + +3. **Status Write-Back Address High** + + Address – PCIS_BASE_ADDR + 0x3D08 + + CSR Offset – CSR_BASE_ADDR + 0xD08 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x308 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-------------------|---------------|----------|-------------------|--------------------------------------| +| STATUS_WB_ADDR_HI | 15:0 | RW | 0x0 | Status Counters Base Address [47:32] | +| RSVD | 31:16 | RO | 0x0 | Reserved | + +4. **Write-Back Coalesce Timeout Count** + + Address – PCIS_BASE_ADDR + 0x3D0C + + CSR Offset – CSR_BASE_ADDR + 0xD0C + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x30C + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|----------------------------------------| +| WC_TO_TICK_CNT | 19:0 | RW | 0x0 | Write-Back Coalesce Timeout Tick Count | +| WC_TO_CNT | 23:20 | RW | 0x0 | Write-Back Coalesce Timeout Count | +| RSVD | 31:24 | RO | 0x0 | Reserved | + +5. **Write Back Status Register** + + Address – PCIS_BASE_ADDR + 0x3D10 + + CSR Offset – CSR_BASE_ADDR + 0xD10 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x310 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|--------------------|---------------|----------|-------------------|----------------------------------------------| +| WB_STS_BRESP_ERROR | 0 | RW1C | 0x0 | Write Back BRESP Error for Status Write-Back | +| RSVD | 31:1 | RO | 0x0 | Reserved | + +6. **Status DW Register** + + Address – PCIS_BASE_ADDR + 0x3D14 + + CSR Offset – CSR_BASE_ADDR + 0xD14 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x314 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|------------------| +| DESC_ERROR | 0 | RO | 0x0 | Descriptor Error | +| DM_ERROR | 1 | RO | 0x0 | Data Mover Error | +| WB_ERROR | 2 | RO | 0x0 | Write Back Error | +| RSVD | 31:3 | RO | 0x0 | Reserved | + + +H2C Buffer CSRs +------------------- + +1. **Buffer Config Register 0** + + Address – PCIS_BASE_ADDR + 0x3E00 + + CSR Offset – CSR_BASE_ADDR + 0xE00 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x400 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|-----------------| +| RSVD | 31:0 | RW | 0x0 | Reserved | + +2. **Buffer Status Register** + + Address – PCIS_BASE_ADDR + 0x3E04 + + CSR Offset – CSR_BASE_ADDR + 0xE04 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x404 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|-----------------| +| BUF_FULL | 0 | RO | 0x0 | Buffer Full | +| BUF_EMPTY | 1 | RO | 0x0 | Buffer Empty | +| AUX_FIFO_FULL | 2 | RO | 0x0 | Aux FIFO Full | +| AUX_FIFO_EMPTY | 3 | RO | 0x0 | Aux FIFO Empty | +| RSVD | 31:4 | RO | 0x0 | Reserved | + +3. **Buffer Input Packet Count Register** + + Address – PCIS_BASE_ADDR + 0x3E08 + + CSR Offset – CSR_BASE_ADDR + 0xE08 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x408 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|--------------------| +| IN_PKT_CNT | 31:0 | RW0C | 0x0 | Input Packet Count | + +4. **Buffer Output Packet Count Register** + + Address – PCIS_BASE_ADDR + 0x3E0C + + CSR Offset – CSR_BASE_ADDR + 0xE0C + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x40C + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|---------------------| +| OUT_PKT_CNT | 31:0 | RW0C | 0x0 | Output Packet Count | + +5. **Buffer Pointer Register** + + Address – PCIS_BASE_ADDR + 0x3E10 + + CSR Offset – CSR_BASE_ADDR + 0xE10 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x410 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|----------------------------------------| +| BUF_WR_PTR | 15:0 | RO | 0x0 | Buffer Write Pointer (RAM entry based) | +| BUF_RD_ADDR | 31:16 | RO | 0x0 | Buffer Read Address (Byte based) | + +6. **Aux RAM Pointers** + + Address – PCIS_BASE_ADDR + 0x3E14 + + CSR Offset – CSR_BASE_ADDR + 0xE14 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x414 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|--------------------|---------------|----------|-------------------|---------------------------| +| AUX_RAM_WR_PTR | 14:0 | RO | 0x0 | Aux RAM Write Pointer | +| AUX_RAM_WR_PTR_MSB | 15 | RO | 0x0 | Aux RAM Write Pointer MSB | +| AUX_RAM_RD_PTR | 30:16 | RO | 0x0 | Aux RAM Read Pointer | +| AUX_RAM_RD_PTR_MSB | 31 | RO | 0x0 | Aux RAM Read Pointer MSB | + +7. **Number of Entries in Buffer Register** + + Address – PCIS_BASE_ADDR + 0x3E18 + + CSR Offset – CSR_BASE_ADDR + 0xE18 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x418 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|------------------|---------------|----------|-------------------|--------------------------------------| +| NUM_FREE_ENTRIES | 15:0 | RO | 0x0 | Number of Free Entries in Buffer RAM | +| RSVD | 31:16 | RO | 0x0 | Reserved | + +8. **Data Mover Buffer Pointer Register** + + Address – PCIS_BASE_ADDR + 0x3E1C + + CSR Offset – CSR_BASE_ADDR + 0xE1C + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x41C + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|-------------------|---------------|----------|-------------------|-------------------------------------| +| DM_BUF_WR_PTR | 14:0 | RO | 0x0 | Data Mover Buffer Write Pointer | +| DM_BUF_WR_PTR_MSB | 15 | RO | 0x0 | Data Mover Buffer Write Pointer MSB | +| DM_AUX_WR_PTR | 30:16 | RO | 0x0 | Data Mover Aux RAM Read Pointer | +| DM_AUX_WR_PTR_MSB | 31 | RO | 0x0 | Data Mover Aux RAM Read Pointer MSB | + + +H2C AXI-Stream CSRs +------------------- + +1. **Packet Count** + + Address – PCIS_BASE_ADDR + 0x3F00 + + CSR Offset – CSR_BASE_ADDR + 0xF00 + + H2C CSR Offset – H2C_CSR_BASE_ADDR + 0x500 + +| **Field Name** | **Bit Range** | **Type** | **Default Value** | **Description** | +|----------------|---------------|----------|-------------------|--------------------------------------------------------------------------------------------------------| +| PKT_CNT | 31:0 | RW0C | 0x0 | Number of packets received on the AXIS interface. Increments after receiving an EOP. Write 0 to clear. | + + + + +### Descriptors and Write-Back Metadata +Descriptors are used to provide all required information for the data transfer. The software/driver is +expected to provide this information to the SDE. SDE supports two types of descriptors – Normal and +compact type. The choice of the descriptor type is static and has to be chosen during the design of the +application when the SDE is instanced in the CL. The normal type descriptor is 256 bit wide and the +compact type descriptor is 128 bit wide. The advantage of using the compact descriptor is the reduction +in the BRAM use for the descriptor RAM in the SDE. +Write-Back Metadata is used to provide all the required information about a completed data transfer. SDE +provides this data to the software/driver by writing to a write-back metadata ring stored in host memory. +Write-Back Metadata is only used for C2H transfers. SDE supports two types of write-back metadata – +Normal and compact type. The choice of the write-back metadata type is static and has to be chosen +during the design of the application when the SDE is instanced in the CL. The normal type write-back +metadata is 128 bit wide and the compact type write-back metadata is 64 bit wide. The type of the write- +back metadata will be the same as the descriptor type chosen. + +#### C2H Descriptor and Metadata + +#### C2H Descriptor + +| **Field** | | **Normal Type** | | | **Compact Type** | | +|----------------------|-----------------|--------------------|-------------------|---------------------|--------------------|-------------------| +| | **Bit-Width** | **High Bit Index** | **Low Bit Index** | **Bit-Width** | **High Bit Index** | **Low Bit Index** | +| **Length (Bytes)** | 32 | 31 | 0 | 32 | 31 | 0 | +| **Physical Address** | 64 | 95 | 32 | 48 | 79 | 32 | +| **RSVD** | 32 | 127 | 96 | 48 | 127 | 80 | +| **Total** | 128 | | 128 | | | | + +Description of Fields +1) Physical Address: Destination physical address for the data. This is the host guest physical address +used by the SDE to write the packet. For compact descriptor type, this address is 48 bits wide. +2) Length: Number of bytes for the data transfer. The minimum length is 1 byte. +3) RSVD: These bits are used to adjust the total length of the descriptor to 128 bits and unused in +the SDE. SDE does not store these bits in the descriptor RAM. + +#### C2H Write-Back Metadata + +| **Field** | | **Normal Type** | | | **Compact Type** | | +|--------------------|-----------------|--------------------|-------------------|---------------|--------------------|-------------------| +| | **Bit-Width** | **High Bit Index** | **Low Bit Index** | **Bit-Width** | **High Bit Index** | **Low Bit Index** | +| **Length (Bytes)** | 32 | 31 | 0 | 32 | 31 | 0 | +| **Valid** | 1 | 32 | 32 | 1 | 32 | 32 | +| **EOP** | 1 | 33 | 33 | 1 | 33 | 33 | +| **RSVD** | 30 | 63 | 34 | 30 | 63 | 34 | +| **User Bits** | 64 | 127 | 64 | NA | NA | NA | +| **Total** | 128 | | 64 | | | | + +Description of Fields + +1. Valid: This is set to 1 when the SDE writes the write-back metadata. + +2. EOP: This indicates that the EOP was received on the AXI Streaming interface + during the data transfer for this descriptor. + +3. Length: Number of bytes of data transferred for this descriptor. + +4. User Bits: These bits are sampled on the user bus of the AXI Streaming + Interface when the EOP is asserted. + +5. RVSD: These bits are used to adjust the total length of the write-back + metadata to 128 bits and are unused in the SDE. + +### H2C Descriptor + +| **Field** | | **Normal Type** | | | **Compact Type** | | +|----------------------|-----------------|--------------------|-------------------|---------------|------------------|-------------------| +| | **Bit-Width** | **High Bit Index** | **Low Bit Index** | **Bit-Width** | **High Bit Index** | **Low Bit Index** | +| **Length (Bytes)** | 32 | 31 | 0 | 32 | 31 | 0 | +| **Physical Address** | 64 | 95 | 32 | 48 | 79 | 32 | +| **EOP** | 1 | NA | 96 | 1 | NA | 80 | +| **SPB** | 1 | NA | 97 | 1 | NA | 81 | +| **RSVD** | 94 | 191 | 98 | 46 | 127 | 82 | +| **User Bits** | 64 | 255 | 192 | NA | NA | NA | +| **Total** | 256 | | 128 | | | | + +Descriptions of Fields + +1. Physical Address: Source physical address for the data. This is the host + guest physical address used by the SDE to read the packet. For compact + descriptor type, this address is 48 bits wide. This field is not used when + SPB = 1. + +2. Length: Number of bytes for the data transfer. The minimum length is 1 byte. + +3. EOP: If bit is set, the SDE will assert the “last” signal on the last beat + of the transfer on the AXI Streaming interface. + +4. SPB: This bit indicates if the source of the packet is Small Packet Buffer + or PCIM. If this bit is set, the SDE data mover will read the packets from + SPB instead of the PCIM. + +5. User Bits: These bits are driven on the user bus of the AXI Streaming + Interface when the EOP is asserted. + +6. RSVD: These bits are used to adjust the total length of the descriptor to + 256 bits and unused in the SDE. SDE does not store these bits in the + descriptor RAM. + + + +## Credit Mechanism + +SDE architecture implements a credit mechanism for descriptors and for small packet buffer. In this section, the description is provided for descriptors but the mechanism is identical for descriptors and small packet buffer. +The credit mechanism contains two counters “consumed” and “limit”. The difference between these two counters is the number of available credits based on which the software can write the descriptors. These counters are implemented as 32 bit rolling counters. These counters are present in both the SDE and the software. However, the SDE updates the software’s copy of the “limit” counter after the SDE reads a descriptor from the descriptor RAM. + +1) “consumed”: This counter is implemented in the SDE and the software. This counter is initialized to 0. When the software writes the descriptor, software will increment its copy of this counter. When the SDE receives this descriptor into the descriptor RAM, the SDE will increment its copy of this counter. + +2) “limit”: This counter is implemented in the SDE. The counter is also present in the software but the software will not change the value. software will only use this counter to determine number of available credits. This counter is initialized to the number of available credits. When the SDE completes a descriptor, it will increment its copy of this counter. It will also update the software’s copy of this counter using the PCIM interface. + +3) “available”: This is difference between the “consumed” and the “limit” counters. The software will compute this locally and will use this value to determine how many descriptors can be written. + + +## Write-Back Mechanism + +### Status Counter Write-Back + + SDE is architect-ed to update some status counters and C2H metadata to host memory locations. +software should store status counters on contiguous host memory locations. In order to minimize bandwidth usage, SDE updates all status counters using a single AXI write transaction on PCIM. All these status counters are 32 bits wide (DW) and software should configure the status counters’ host memory base address in the SDE during initialization. SDE updates the following counters periodically + +1) Status DW (Offset 0x0) +a. Bit 0 – Descriptor Error +b. Bit 1 – Data Mover Error +c. Bit 2 – Write Back Error +d. Bit 31:3 – RSVD +2) Descriptor Credit “Limit” Counter (Offset 0x4) +3) Number of completed Descriptors (Offset 0x8) +4) Packet count on the AXIS interface (Offset 0xC) +5) Metadata buffer write pointer (C2H Only) (Offset 0x10) + + The Status DW contains bits that denote error conditions in the SDE. When errors are detected, the SDE will update SW’s copy of the Status DW. The SW should poll its copy of the status DW periodically and take recovery action when it reads non-zero values in the Status DW. Each bit corresponds to a functional block that reported the error and SW should read the respective functional block’s status register to determine the exact error. After recovery action is taken, the SW should clear the error flag from the functional block’s status register. When cleared, the SDE will also update SW’s copy of the Status DW. The Status DW should not be written by SW. + + In order to conserve bandwidth and allow for maximum bandwidth usage by the data mover, SDE is architect-ed to coalesce updates to the status counters except the Status DW. SDE maintains one coalesce counter for each status counter and will coalesce the respective status counter. The number writes to coalesce is configurable using CSRs. SDE also implements a configurable timeout mechanism to update the status counters if the required number of writes are not coalesced in the timeout window. + +### C2H Metadata Write-Back + + SDE writes C2H metadata to a circular buffer that is stored in host memory. The mechanism contains two pointers – read and write. The pointers are present in the SDE and the software and they are used to determine if the circular buffer is full and empty respectively. These pointers are implemented using counters initialized to 0 and roll over when their respective values are equal to the number of metadata entries minus 1. + + The software should configure the circular buffer’s base address and circular buffer size during initialization. The software should also clear SDE’s copy of the read pointer and write pointer during initialization. + + 1) Read pointer: software increments the read pointer when it reads the write-back metadata and software periodically updates SDE’s copy of the read pointer using CSR memory writes. The SDE uses its copy to determine if there is room in the circular buffer before writing metadata. In order to provide as much bandwidth to descriptor writes, software should keep the frequency of updating the SDE’s copy low. + + When posting descriptors, the software can optionally ensure that there is room in the metadata ring. If no free entries are available in the metadata ring, the SDE will keep waiting until software updates the read-pointer. This will eventually backpressure the data mover. +The software should consider that the metadata ring is full when the value of write pointer plus 1 is equal to the read pointer. + + 2) Write pointer: SDE uses the write-pointer, metadata ring base address and ring size to determine the address to where the metadata has to be written. SDE increments the write pointer after the SDE writes the metadata to host location and SDE updates software’s copy of the write pointer by writing to host memory. The software can use the write pointer value to determine how many valid metadata entries are present in the circular buffer. + + +## Data Flow Model + +### C2H + +1) APP: Application requests the software to move packets from the CL by calling software provided APIs. + +2) CL: The CL streams data into the SDE’s buffer. + +3) Software: When enough descriptor credits and metadata entries are available, software will write the descriptor (physical address of packet buffer and length) to the SDE’s desc RAM using PF0-BAR4 and write-combine. + +4) SDE: When the software writes the descriptors, the SDE will increment the “consumed”. SDE’s data mover will read the descriptor from the desc RAM. When the SDE’s data mover reads the descriptor, SDE increments the descriptor credit “limit” counter and also schedules an update to the software’s copy of this counter using PCIM. + +5) Software: Software will read the “limit” and compute number of available credits to figure out if more descriptors can be written. + +6) SDE: If there is enough data (as requested in the desc) or if there is an EOP, SDE Data Mover initiates data transfer by issuing writes to host on PCIM. If there is not enough data and if an EOP is not received, data mover will wait. + +7) SDE: After the data mover completes the data transfer and if metadata ring is not full, SDE writes the metadata (valid bit, byte count, EOP and any user bits) to the metadata ring using PCIM. SDE increments its copy of the metadata ring write-pointer and will also schedule an update to software’s copy of the metadata ring write-pointer. + +8) SDE: The SDE increments the “number of completed descriptors” counter and metadata write pointer. The SDE also schedules an update to software’s copy of these counters. + +9) Software: Software will poll the valid bit of the metadata to figure out that the data transfer is complete. + +10) Software: After reading the metadata, software clears the valid bit of the metadata that was read. Software will increment read pointer and when required, will update SDE’s copy of the metadata ring read pointer. Note if software ensures that metadata entries are available before posting the descriptor, metadata pointers can be disabled and the software is not required to update SDE’s copy of the read pointer. + + +### H2C + +1) APP: Application requests the software to move packets to the CL using software provided APIs. + +2) Software: When enough descriptor credits are available, software will write the descriptor (physical address of packet buffer, length, EOP and SPB bits) to the SDE’s desc RAM using PF0-BAR4 and write-combine. + +3) SDE: When the software writes the descriptors, the SDE will increment the “consumed”. SDE’s data mover will read the descriptor from the desc RAM. When the SDE’s data mover reads the descriptor, SDE increments the descriptor credit “limit” counter and also schedules an update to the software’s copy of this counter using PCIM. + +4) Software: Software will read the “limit” and compute number of available credits to figure out if more descriptors can be written. + +5) SDE: If there is enough room in the SDE buffer (as requested by the descriptor), SDE Data Mover initiates data transfer by issuing reads from host DRAM on PCIM. When the descriptor specifies the source of the packet as the small-pkt buffer, the data mover will read from small-pkt buffer instead of using PCIM. If there is not enough room in the buffer, data mover will wait. + +6) SDE: Data mover writes the received PCIM read data to the buffer to be streamed to the CL (for non-small packet buffer case). + +7) SDE: SDE implements a master streaming interface that reads data from the buffer and streams it to the CL. + +8) SDE: After the data mover completes the data transfer, SDE increments the “number of completed descriptors” counter and also schedules an update to the software’s copy of this counter using PCIM. + +9) Software: Software will poll its copy of “number of completed descriptors” to figure out that data transfer is complete. + +10) Software: Software can also poll its copy of “packet count” to figure out that a packet has been transmitted on the AXI-Stream interface. + + + +## Error Conditions + +### C2H Error Conditions + +1. Descriptor RAM Overflow: Occurs when the descriptor RAM is full and SW + writes a new descriptor + +2. Descriptor Out of Order Error: If a descriptor write is split into multiple + writes, each write should use incrementing address. If this condition is + violated, the out of order error is set. + +3. Descriptor Unaligned Error: Occurs when a non-64B aligned address is used + for writing descriptors. + +4. Data Mover BRESP Error: Occurs when a non-zero BRESP is received on the PCIM + interface for data writes + +5. Data Mover Descriptor Length Error: Occurs when data mover encounters a + descriptor with length equal to 0. + +6. Write Back BRESP Error: Occurs when a non-zero BRESP is received on the PCIM + interface for write-back writes. + +### H2C Error Conditions + +1. Descriptor RAM Overflow: Occurs when the descriptor RAM is full and SW + writes a new descriptor + +2. Descriptor Out of Order Error: If a descriptor write is split into multiple + writes, each write should use incrementing address. If this condition is + violated, the out of order error is set. + +3. Descriptor Unaligned Error: Occurs when a non-64B aligned address is used + for writing descriptors. + +4. Data Mover RRESP Error: Occurs when a non-zero RRESP is received on the PCIM + interface for data reads + +5. Data Mover Descriptor Length Error: Occurs when data mover encounters a + descriptor with length equal to 0. + +6. Write Back BRESP Error: Occurs when a non-zero BRESP is received on the PCIM + interface for write-back writes. ### Implementation - Maximum Clock Frequency diff --git a/sdk/linux_kernel_drivers/edma/README.md b/sdk/linux_kernel_drivers/edma/README.md index 87ec13eb..c50c061f 100644 --- a/sdk/linux_kernel_drivers/edma/README.md +++ b/sdk/linux_kernel_drivers/edma/README.md @@ -1,6 +1,8 @@ # Using AWS EDMA in C/C++ application +## :exclamation: Please Note: Support for EDMA driver has ended. AWS strongly recommends moving applications to XDMA driver. EDMA driver will be deprecated and removed in the Developer Kit release 1.4.7. + ## Table of Content 1. [Overview](#overview) diff --git a/sdk/linux_kernel_drivers/edma/RELEASE_NOTES.md b/sdk/linux_kernel_drivers/edma/RELEASE_NOTES.md index 68d69814..cc7ba192 100644 --- a/sdk/linux_kernel_drivers/edma/RELEASE_NOTES.md +++ b/sdk/linux_kernel_drivers/edma/RELEASE_NOTES.md @@ -1,5 +1,8 @@ # EDMA Driver Release Notes + +## :exclamation: Please Note: Support for EDMA driver has ended. AWS strongly recommends moving applications to XDMA driver. EDMA driver will be deprecated and removed in the Developer Kit release 1.4.7. + This is the first release of the EDMA driver. This driver is still under development and performance may not be achieving maximal potential. This is a Linux kernel driver only diff --git a/sdk/linux_kernel_drivers/edma/edma_install.md b/sdk/linux_kernel_drivers/edma/edma_install.md index 4307f9d4..b1bb36e3 100644 --- a/sdk/linux_kernel_drivers/edma/edma_install.md +++ b/sdk/linux_kernel_drivers/edma/edma_install.md @@ -1,6 +1,9 @@ # Elastic DMA (EDMA) Installation and Frequently Asked Questions + +## :exclamation: Please Note: Support for EDMA driver has ended. AWS strongly recommends moving applications to XDMA driver. EDMA driver will be deprecated and removed starting Developer Kit release 1.4.7. + EDMA is a Linux kernel driver provided by AWS for using DMA and/or User-defined interrupts for AWS FPGAs. Please see [EDMA README](README.md) for details. # Table of Contents diff --git a/sdk/linux_kernel_drivers/edma/user_defined_interrupts_README.md b/sdk/linux_kernel_drivers/edma/user_defined_interrupts_README.md index a98e47ae..f99608ad 100644 --- a/sdk/linux_kernel_drivers/edma/user_defined_interrupts_README.md +++ b/sdk/linux_kernel_drivers/edma/user_defined_interrupts_README.md @@ -1,5 +1,8 @@ # Using AWS FPGA user-defined interrupts in C/C++ application + +## :exclamation: Please Note: Support for EDMA driver has ended. AWS strongly recommends moving applications to XDMA driver. EDMA driver will be deprecated and removed in the Developer Kit release 1.4.7. + AWS FPGA provides options for Custom Logic (CL) to generate user-defined interrupt events, sent to the instance via MSI-X message. At the hardware level, these interrupt event are defined in [AWS Shell Interface Specification](../../../hdk/docs/AWS_Shell_Interface_Specification.md) diff --git a/sdk/tests/fio_dma_tools/README.md b/sdk/tests/fio_dma_tools/README.md index fff997da..2ff26ad8 100644 --- a/sdk/tests/fio_dma_tools/README.md +++ b/sdk/tests/fio_dma_tools/README.md @@ -39,7 +39,7 @@ fpga-load-local-image -S 0 -I -F ## Load DMA Driver -Load the XDMA or EDMA driver in an interrupt or polled mode. In the verify and benchmark steps below, we are using the XDMA driver. +Load the XDMA driver in an interrupt or polled mode. In the verify and benchmark steps below, we are using the XDMA driver. ``` insmod $SDK_DIR/linux_kernel_drivers/xdma/xdma.ko @@ -51,18 +51,6 @@ insmod $SDK_DIR/linux_kernel_drivers/xdma/xdma.ko insmod $SDK_DIR/linux_kernel_drivers/xdma/xdma.ko poll_mode=1 ``` --or- - -``` -insmod $SDK_DIR/linux_kernel_drivers/edma/edma-drv.ko -``` - --or- - -``` -insmod $SDK_DIR/linux_kernel_drivers/edma/edma-drv.ko poll_mode=1 -``` - ## Run DMA verify test Verify DMA IOs are working as expected, assuming the XDMA driver has been loaded. @@ -119,11 +107,11 @@ XDMA Read Results: The FIO config file naming conventions are: ``` -_<# DMA channels>_<# FIO workers>-_.fio +_<# DMA channels>_<# FIO workers>-_.fio '# DMA channels' is 4 DMA channels in these sample FIO config files '# FIO workers' is 4 concurrent FIO worker processes to drive the 4 DMA channels - 'IO size' is the pwrite/pread user buffer size (that may be segmented by the EDMA driver into single_transaction_size DMA IO segments). + 'IO size' is the pwrite/pread user buffer size (that may be segmented by the XDMA driver into single_transaction_size DMA IO segments). ``` ## What is the benefit of using `poll_mode`? @@ -137,47 +125,14 @@ XDMA: ./fio xdma_4-ch_4-X_write.fio ./fio xdma_4-ch_4-X_read.fio -EDMA: -./fio edma_4-ch_4-X_write.fio -./fio edma_4-ch_4-X_read.fio - ``` The above '4-X' scripts include 4 channel group reporting for a set of blocksizes {4KB, 8KB, 16KB, 32KB, 64KB, 256KB, 1MB, 2MB} -## How do I use the EDMA driver to perform my own comparison using the same FIO benchmarking tool? - -To use the EDMA driver, see the EDMA related "Load DMA Driver" steps, then simply use the "edma*.fio" config files as input to FIO in the "Run DMA benchmark tests" section. Note that the XDMA driver must first be unloaded (e.g. `rmmod xdma`) before the EDMA driver can be loaded. - -``` -./fio edma_4-ch_4-1M_verify.fio -./fio edma_4-ch_4-1M_write.fio -./fio edma_4-ch_4-1M_read.fio - -EDMA Write Results: - -2xl int mode: 2.2GB/s - - WRITE: bw=2126MiB/s (2229MB/s), 531MiB/s-539MiB/s (557MB/s-565MB/s), io=64.0GiB (68.7GB), run=30400-30832msec - -2xl poll mode: 9GB/s - - WRITE: bw=8633MiB/s (9053MB/s), 2158MiB/s-2311MiB/s (2263MB/s-2423MB/s), io=64.0GiB (68.7GB), run=7089-7591msec - -EDMA Read Results: - -2xl int mode: 2.4GB/s - - READ: bw=2382MiB/s (2497MB/s), 595MiB/s-596MiB/s (624MB/s-625MB/s), io=64.0GiB (68.7GB), run=27476-27516msec - -2xl poll mode: 9GB/s - - READ: bw=8769MiB/s (9194MB/s), 2192MiB/s-2273MiB/s (2299MB/s-2384MB/s), io=64.0GiB (68.7GB), run=7207-7474msec -``` -## What is the XDMA and EDMA driver test methodology? +## What is the XDMA driver test methodology? -The FIO benchmarking tests for the Xilinx XDMA and AWS EDMA drivers are very similar, with only differences in device names and the fsync ratio (EDMA only). The XDMA and EDMA driver are benchmarked in interrupt and polled modes. FIO was configured for pwrite/pread (ioengine=psync) and to allocate memory using mmap (iomem=mmap). When using malloc instead of mmap, throughput becomes less consistent for the larger IO sizes. To maximize DMA IO concurrency, 4 parallel FIO workers each drive their own DMA channel to their own 16GB section of the 64GB FPGA DDR. +The XDMA driver is benchmarked in interrupt and polled modes. FIO was configured for pwrite/pread (ioengine=psync) and to allocate memory using mmap (iomem=mmap). When using malloc instead of mmap, throughput becomes less consistent for the larger IO sizes. To maximize DMA IO concurrency, 4 parallel FIO workers each drive their own DMA channel to their own 16GB section of the 64GB FPGA DDR. -## How did we capture the above XDMA and EDMA FIO performance metrics? +## How did we capture the above XDMA FIO performance metrics? At the end of the test, FIO will report the individual worker (per DMA channel) results and the aggregated results for all workers in the group (e.g. 'Run status group 0 (all jobs)'). The aggregated results are the results posted above in 'Results' for the 'Run DMA benchmark tests' step. diff --git a/sdk/tests/non_root_log_into_group.sh b/sdk/tests/non_root_log_into_group.sh new file mode 100644 index 00000000..3435568c --- /dev/null +++ b/sdk/tests/non_root_log_into_group.sh @@ -0,0 +1,26 @@ +#!/usr/bin/bash + +# Amazon FPGA Hardware Development Kit +# +# Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. + +set -e +SLOT=$1 +fpga-describe-local-image -S $SLOT +echo "$WORKSPACE/hdk/cl/examples/cl_hello_world/software/runtime/test_hello_world --slot $SLOT" > /tmp/run_non_root_cmd_as_new_group +newgrp fpgauser << ES +chmod 755 /tmp/run_non_root_cmd_as_new_group +/tmp/run_non_root_cmd_as_new_group +ES + diff --git a/sdk/tests/test_edma.py b/sdk/tests/test_edma.py index 69c8fecd..5d1a9f8e 100644 --- a/sdk/tests/test_edma.py +++ b/sdk/tests/test_edma.py @@ -54,14 +54,15 @@ def setup_class(cls): (cls.cl_dram_dma_agfi, cl_dram_dma_afi) = cls.get_agfi_from_readme('cl_dram_dma') - for slot in range(AwsFpgaTestBase.num_slots): - AwsFpgaTestBase.load_msix_workaround(slot) - cls.setup_fio_tools() return def setup_method(self, test_method): + + for slot in range(AwsFpgaTestBase.num_slots): + AwsFpgaTestBase.fpga_clear_local_image(slot) + aws_fpga_test_utils.remove_all_drivers() for slot in range(AwsFpgaTestBase.num_slots): @@ -69,11 +70,12 @@ def setup_method(self, test_method): assert AwsFpgaTestBase.check_fpga_afi_loaded(self.cl_dram_dma_agfi, slot), "{} not loaded in slot {}".format(self.cl_dram_dma_agfi, slot) def teardown_method(self, test_method): - aws_fpga_test_utils.remove_all_drivers() for slot in range(AwsFpgaTestBase.num_slots): AwsFpgaTestBase.fpga_clear_local_image(slot) + aws_fpga_test_utils.remove_all_drivers() + @pytest.fixture(params=['poll','interrupt']) def driver_mode(self, request): return request.param diff --git a/sdk/tests/test_fpga_tools.py b/sdk/tests/test_fpga_tools.py index 85deefb9..def4a6ca 100644 --- a/sdk/tests/test_fpga_tools.py +++ b/sdk/tests/test_fpga_tools.py @@ -186,7 +186,7 @@ def test_clear_local_image(self): # Clear again immediately. It should fail because busy (rc, stdout, stderr) = self.run_cmd("sudo fpga-clear-local-image --request-timeout {} -S {} -A".format(self.DEFAULT_REQUEST_TIMEOUT, slot), echo=True, check=False) assert rc != 0 - assert len(stdout) == 2 + assert len(stdout) == 3 assert len(stderr) == 1 assert stdout[0] == 'Error: (3) busy' diff --git a/sdk/tests/test_non_root_access.py b/sdk/tests/test_non_root_access.py new file mode 100644 index 00000000..09482b0b --- /dev/null +++ b/sdk/tests/test_non_root_access.py @@ -0,0 +1,83 @@ +#!/usr/bin/env python2.7 + +# Amazon FPGA Hardware Development Kit +# +# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. + +''' +Pytest module: + +Call using ```pytest test_drivers.py``` + +See TESTING.md for details. +''' + +import os +from os.path import basename, dirname, realpath +import pytest +import sys +import traceback +try: + import aws_fpga_utils + import aws_fpga_test_utils + from aws_fpga_test_utils.AwsFpgaTestBase import AwsFpgaTestBase +except ImportError as e: + traceback.print_tb(sys.exc_info()[2]) + print "error: {}\nMake sure to source sdk_setup.sh".format(sys.exc_info()[1]) + sys.exit(1) + +logger = aws_fpga_utils.get_logger(__name__) + +class TestNonRootAccess(AwsFpgaTestBase): + ''' + Pytest test class. + + NOTE: Cannot have an __init__ method. + ''' + + @classmethod + def setup_class(cls): + ''' + Do any setup required for tests. + ''' + AwsFpgaTestBase.setup_class(cls, __file__) + + AwsFpgaTestBase.assert_sdk_setup() + + assert AwsFpgaTestBase.running_on_f1_instance(), "This test must be run on an F1 instance. Running on {}".format(aws_fpga_test_utils.get_instance_type()) + + (cls.cl_hello_world_agfi, cl_hello_world_afi) = cls.get_agfi_from_readme('cl_hello_world') + return + + def setup_method(self, test_method): + + for slot in range(AwsFpgaTestBase.num_slots): + self.fpga_load_local_image(self.cl_hello_world_agfi, slot, + as_root=False) + assert AwsFpgaTestBase.check_fpga_afi_loaded(self.cl_hello_world_agfi, slot), "{} not loaded in slot {}".format(self.cl_hello_world_agfi, slot) + cmd = "cd $WORKSPACE/hdk/cl/examples/cl_hello_world/software/runtime && make " + assert os.system(cmd) == 0 + logger.info("Compiled hello world") + + def teardown_method(self, test_method): + for slot in range(AwsFpgaTestBase.num_slots): + AwsFpgaTestBase.fpga_clear_local_image(slot, as_root=False) + + def test_hello_world_as_non_root_user(self): + for slot in range(AwsFpgaTestBase.num_slots): + (rc, out, err) = self.run_cmd("bash -x {}/sdk/tests/non_root_log_into_group.sh {}".format(os.environ['WORKSPACE'], slot)) + logger.info("{}\n{}".format(out, err)) + assert rc == 0 + AwsFpgaTestBase.fpga_set_virtual_dip_switch("1111111111111111", slot, as_root=False) + assert AwsFpgaTestBase.fpga_get_virtual_led(slot, as_root=False) == "1010-1101-1101-1110" diff --git a/sdk/tests/test_xdma.py b/sdk/tests/test_xdma.py index 22720a62..8f507c60 100644 --- a/sdk/tests/test_xdma.py +++ b/sdk/tests/test_xdma.py @@ -61,26 +61,29 @@ def setup_class(cls): (cls.cl_dram_dma_agfi, cl_dram_dma_afi) = cls.get_agfi_from_readme('cl_dram_dma') - for slot in range(AwsFpgaTestBase.num_slots): - AwsFpgaTestBase.load_msix_workaround(slot) - cls.setup_fio_tools() return def setup_method(self, test_method): + + for slot in range(AwsFpgaTestBase.num_slots): + AwsFpgaTestBase.fpga_clear_local_image(slot) + aws_fpga_test_utils.remove_all_drivers() for slot in range(AwsFpgaTestBase.num_slots): self.fpga_load_local_image(self.cl_dram_dma_agfi, slot) assert AwsFpgaTestBase.check_fpga_afi_loaded(self.cl_dram_dma_agfi, slot), "{} not loaded in slot {}".format(self.cl_dram_dma_agfi, slot) + def teardown_method(self, test_method): - aws_fpga_test_utils.remove_all_drivers() for slot in range(AwsFpgaTestBase.num_slots): AwsFpgaTestBase.fpga_clear_local_image(slot) + aws_fpga_test_utils.remove_all_drivers() + @pytest.fixture(params=['poll','interrupt']) def driver_mode(self, request): return request.param diff --git a/sdk/userspace/add_udev_rules.sh b/sdk/userspace/add_udev_rules.sh old mode 100644 new mode 100755 diff --git a/sdk/userspace/fpga_libs/fpga_dma/fpga_dma_utils.c b/sdk/userspace/fpga_libs/fpga_dma/fpga_dma_utils.c index 2ba089df..b8572ce7 100644 --- a/sdk/userspace/fpga_libs/fpga_dma/fpga_dma_utils.c +++ b/sdk/userspace/fpga_libs/fpga_dma/fpga_dma_utils.c @@ -23,6 +23,9 @@ #include #include +#include +#include + #include "utils/log.h" #include "fpga_dma.h" #include "fpga_pci.h" @@ -30,20 +33,27 @@ #define MAX_FD_LEN 256 #define PCI_DEV_FMT "%04x:%02x:%02x.%d" +typedef int (*get_dev_number_t)(char *, int *); + struct dma_opts_s { char *drv_name; char *drv_model_name; char *drv_write_name; char *drv_read_name; uint8_t n_channels; + get_dev_number_t get_dev_number_f; }; +static int fpga_dma_get_xdma_dev_number(char *device_name, int *device_num); +static int fpga_dma_get_edma_dev_number(char *device_name, int *device_num); + static const struct dma_opts_s xdma_opts = { .drv_name = "xdma", .drv_model_name = "xdma", .drv_write_name = "h2c", .drv_read_name = "c2h", .n_channels = 4, + .get_dev_number_f = fpga_dma_get_xdma_dev_number, }; static const struct dma_opts_s edma_opts = { @@ -52,6 +62,7 @@ static const struct dma_opts_s edma_opts = { .drv_write_name = "queue", .drv_read_name = "queue", .n_channels = 1, + .get_dev_number_f = fpga_dma_get_edma_dev_number, }; static const struct dma_opts_s *fpga_dma_get_dma_opts( @@ -64,7 +75,6 @@ static const struct dma_opts_s *fpga_dma_get_dma_opts( } } - int fpga_dma_open_queue(enum fpga_dma_driver which_driver, int slot_id, int channel, bool is_read) { @@ -73,27 +83,25 @@ int fpga_dma_open_queue(enum fpga_dma_driver which_driver, int slot_id, rc = fpga_dma_device_id(which_driver, slot_id, channel, is_read, device_file); - fail_on(rc, err, "unable to get device id to open DMA queue"); + /* TODO: this isn't really the right error code. */ + fail_on_with_code(rc, err, rc, -EINVAL, + "unable to get device id to open DMA queue"); fd = open(device_file, is_read ? O_RDONLY : O_WRONLY); - fail_on(rc = (fd < 0) ? fd : 0, err, "unable to open DMA device queue: %s", + fail_on_with_code(fd < 0, err, rc, fd, "unable to open DMA device queue: %s", device_file); return fd; err: - if (rc > 0) { - return -rc; - } else { - return rc; - } + return rc; } - int fpga_dma_device_id(enum fpga_dma_driver which_driver, int slot_id, int channel, bool is_read, char device_file[static FPGA_DEVICE_FILE_NAME_MAX_LEN]) { int rc = 0; + int device_num; char read_or_write[16]; const struct dma_opts_s *dma_opts = fpga_dma_get_dma_opts(which_driver); fail_on(rc = (dma_opts == NULL) ? -EINVAL : 0, out, "invalid DMA driver"); @@ -110,72 +118,26 @@ int fpga_dma_device_id(enum fpga_dma_driver which_driver, int slot_id, } if (rc < 1) { - return FPGA_ERR_FAIL; + return FPGA_ERR_SOFTWARE_PROBLEM; } - if (which_driver == FPGA_DMA_EDMA) { - /* TODO: this is not likely to work for multiple slots */ - #define DRV_CHANNEL_FMT "/dev/%s%i_%s_0" - return snprintf(device_file, MAX_FD_LEN, DRV_CHANNEL_FMT, - dma_opts->drv_name, slot_id, read_or_write); - } else if (which_driver == FPGA_DMA_XDMA) { - /* We have an XDMA driver, we do not know if the descriptors - * /dev/xdma[07]_[hc]2[ch]_0 correspond to the slots. We will discover - * using the sysfs mappings of the FPGA card mapping on PCI - */ - struct fpga_pci_resource_map resource; - char dbdf[16]; - char sysfs_path[32]; - int actual_instance = -1; - char real_path[MAX_FD_LEN]; - - rc = fpga_pci_get_resource_map(slot_id, FPGA_APP_PF, &resource); - fail_on(rc, out, "Could not get resource map"); - rc = snprintf(dbdf, - 16, - PCI_DEV_FMT, - resource.domain, - resource.bus, - resource.dev, - resource.func); - fail_on(rc < 1, out, "Could not record DBDF"); - sprintf(sysfs_path, "/sys/class/xdma/"); - for (int s = 0; s < FPGA_SLOT_MAX; s++) { - char sysfs_path_instance[MAX_FD_LEN]; - char *possible_dbdf = NULL; - sprintf(sysfs_path_instance, "%sxdma%d_%s_%d/device", - sysfs_path, s, dma_opts->drv_read_name, channel); - /* Check if device exists in sys fs */ - if (access(sysfs_path_instance, F_OK) != 0) - continue; - - possible_dbdf = realpath(sysfs_path_instance, real_path); - if (possible_dbdf == NULL) { - fail_on(true, out, "Could not get real path of the device file"); - } - possible_dbdf = basename(real_path); - if (strncmp(possible_dbdf, dbdf, 12) == 0) { - actual_instance = s; - break; - } - continue; - } - fail_on(actual_instance == -1, out, - "Could not find the actual XDMA driver instance for the slot"); - rc = snprintf(device_file, - MAX_FD_LEN, - DRV_CHANNEL_FMT, - dma_opts->drv_name, - actual_instance, - read_or_write); - fail_on(rc = (rc < 0) ? FPGA_ERR_FAIL : 0, out, - "Could not generate device_file"); - } + rc = fpga_pci_get_dma_device_num(which_driver, slot_id, &device_num); + fail_on(rc != 0, out, "Unable to get device number"); + + + rc = snprintf(device_file, MAX_FD_LEN, "/dev/%s%i_%s_%d", + dma_opts->drv_name, + device_num, + read_or_write, + channel); + fail_on_with_code(rc < 0, out, rc, FPGA_ERR_SOFTWARE_PROBLEM, + "Could not generate device_file"); + rc = 0; + out: return rc; } - int fpga_dma_burst_read(int fd, uint8_t *buffer, size_t xfer_sz, size_t address) { @@ -190,7 +152,7 @@ int fpga_dma_burst_read(int fd, uint8_t *buffer, size_t xfer_sz, /* size of xfer */ xfer_sz - read_offset, /* read address */ address + read_offset); if (rc < 0) { - fail_on((rc = (rc < 0) ? -errno : 0), out, "call to pread failed."); + fail_on_with_code(rc < 0, out, rc, -errno, "call to pread failed."); } read_offset += rc; } @@ -214,7 +176,7 @@ int fpga_dma_burst_write(int fd, uint8_t *buffer, size_t xfer_sz, /* size of xfer */ xfer_sz - write_offset, /* read address */ address + write_offset); if (rc < 0) { - fail_on((rc = (rc < 0) ? -errno : 0), out, "call to pwrite failed."); + fail_on_with_code(rc < 0, out, rc, -errno, "call to pwrite failed."); } write_offset += rc; } @@ -222,3 +184,138 @@ int fpga_dma_burst_write(int fd, uint8_t *buffer, size_t xfer_sz, out: return rc; } + +int fpga_pci_get_dma_device_num(enum fpga_dma_driver which_driver, + int slot_id, int *device_num) +{ + int rc; + char dbdf[16]; + char path[64]; + int _device_num; + struct dirent *entry; + char real_path[MAX_FD_LEN]; + char *possible_dbdf = NULL; + struct fpga_pci_resource_map resource; + char sysfs_path_instance[MAX_FD_LEN + sizeof(entry->d_name) + sizeof(path)]; + + const struct dma_opts_s *dma_opts = fpga_dma_get_dma_opts(which_driver); + fail_on_with_code(!dma_opts, err, rc, -EINVAL, "invalid DMA driver"); + rc = snprintf(path, sizeof(path), "/sys/class/%s", dma_opts->drv_name); + fail_on_with_code(rc < 1, err, rc, FPGA_ERR_SOFTWARE_PROBLEM, + "snprintf failed"); + + /* This call must be before the lock, because the call holds the lock. */ + rc = fpga_pci_get_resource_map(slot_id, FPGA_APP_PF, &resource); + fail_on(rc, err, "Could not get resource map"); + rc = snprintf(dbdf, + sizeof(dbdf), + PCI_DEV_FMT, + resource.domain, + resource.bus, + resource.dev, + resource.func); + fail_on_with_code(rc < 1, err, rc, FPGA_ERR_SOFTWARE_PROBLEM, + "Could not record DBDF"); + + DIR *dirp = opendir(path); + fail_on_with_code(!dirp, err, rc, FPGA_ERR_SOFTWARE_PROBLEM, + "opendir failed for path=%s", path); + +#if defined(FPGA_PCI_USE_READDIR_R) + struct dirent entry_stack, *result; + entry = &entry_stack; + memset(entry, 0, sizeof(struct dirent)); +#else + /** + * Protect calls to readdir with a mutex because multiple threads may call + * this function, which always reads from the same directory. The man page + * for readdir says the POSIX spec does not require threadsafety. + */ + pthread_mutex_lock(&fpga_pci_readdir_mutex); +#endif + + while (true) { + /* reset so that the loop termination detection below works */ + _device_num = -1; + +#if defined(FPGA_PCI_USE_READDIR_R) + memset(entry, 0, sizeof(struct dirent)); + readdir_r(dirp, entry, &result); + if (result == NULL) { + /** No more directories */ + break; + } +#else + entry = readdir(dirp); + if (entry == NULL) { + /** No more directories */ + break; + } +#endif + + rc = (*dma_opts->get_dev_number_f)(entry->d_name, &_device_num); + if (rc != 0) { + continue; + } + + rc = snprintf(sysfs_path_instance, sizeof(sysfs_path_instance), + "%s/%s/device", path, entry->d_name); + fail_on_with_code(rc < 2, err_unlock, rc, FPGA_ERR_SOFTWARE_PROBLEM, + "snprintf failed to build sysfs path"); + possible_dbdf = realpath(sysfs_path_instance, real_path); + if (possible_dbdf == NULL) { + continue; + } + possible_dbdf = basename(real_path); + if (strncmp(possible_dbdf, dbdf, 12) == 0) { + break; /* found device */ + } + /* continue... */ + } +#if !defined(FPGA_PCI_USE_READDIR_R) + pthread_mutex_unlock(&fpga_pci_readdir_mutex); +#endif + fail_on_with_code(_device_num == -1, err, rc, FPGA_ERR_PCI_MISSING, + "Unable to find device num"); + + closedir(dirp); + *device_num = _device_num; + errno = 0; + return 0; + +err_unlock: +#if !defined(FPGA_PCI_USE_READDIR_R) + pthread_mutex_unlock(&fpga_pci_readdir_mutex); +#endif + +err: + if (dirp) { + closedir(dirp); + } + errno = 0; + return rc; +} + +static int fpga_dma_get_xdma_dev_number(char *device_name, int *device_num) +{ + int rc; + int num; + rc = sscanf(device_name, "xdma%d_control", &num); + if (rc == 1) { + *device_num = num; + return 0; + } + return FPGA_ERR_SOFTWARE_PROBLEM; +} + +static int fpga_dma_get_edma_dev_number(char *device_name, int *device_num) +{ + int rc; + int num; + rc = sscanf(device_name, "edma%d_queue_0", &num); + if (rc == 1) { + *device_num = num; + return 0; + } + return FPGA_ERR_SOFTWARE_PROBLEM; +} diff --git a/sdk/userspace/fpga_libs/fpga_mgmt/fpga_hal_mbox.c b/sdk/userspace/fpga_libs/fpga_mgmt/fpga_hal_mbox.c index 6f07f185..d24ea2fb 100644 --- a/sdk/userspace/fpga_libs/fpga_mgmt/fpga_hal_mbox.c +++ b/sdk/userspace/fpga_libs/fpga_mgmt/fpga_hal_mbox.c @@ -135,7 +135,7 @@ fpga_hal_mbox_check_len(uint32_t len) len, FPGA_MBOX_MSG_DATA_LEN); return 0; err: - return -1; + return FPGA_ERR_AFI_CMD_MALFORMED; } int @@ -145,9 +145,10 @@ fpga_hal_mbox_read_async(pci_bar_handle_t handle, void *msg, uint32_t *len) assert(msg); assert(len); + int ret, ret2; uint32_t val; - int ret = fpga_pci_peek(handle, FMB_REG_STATUS, &val); - fail_on(ret != 0, err, "fpga_pci_peek(status) failed"); + ret = fpga_pci_peek(handle, FMB_REG_STATUS, &val); + fail_on(ret != 0, err_code, "fpga_pci_peek(status) failed"); /** Check if an RX event is available */ if (!(val & FMB_RX_EVT)) { @@ -160,6 +161,9 @@ fpga_hal_mbox_read_async(pci_bar_handle_t handle, void *msg, uint32_t *len) ret = fpga_pci_peek(handle, FMB_REG_RD_LEN, &mb_rd_len); fail_on(ret != 0, err_rx_ack, "fpga_pci_peek(mb_rd_len) failed"); + ret = FPGA_ERR_AFI_CMD_MALFORMED; + fail_on(mb_rd_len > FPGA_MBOX_MSG_DATA_LEN / sizeof(uint32_t), err_rx_ack, + "mb_rd_len is too large"); ret = fpga_hal_mbox_check_len(mb_rd_len << 2); fail_on(ret != 0, err_rx_ack, "fpga_hal_mbox_check_len failed"); @@ -179,7 +183,7 @@ fpga_hal_mbox_read_async(pci_bar_handle_t handle, void *msg, uint32_t *len) /** Acknowledge the RX event */ ret = fpga_pci_poke(handle, FMB_REG_STATUS, FMB_RX_EVT); - fail_on(ret != 0, err, "fpga_pci_poke(status) failed"); + fail_on(ret != 0, err_code, "fpga_pci_poke(status) failed"); *len = mb_rd_len << 2; log_debug("Read len=%u", *len); @@ -189,10 +193,10 @@ fpga_hal_mbox_read_async(pci_bar_handle_t handle, void *msg, uint32_t *len) return -EAGAIN; err_rx_ack: /** Acknowledge the RX event */ - ret = fpga_pci_poke(handle, FMB_REG_STATUS, FMB_RX_EVT); - fail_on(ret != 0, err, "fpga_pci_poke(status) failed"); -err: - return -1; + ret2 = fpga_pci_poke(handle, FMB_REG_STATUS, FMB_RX_EVT); + fail_on(ret2 != 0, err_code, "fpga_pci_poke(status) failed"); +err_code: + return ret; } /** Test and Clear (TC) async write acknowledgement */ @@ -256,7 +260,7 @@ fpga_hal_mbox_write_async(pci_bar_handle_t handle, void *msg, uint32_t len) log_debug("Wrote len=%u", len); return 0; err: - return -1; + return ret; } int @@ -266,25 +270,29 @@ fpga_hal_mbox_read(pci_bar_handle_t handle, void *msg, uint32_t *len) assert(msg); assert(len); + int ret; uint32_t count = priv.mbox.timeout; while (count) { - int ret = fpga_hal_mbox_read_async(handle, msg, len); + ret = fpga_hal_mbox_read_async(handle, msg, len); if (ret == 0) { goto out; } /** Sleep and retry on EAGAIN, otherwise error out of loop */ - fail_on(ret != -EAGAIN, err, "fpga_hal_mbox_read_async failed"); + fail_on(ret != -EAGAIN, err_code, "fpga_hal_mbox_read_async failed"); msleep(priv.mbox.delay_msec); count--; } - fail_on(!count, err, "Timeout on mbox read, timeout=%u, delay_msec=%u", + fail_on(!count, timeout_err, + "Timeout on mbox read, timeout=%u, delay_msec=%u", priv.mbox.timeout, priv.mbox.delay_msec); out: return 0; -err: - return -1; +err_code: + return ret; +timeout_err: + return -ETIMEDOUT; } int @@ -294,13 +302,13 @@ fpga_hal_mbox_write(pci_bar_handle_t handle, void *msg, uint32_t len) assert(msg); int ret = fpga_hal_mbox_write_async(handle, msg, len); - fail_on(ret != 0, err, "fpga_hal_mbox_write_async failed"); + fail_on(ret != 0, err_code, "fpga_hal_mbox_write_async failed"); uint32_t count = priv.mbox.timeout; while (count) { bool ack = false;; ret = fpga_hal_mbox_write_async_tc_ack(handle, &ack); - fail_on(ret != 0, err, "fpga_hal_mbox_write_async_tc_ack failed"); + fail_on(ret != 0, err_code, "fpga_hal_mbox_write_async_tc_ack failed"); if (ack) { goto out; @@ -311,10 +319,12 @@ fpga_hal_mbox_write(pci_bar_handle_t handle, void *msg, uint32_t len) count--; } - fail_on(!count, err, "Timeout on mbox write, timeout=%u, delay_msec=%u", + fail_on(!count, timeout_err, "Timeout on mbox write, timeout=%u, delay_msec=%u", priv.mbox.timeout, priv.mbox.delay_msec); out: return 0; -err: - return -1; +err_code: + return ret; +timeout_err: + return -ETIMEDOUT; } diff --git a/sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt.c b/sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt.c index f68468f3..530b1a3d 100644 --- a/sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt.c +++ b/sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt.c @@ -170,6 +170,97 @@ const char *fpga_mgmt_strerror(int err) return FPGA_ERR2STR(err); } +static const char * long_help_FPGA_ERR_AFI_CMD_BUSY = + "The FPGA is busy with an operation such as a load or a clear.\n"; + +static const char * long_help_FPGA_ERR_AFI_ID_INVALID = + "The agfi id passed is invalid or you do not have permission to load\n" + "the AFI.\n"; + +static const char * long_help_FPGA_ERR_AFI_CMD_API_VERSION_INVALID = + "The FPGA images tools are outdated. Newer tools are available at\n" + "https://github.com/aws/aws-fpga\n"; + +static const char * long_help_FPGA_ERR_CL_ID_MISMATCH = + "The vendor and device ID presented by the CL did not match expected\n" + "values provided at ingestion time.\n"; + +static const char * long_help_FPGA_ERR_CL_DDR_CALIB_FAILED = + "The DDR controllers in the CL did not correctly calibrate DDR.\n"; + +static const char * long_help_FPGA_ERR_SHELL_MISMATCH = + "The requested AFI relies on a shell which is not supported on this\n" + "instance type.\n"; + +static const char * long_help_FPGA_ERR_POWER_VIOLATION = + "The loaded CL exceeded maximum allowed power consumption and was\n" + "automatically disabled. To clear this condition, simply reload the AFI.\n"; + +static const char * long_help_FPGA_ERR_PCI_MISSING = + "Unable to locate a PCI device or resource for communicating with the\n" + "FPGA API. This can happen if the FPGA has stopped behaving correctly\n" + "and the instance will need to be stopped and restarted. This can also\n" + "happen if the tools are run on a system with no AWS FPGA attached.\n"; + +static const char * long_help_ETIMEDOUT = + "A time out error is usually spurious and the request can be retried. If\n" + "it continues to fail, the FPGA may be inaccessible or the the FPGA API\n" + "may be unresponsive.\n"; + +static const char * long_help_FPGA_ERR_AFI_CMD_MALFORMED = + "A malformed response from the FPGA API can indicate that the FPGA has\n" + "stopped behaving correctly and the instance will need to be stopped and\n" + "and restarted. If this continues to happen (after an instance restart),\n" + "this may be an indication that your AFI is exceeding allowed power\n" + "consumption limits.\n"; + +static const char * long_help_FPGA_ERR_SOFTWARE_PROBLEM = + "This usually indicates a bug in the fpga image tools, but can also be a\n" + "symptom of a bug in the code which is using the library in cases where\n" + "the customer is using the library directly.\n"; + +static const char * long_help_FPGA_ERR_UNRESPONSIVE = + "The FPGA or PCI subsytem is not responding. This can happen if the FPGA\n" + "stopped behaving correctly and the instance will need to be stopped and\n" + "restarted.\n"; + + +const char *fpga_mgmt_strerror_long(int err) +{ + switch (err) { + default: + case FPGA_ERR_FAIL: + case FPGA_ERR_OK: + return NULL; + + case FPGA_ERR_AFI_CMD_BUSY: + return long_help_FPGA_ERR_AFI_CMD_BUSY; + case FPGA_ERR_AFI_ID_INVALID: + return long_help_FPGA_ERR_AFI_ID_INVALID; + case FPGA_ERR_AFI_CMD_API_VERSION_INVALID: + return long_help_FPGA_ERR_AFI_CMD_API_VERSION_INVALID; + case FPGA_ERR_CL_ID_MISMATCH: + return long_help_FPGA_ERR_CL_ID_MISMATCH; + case FPGA_ERR_CL_DDR_CALIB_FAILED: + return long_help_FPGA_ERR_CL_DDR_CALIB_FAILED; + case FPGA_ERR_SHELL_MISMATCH: + return long_help_FPGA_ERR_SHELL_MISMATCH; + case FPGA_ERR_POWER_VIOLATION: + return long_help_FPGA_ERR_POWER_VIOLATION; + case FPGA_ERR_PCI_MISSING: + return long_help_FPGA_ERR_PCI_MISSING; + case FPGA_ERR_AFI_CMD_MALFORMED: + return long_help_FPGA_ERR_AFI_CMD_MALFORMED; + case -EINVAL: + case FPGA_ERR_SOFTWARE_PROBLEM: + return long_help_FPGA_ERR_SOFTWARE_PROBLEM; + case FPGA_ERR_UNRESPONSIVE: + return long_help_FPGA_ERR_UNRESPONSIVE; + case -ETIMEDOUT: + return long_help_ETIMEDOUT; + } +} + int fpga_mgmt_clear_local_image(int slot_id) { int ret; diff --git a/sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt_cmd.c b/sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt_cmd.c index b7c4edf4..54e9b175 100644 --- a/sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt_cmd.c +++ b/sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt_cmd.c @@ -69,7 +69,7 @@ afi_cmd_hdr_set_len(union afi_cmd *cmd, size_t len) { /* Null pointer or overflow? */ if (!cmd || (len & ~AFI_CMD_HDR_LEN_MASK)) { - return FPGA_ERR_FAIL; + return FPGA_ERR_SOFTWARE_PROBLEM; } cmd->hdr.len_flags &= ~AFI_CMD_HDR_LEN_MASK; @@ -92,7 +92,7 @@ afi_cmd_hdr_set_flags(union afi_cmd *cmd, unsigned int flags) { /* Null pointer or overflow? */ if (!cmd || (flags & ~AFI_CMD_HDR_ALL_FLAGS)) { - return FPGA_ERR_FAIL; + return FPGA_ERR_SOFTWARE_PROBLEM; } cmd->hdr.len_flags &= AFI_CMD_HDR_LEN_MASK; @@ -238,7 +238,7 @@ fpga_mgmt_cmd_handle_metrics(const union afi_cmd *rsp, uint32_t len, return 0; err: - return FPGA_ERR_FAIL; + return FPGA_ERR_AFI_CMD_MALFORMED; } @@ -271,7 +271,7 @@ fpga_mgmt_mbox_attach(int slot_id) return 0; err: - return FPGA_ERR_FAIL; + return ret; } int @@ -341,7 +341,7 @@ fpga_mgmt_handle_afi_cmd_error_rsp(const union afi_cmd *rsp, uint32_t len) return err_rsp->error; err: - return FPGA_ERR_FAIL; + return FPGA_ERR_AFI_CMD_MALFORMED; } /** @@ -362,8 +362,8 @@ fpga_mgmt_afi_validate_header(const union afi_cmd *cmd, uint32_t is_response = stored_flags & AFI_CMD_HDR_IS_RSP; uint32_t payload_len = afi_cmd_hdr_get_len(rsp); - fail_on(!cmd, err, "cmd == NULL"); - fail_on(!rsp, err, "rsp == NULL"); + fail_on(!cmd, assertion_err, "cmd == NULL"); + fail_on(!rsp, assertion_err, "rsp == NULL"); /** Version */ fail_on(MAJOR_VERSION(cmd->hdr.version) != MAJOR_VERSION(rsp->hdr.version), err, @@ -399,7 +399,9 @@ fpga_mgmt_afi_validate_header(const union afi_cmd *cmd, id_err: return -EAGAIN; err: - return FPGA_ERR_FAIL; + return FPGA_ERR_AFI_CMD_MALFORMED; +assertion_err: + return FPGA_ERR_SOFTWARE_PROBLEM; } static int @@ -411,7 +413,7 @@ fpga_mgmt_send_cmd(int slot_id, /** Write the AFI cmd to the mailbox */ pci_bar_handle_t handle = fpga_mgmt_state.slots[slot_id].handle; ret = fpga_hal_mbox_write(handle, (void *)cmd, *len); - fail_on(ret != 0, err, "fpga_hal_mbox_write failed"); + fail_on(ret != 0, err_code, "fpga_hal_mbox_write failed"); /** * Read the AFI rsp from the mailbox. @@ -422,7 +424,7 @@ fpga_mgmt_send_cmd(int slot_id, bool done = false; while (!done) { ret = fpga_hal_mbox_read(handle, (void *)rsp, len); - fail_on(ret = (ret) ? -ETIMEDOUT : 0, err_code, "Error: operation timed out"); + fail_on(ret, err_code, "fpga_hal_mbox_read failed with code: %d", ret); ret = fpga_mgmt_afi_validate_header(cmd, rsp, *len); if (ret == 0) { @@ -430,15 +432,15 @@ fpga_mgmt_send_cmd(int slot_id, } else { fail_on(ret != -EAGAIN, err_code, "fpga_mgmt_afi_validate_header failed"); - fail_on(retries >= AFI_MAX_RETRIES, err, "retries=%u, exceeded", + fail_on(retries >= AFI_MAX_RETRIES, timeout_err, "retries=%u, exceeded", retries); retries++; } } return 0; -err: - return FPGA_ERR_FAIL; +timeout_err: + return -ETIMEDOUT; err_code: return ret; } diff --git a/sdk/userspace/fpga_libs/fpga_pci/fpga_pci.c b/sdk/userspace/fpga_libs/fpga_pci/fpga_pci.c index 747312bf..9202e8d6 100644 --- a/sdk/userspace/fpga_libs/fpga_pci/fpga_pci.c +++ b/sdk/userspace/fpga_libs/fpga_pci/fpga_pci.c @@ -68,7 +68,7 @@ fpga_pci_bar_set_mem_base_size(pci_bar_handle_t handle, void *mem_base, size_t m return 0; err: - return FPGA_ERR_FAIL; + return -EINVAL; } static inline void * @@ -112,7 +112,7 @@ fpga_pci_bar_alloc(void) pthread_mutex_unlock(&bars_mutex); - return FPGA_ERR_FAIL; + return -ENOMEM; } static int @@ -131,7 +131,7 @@ fpga_pci_bar_free(pci_bar_handle_t handle) return 0; err: - return FPGA_ERR_FAIL; + return -EINVAL; } static int @@ -142,7 +142,7 @@ fpga_pci_check_file_id(char *path, uint16_t id) int ret = 0; FILE *fp = fopen(path, "r"); - fail_on(!fp, err, "Error opening %s", path); + fail_on(!fp, err_open, "Error opening %s", path); uint32_t tmp_id; ret = fscanf(fp, "%x", &tmp_id); @@ -157,7 +157,9 @@ fpga_pci_check_file_id(char *path, uint16_t id) err_close: fclose(fp); err: - return FPGA_ERR_FAIL; + return -EINVAL; +err_open: + return -errno; } static int @@ -165,12 +167,15 @@ fpga_pci_bar_attach(struct fpga_slot_spec *spec, int pf_id, int bar_id, bool write_combining, int *handle) { int fd = -1; + int ret = 0; log_debug("enter"); void *mem_base = NULL; - fail_on(!spec, err, "spec is NULL"); - fail_on(!handle, err, "handle is NULL"); + fail_on_with_code(!spec, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "spec is NULL"); + fail_on_with_code(!handle, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "handle is NULL"); struct fpga_pci_resource_map *map = &spec->map[pf_id]; @@ -185,15 +190,17 @@ fpga_pci_bar_attach(struct fpga_slot_spec *spec, int pf_id, int bar_id, /** Sanity check the vendor */ char sysfs_name[NAME_MAX + 1]; - int ret = snprintf(sysfs_name, sizeof(sysfs_name), - "/sys/bus/pci/devices/" PCI_DEV_FMT "/vendor", + ret = snprintf(sysfs_name, sizeof(sysfs_name), + "/sys/bus/pci/devices/" PCI_DEV_FMT "/vendor", map->domain, map->bus, map->dev, map->func); - fail_on(ret < 0, err, "Error building the sysfs path for vendor"); - fail_on((size_t) ret >= sizeof(sysfs_name), err, "sysfs path too long for vendor"); + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "Error building the sysfs path for vendor"); + fail_on_with_code((size_t) ret >= sizeof(sysfs_name), err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "sysfs path too long for vendor"); ret = fpga_pci_check_file_id(sysfs_name, map->vendor_id); - fail_on(ret != 0, err, + fail_on_with_code(ret != 0, err, ret, FPGA_ERR_PCI_MISSING, "fpga_pci_check_file_id failed, sysfs_name=%s, vendor_id=0x%04x", sysfs_name, map->vendor_id); @@ -202,14 +209,15 @@ fpga_pci_bar_attach(struct fpga_slot_spec *spec, int pf_id, int bar_id, "/sys/bus/pci/devices/" PCI_DEV_FMT "/device", map->domain, map->bus, map->dev, map->func); - fail_on(ret < 0, err, "Error building the sysfs path for device"); - fail_on((size_t) ret >= sizeof(sysfs_name), err, - "sysfs path too long for device"); + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "Error building the sysfs path for device"); + fail_on_with_code((size_t) ret >= sizeof(sysfs_name), err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "sysfs path too long for device"); ret = fpga_pci_check_file_id(sysfs_name, map->device_id); - fail_on(ret != 0, err, - "fpga_pci_check_file_id failed, sysfs_name=%s, device_id=0x%04x", - sysfs_name, map->device_id); + fail_on_with_code(ret != 0, err, ret, FPGA_ERR_PCI_MISSING, + "fpga_pci_check_file_id failed, sysfs_name=%s, device_id=0x%04x", + sysfs_name, map->device_id); char wc_suffix[4] = "\0"; if (map->resource_burstable[bar_id] && write_combining) { @@ -224,23 +232,27 @@ fpga_pci_bar_attach(struct fpga_slot_spec *spec, int pf_id, int bar_id, "/sys/bus/pci/devices/" PCI_DEV_FMT "/resource%u%s", map->domain, map->bus, map->dev, map->func, bar_id, wc_suffix); - fail_on(ret < 0, err, "Error building the sysfs path for resource"); - fail_on((size_t) ret >= sizeof(sysfs_name), err, "sysfs path too long for resource"); + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "Error building the sysfs path for resource"); + fail_on_with_code((size_t) ret >= sizeof(sysfs_name), err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "sysfs path too long for resource"); log_debug("Opening sysfs_name=%s", sysfs_name); fd = open(sysfs_name, O_RDWR | O_SYNC); - fail_on(fd == -1, err, "open failed"); + fail_on_with_code(fd == -1, err, ret, FPGA_ERR_UNRESPONSIVE, "open failed"); mem_base = mmap(0, map->resource_size[bar_id], PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); - fail_on(mem_base == MAP_FAILED, err, "mmap failed"); + fail_on_with_code(mem_base == MAP_FAILED, err, ret, FPGA_ERR_UNRESPONSIVE, + "mmap failed"); close(fd); fd = -1; /** Allocate a bar */ int tmp_handle = fpga_pci_bar_alloc(); - fail_on(tmp_handle < 0, err_unmap, "fpga_pci_bar_alloc failed"); + fail_on_with_code(tmp_handle < 0, err_unmap, ret, -ENOMEM, + "fpga_pci_bar_alloc failed"); /** Set the bar's mem base and size */ ret = fpga_pci_bar_set_mem_base_size(tmp_handle, mem_base, @@ -261,7 +273,7 @@ fpga_pci_bar_attach(struct fpga_slot_spec *spec, int pf_id, int bar_id, close(fd); } errno = 0; - return FPGA_ERR_FAIL; + return ret; } int @@ -292,7 +304,7 @@ fpga_pci_attach(int slot_id, int pf_id, int bar_id, uint32_t flags, write_combining = false; if (flags & BURST_CAPABLE) { - ret = (spec.map[pf_id].resource_burstable[bar_id]) ? 0 : FPGA_ERR_FAIL; + ret = (spec.map[pf_id].resource_burstable[bar_id]) ? 0 : -EINVAL; fail_on(ret, err, "bar is not BURST_CAPABLE (does not support write " "combining.)"); write_combining = true; @@ -318,7 +330,7 @@ fpga_pci_detach(pci_bar_handle_t handle) { return 0; err: errno = 0; - return FPGA_ERR_FAIL; + return -EINVAL; } int @@ -334,7 +346,7 @@ fpga_pci_poke(pci_bar_handle_t handle, uint64_t offset, uint32_t value) { return 0; err: - return FPGA_ERR_FAIL; + return -EINVAL; } int @@ -350,7 +362,7 @@ fpga_pci_poke8(pci_bar_handle_t handle, uint64_t offset, uint8_t value) { return 0; err: - return FPGA_ERR_FAIL; + return -EINVAL; } int @@ -366,7 +378,7 @@ fpga_pci_poke64(pci_bar_handle_t handle, uint64_t offset, uint64_t value) { return 0; err: - return FPGA_ERR_FAIL; + return -EINVAL; } int @@ -383,7 +395,7 @@ fpga_pci_peek(pci_bar_handle_t handle, uint64_t offset, uint32_t *value) { handle, offset, *value); return 0; err: - return FPGA_ERR_FAIL; + return -EINVAL; } int @@ -400,7 +412,7 @@ fpga_pci_peek8(pci_bar_handle_t handle, uint64_t offset, uint8_t *value) { handle, offset, *value); return 0; err: - return FPGA_ERR_FAIL; + return -EINVAL; } int @@ -417,7 +429,7 @@ fpga_pci_peek64(pci_bar_handle_t handle, uint64_t offset, uint64_t *value) { handle, offset, *value); return 0; err: - return FPGA_ERR_FAIL; + return -EINVAL; } int fpga_pci_write_burst(pci_bar_handle_t handle, uint64_t offset, uint32_t* datap, uint64_t dword_len) { @@ -436,7 +448,7 @@ int fpga_pci_write_burst(pci_bar_handle_t handle, uint64_t offset, uint32_t* dat return 0; err: - return FPGA_ERR_FAIL; + return -EINVAL; } int @@ -449,7 +461,7 @@ fpga_pci_get_address(pci_bar_handle_t handle, uint64_t offset, size_t len, fail_on(!*ptr, err, "fpga_plat_get_mem_at_offset failed"); return 0; err: - return FPGA_ERR_FAIL; + return -EINVAL; } int @@ -471,5 +483,5 @@ fpga_pci_memset(pci_bar_handle_t handle, uint64_t offset, uint32_t value, return 0; err: - return FPGA_ERR_FAIL; + return -EINVAL; } diff --git a/sdk/userspace/fpga_libs/fpga_pci/fpga_pci_sysfs.c b/sdk/userspace/fpga_libs/fpga_pci/fpga_pci_sysfs.c index fa4c75b6..95808c3a 100644 --- a/sdk/userspace/fpga_libs/fpga_pci/fpga_pci_sysfs.c +++ b/sdk/userspace/fpga_libs/fpga_pci/fpga_pci_sysfs.c @@ -47,12 +47,13 @@ static int fpga_pci_check_app_pf_sysfs(char *dir_name, bool exists); static int fpga_pci_get_id(char *path, uint16_t *id) { - fail_on(!path, err, "path is NULL"); - fail_on(!id, err, "id is NULL"); - int ret = 0; + + fail_on_with_code(!path, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, "path is NULL"); + fail_on_with_code(!id, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, "id is NULL"); + FILE *fp = fopen(path, "r"); - fail_on_quiet(!fp, err, "Error opening %s", path); + fail_on_quiet((ret = (!fp) ? -errno: 0), err, "Error opening %s", path); uint32_t tmp_id; ret = fscanf(fp, "%x", &tmp_id); @@ -65,9 +66,10 @@ fpga_pci_get_id(char *path, uint16_t *id) err_close: fclose(fp); + ret = FPGA_ERR_UNRESPONSIVE; /* couldn't parse the id */ err: errno = 0; - return FPGA_ERR_FAIL; + return ret; } /** @@ -112,23 +114,26 @@ fpga_pci_write_one2file(char *path) static int fpga_pci_get_dbdf(char *dir_name, struct fpga_pci_resource_map *map) { - fail_on(!dir_name, err, "dir_name is NULL"); - fail_on(!map, err, "map is NULL"); + int ret = 0; + fail_on_with_code(!dir_name, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "dir_name is NULL"); + fail_on_with_code(!map, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, "map is NULL"); uint32_t domain; uint32_t bus; uint32_t dev; int func; - int ret = sscanf(dir_name, PCI_DEV_FMT, &domain, &bus, &dev, &func); - fail_on(ret != 4, err, "sscanf failed for DBDF"); + ret = sscanf(dir_name, PCI_DEV_FMT, &domain, &bus, &dev, &func); + fail_on_with_code(ret != 4, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "sscanf failed for DBDF"); map->domain = domain; map->bus = bus; map->dev = dev; map->func = func; - return 0; + ret = 0; err: - return FPGA_ERR_FAIL; + return ret; } /** @@ -148,25 +153,33 @@ static int fpga_pci_get_pci_resource_info(char *dir_name, uint8_t resource_num, uint64_t *resource_size, bool *burstable) { - int ret; + int ret, err_rc; - fail_on(!dir_name, err, "dir_name is NULL"); - fail_on(!resource_size, err, "resource_size is NULL"); + err_rc = 0; + + fail_on_with_code(!dir_name, err, err_rc, FPGA_ERR_SOFTWARE_PROBLEM, + "dir_name is NULL"); + fail_on_with_code(!resource_size, err, err_rc, FPGA_ERR_SOFTWARE_PROBLEM, + "resource_size is NULL"); + fail_on_with_code(!burstable, err, err_rc, FPGA_ERR_SOFTWARE_PROBLEM, + "burstable is NULL"); char sysfs_name[NAME_MAX + 1]; ret = snprintf(sysfs_name, sizeof(sysfs_name), "/sys/bus/pci/devices/%s/resource%u", dir_name, resource_num); - fail_on(ret < 0, err, "Error building the sysfs path for resource%u", - resource_num); - fail_on((size_t) ret >= sizeof(sysfs_name), err, - "sysfs path too long for resource%u", resource_num); + fail_on_with_code(ret < 0, err, err_rc, FPGA_ERR_SOFTWARE_PROBLEM, + "Error building the sysfs path for resource%u", resource_num); + fail_on_with_code((size_t) ret >= sizeof(sysfs_name), err, err_rc, + FPGA_ERR_SOFTWARE_PROBLEM, + "sysfs path too long for resource%u", resource_num); /** Check for file existence, obtain the file size */ struct stat file_stat; ret = stat(sysfs_name, &file_stat); - fail_on_quiet(ret != 0, err, "stat failed, path=%s", sysfs_name); + fail_on_quiet(err_rc = (ret != 0) ? FPGA_ERR_PCI_MISSING : 0, err, + "stat failed, path=%s", sysfs_name); *resource_size = file_stat.st_size; @@ -174,20 +187,19 @@ fpga_pci_get_pci_resource_info(char *dir_name, "/sys/bus/pci/devices/%s/resource%u_wc", dir_name, resource_num); - fail_on(ret < 0, err, "Error building the sysfs path for resource%u", - resource_num); - fail_on((size_t) ret >= sizeof(sysfs_name), err, - "sysfs path too long for resource%u", resource_num); + fail_on_with_code(ret < 0, err, err_rc, FPGA_ERR_SOFTWARE_PROBLEM, + "Error building the sysfs path for resource%u", resource_num); + fail_on_with_code((size_t) ret >= sizeof(sysfs_name), err, err_rc, + FPGA_ERR_SOFTWARE_PROBLEM, + "sysfs path too long for resource%u", resource_num); memset(&file_stat, 0, sizeof(struct stat)); ret = stat(sysfs_name, &file_stat); *burstable = (ret == 0); - errno = 0; - return 0; err: errno = 0; - return FPGA_ERR_FAIL; + return err_rc; } /** @@ -204,6 +216,7 @@ static int fpga_pci_get_resources(char *dir_name, struct fpga_pci_resource_map *map) { int ret; + bool found_one_device = false; static const uint8_t resource_nums[4] = {0, 1, 2, 4}; for (unsigned int i = 0; i < sizeof_array(resource_nums); ++i) { @@ -216,13 +229,17 @@ fpga_pci_get_resources(char *dir_name, struct fpga_pci_resource_map *map) ret = fpga_pci_get_pci_resource_info(dir_name, resource_num, &resource_size, &burstable); - if (ret) { + if (ret == FPGA_ERR_PCI_MISSING) { log_debug("Unable to read resource information for %d", resource_num); + } else if (ret != 0) { + return ret; + } else { + map->resource_size[resource_num] = resource_size; + map->resource_burstable[resource_num] = burstable; + found_one_device = true; } - map->resource_size[resource_num] = resource_size; - map->resource_burstable[resource_num] = burstable; } - return 0; + return (found_one_device) ? 0 : FPGA_ERR_PCI_MISSING; } @@ -239,20 +256,24 @@ fpga_pci_get_resources(char *dir_name, struct fpga_pci_resource_map *map) static int fpga_pci_get_resource_map_ids(char *dir_name, struct fpga_pci_resource_map *map) { + int ret = 0; uint16_t vendor_id = 0; uint16_t device_id = 0; uint16_t subsystem_vendor_id = 0; uint16_t subsystem_device_id = 0; - fail_on(!dir_name, err, "dir_name is NULL"); + fail_on_with_code(!dir_name, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "dir_name is NULL"); /** Setup and read the PCI Vendor ID */ char sysfs_name[NAME_MAX + 1]; - int ret = snprintf(sysfs_name, sizeof(sysfs_name), + ret = snprintf(sysfs_name, sizeof(sysfs_name), "/sys/bus/pci/devices/%s/vendor", dir_name); - fail_on(ret < 0, err, "Error building the sysfs path for vendor"); - fail_on((size_t) ret >= sizeof(sysfs_name), err, "sysfs path too long for vendor"); + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "Error building the sysfs path for vendor"); + fail_on_with_code((size_t) ret >= sizeof(sysfs_name), err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "sysfs path too long for vendor"); ret = fpga_pci_get_id(sysfs_name, &vendor_id); fail_on_quiet(ret != 0, err, "Error retrieving vendor_id"); @@ -261,8 +282,10 @@ fpga_pci_get_resource_map_ids(char *dir_name, struct fpga_pci_resource_map *map) ret = snprintf(sysfs_name, sizeof(sysfs_name), "/sys/bus/pci/devices/%s/device", dir_name); - fail_on(ret < 0, err, "Error building the sysfs path for device"); - fail_on((size_t) ret >= sizeof(sysfs_name), err, "sysfs path too long for device"); + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "Error building the sysfs path for device"); + fail_on_with_code((size_t) ret >= sizeof(sysfs_name), err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "sysfs path too long for device"); ret = fpga_pci_get_id(sysfs_name, &device_id); fail_on_quiet(ret != 0, err, "Error retrieving device_id"); @@ -271,8 +294,10 @@ fpga_pci_get_resource_map_ids(char *dir_name, struct fpga_pci_resource_map *map) ret = snprintf(sysfs_name, sizeof(sysfs_name), "/sys/bus/pci/devices/%s/subsystem_vendor", dir_name); - fail_on(ret < 0, err, "Error building the sysfs path for subsystem_vendor"); - fail_on((size_t) ret >= sizeof(sysfs_name), err, "sysfs path too long for subsystem_vendor"); + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "Error building the sysfs path for subsystem_vendor"); + fail_on_with_code((size_t) ret >= sizeof(sysfs_name), err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "sysfs path too long for subsystem_vendor"); ret = fpga_pci_get_id(sysfs_name, &subsystem_vendor_id); fail_on_quiet(ret != 0, err, "Error retrieving subsystem_vendor"); @@ -281,8 +306,10 @@ fpga_pci_get_resource_map_ids(char *dir_name, struct fpga_pci_resource_map *map) ret = snprintf(sysfs_name, sizeof(sysfs_name), "/sys/bus/pci/devices/%s/subsystem_device", dir_name); - fail_on(ret < 0, err, "Error building the sysfs path for subsystem_device"); - fail_on((size_t) ret >= sizeof(sysfs_name), err, "sysfs path too long for subsystem_device"); + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "Error building the sysfs path for subsystem_device"); + fail_on_with_code((size_t) ret >= sizeof(sysfs_name), err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "sysfs path too long for subsystem_device"); ret = fpga_pci_get_id(sysfs_name, &subsystem_device_id); fail_on_quiet(ret != 0, err, "Error retrieving subsystem_device"); @@ -298,9 +325,9 @@ fpga_pci_get_resource_map_ids(char *dir_name, struct fpga_pci_resource_map *map) map->subsystem_vendor_id = subsystem_vendor_id; map->subsystem_device_id = subsystem_device_id; - return 0; + ret = 0; err: - return FPGA_ERR_FAIL; + return ret; } /** @@ -322,16 +349,20 @@ fpga_pci_mbox2app(struct fpga_pci_resource_map *mbox_map, struct fpga_pci_resource_map *app_map, char *app_dir_name, size_t app_dir_name_size) { - fail_on(!mbox_map || !app_map || !app_dir_name || !app_dir_name_size, - err, "Invalid input parameters"); + int ret = 0; + + fail_on_with_code(!mbox_map || !app_map || !app_dir_name || !app_dir_name_size, + err, ret, FPGA_ERR_SOFTWARE_PROBLEM, "Invalid input parameters"); /** Construct the app dir name based on the mbox_map */ - int ret = snprintf(app_dir_name, app_dir_name_size, PCI_DEV_FMT, + ret = snprintf(app_dir_name, app_dir_name_size, PCI_DEV_FMT, mbox_map->domain, mbox_map->bus, F1_MBOX_DEV2APP_DEV(mbox_map->dev), mbox_map->func); - fail_on(ret < 0, err, "Error building the app_dir_name"); - fail_on((size_t) ret >= app_dir_name_size, err, "app_dir_name too long"); + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "Error building the app_dir_name"); + fail_on_with_code((size_t) ret >= app_dir_name_size, err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "app_dir_name too long"); /** * Check that the app_pf exists. If not found, make a minimal attempt to @@ -352,7 +383,8 @@ fpga_pci_mbox2app(struct fpga_pci_resource_map *mbox_map, if (ret == 0) { done = true; } else { - fail_on(retries >= F1_CHECK_APP_PF_MAX_RETRIES, err, + fail_on_with_code(retries >= F1_CHECK_APP_PF_MAX_RETRIES, err, ret, + FPGA_ERR_UNRESPONSIVE, "fpga_pci_get_resource_map_ids failed for app_dir_name=%s", app_dir_name); msleep(F1_CHECK_APP_PF_DELAY_MSEC); @@ -360,34 +392,26 @@ fpga_pci_mbox2app(struct fpga_pci_resource_map *mbox_map, } } - return 0; + ret = 0; err: - return FPGA_ERR_FAIL; + return ret; } -/** - * Glibc 2.19 and lower support readdir_r, a reentrant version of readdir. - * Newer versions of glibc deprecate readdir_r and therefore require external - * synchronization on readdir. - */ -#if defined(_BSD_SOURCE) || defined(_SVID_SOURCE) -# define USE_READDIR_R -#endif - -#if !defined(USE_READDIR_R) +#if !defined(FPGA_PCI_USE_READDIR_R) pthread_mutex_t fpga_pci_readdir_mutex = PTHREAD_MUTEX_INITIALIZER; #endif int fpga_pci_get_all_slot_specs(struct fpga_slot_spec spec_array[], int size) { + int ret; bool found_afi_slot = false; char *path = "/sys/bus/pci/devices"; DIR *dirp = opendir(path); fail_on(!dirp, err, "opendir failed for path=%s", path); struct dirent *entry; -#if defined(USE_READDIR_R) +#if defined(FPGA_PCI_USE_READDIR_R) struct dirent entry_stack, *result; entry = &entry_stack; memset(entry, 0, sizeof(struct dirent)); @@ -418,7 +442,7 @@ fpga_pci_get_all_slot_specs(struct fpga_slot_spec spec_array[], int size) */ while (true) { -#if defined(USE_READDIR_R) +#if defined(FPGA_PCI_USE_READDIR_R) memset(entry, 0, sizeof(struct dirent)); readdir_r(dirp, entry, &result); if (result == NULL) { @@ -435,7 +459,7 @@ fpga_pci_get_all_slot_specs(struct fpga_slot_spec spec_array[], int size) /** Handle the current directory entry */ memset(&search_map, 0, sizeof(struct fpga_pci_resource_map)); - int ret = fpga_pci_get_resource_map_ids(entry->d_name, &search_map); + ret = fpga_pci_get_resource_map_ids(entry->d_name, &search_map); if (ret != 0) { continue; } @@ -467,10 +491,11 @@ fpga_pci_get_all_slot_specs(struct fpga_slot_spec spec_array[], int size) } } } -#if !defined(USE_READDIR_R) +#if !defined(FPGA_PCI_USE_READDIR_R) pthread_mutex_unlock(&fpga_pci_readdir_mutex); #endif - fail_on(!found_afi_slot, err, "No fpga-image-slots found"); + fail_on_with_code(!found_afi_slot, err, ret, FPGA_ERR_PCI_MISSING, + "No fpga-image-slots found"); closedir(dirp); @@ -478,7 +503,7 @@ fpga_pci_get_all_slot_specs(struct fpga_slot_spec spec_array[], int size) return 0; err_unlock: -#if !defined(USE_READDIR_R) +#if !defined(FPGA_PCI_USE_READDIR_R) pthread_mutex_unlock(&fpga_pci_readdir_mutex); #endif @@ -487,7 +512,7 @@ fpga_pci_get_all_slot_specs(struct fpga_slot_spec spec_array[], int size) closedir(dirp); } errno = 0; - return FPGA_ERR_FAIL; + return ret; } int @@ -516,7 +541,7 @@ fpga_pci_get_slot_spec(int slot_id, struct fpga_slot_spec *spec) *spec = spec_array[slot_id]; return 0; err: - return FPGA_ERR_FAIL; + return ret; } int @@ -555,26 +580,32 @@ static int fpga_pci_check_app_pf_driver(struct fpga_pci_resource_map *app_map, bool *attached) { - fail_on(!app_map, err, "app_map is NULL"); - fail_on(!attached, err, "attached is NULL"); + int ret = 0; + + fail_on_with_code(!app_map, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "app_map is NULL"); + fail_on_with_code(!attached, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "attached is NULL"); /** Construct the PCI device directory name using the PCI_DEV_FMT */ char dir_name[NAME_MAX + 1]; - int ret = snprintf(dir_name, sizeof(dir_name), PCI_DEV_FMT, + ret = snprintf(dir_name, sizeof(dir_name), PCI_DEV_FMT, app_map->domain, app_map->bus, app_map->dev, app_map->func); - fail_on(ret < 0, err, "Error building the dir_name"); - fail_on((size_t) ret >= sizeof(dir_name), err, "dir_name too long"); + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "Error building the dir_name"); + fail_on_with_code((size_t) ret >= sizeof(dir_name), err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "dir_name too long"); /** Setup the path to the app_pf */ char sysfs_name[NAME_MAX + 1]; ret = snprintf(sysfs_name, sizeof(sysfs_name), "/sys/bus/pci/devices/%s/driver", dir_name); - fail_on(ret < 0, err, + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, "Error building the sysfs path for app_pf"); - fail_on((size_t) ret >= sizeof(sysfs_name), err, - "sysfs path too long for app_pf"); + fail_on_with_code((size_t) ret >= sizeof(sysfs_name), err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "sysfs path too long for app_pf"); log_debug("Checking path=%s for existence", sysfs_name); @@ -585,11 +616,10 @@ fpga_pci_check_app_pf_driver(struct fpga_pci_resource_map *app_map, /** Setup for return */ *attached = (ret == 0) ? true : false; - errno = 0; - return 0; + ret = 0; err: errno = 0; - return FPGA_ERR_FAIL; + return ret; } /** @@ -606,17 +636,19 @@ fpga_pci_check_app_pf_driver(struct fpga_pci_resource_map *app_map, static int fpga_pci_check_app_pf_sysfs(char *dir_name, bool exists) { + int ret = 0; + fail_on(!dir_name, err, "dir_name is NULL"); /** Setup the path to the app_pf */ char sysfs_name[NAME_MAX + 1]; - int ret = snprintf(sysfs_name, sizeof(sysfs_name), + ret = snprintf(sysfs_name, sizeof(sysfs_name), "/sys/bus/pci/devices/%s", dir_name); - fail_on(ret < 0, err, + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, "Error building the sysfs path for app_pf"); - fail_on((size_t) ret >= sizeof(sysfs_name), err, - "sysfs path too long for app_pf"); + fail_on_with_code((size_t) ret >= sizeof(sysfs_name), err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "sysfs path too long for app_pf"); bool done = false; uint32_t retries = 0; @@ -627,8 +659,9 @@ fpga_pci_check_app_pf_sysfs(char *dir_name, bool exists) if (!!ret == !exists) { done = true; } else { - fail_on(retries >= F1_CHECK_APP_PF_MAX_RETRIES, err, - "exists=%u, failed for path=%s", exists, sysfs_name); + fail_on_with_code(retries >= F1_CHECK_APP_PF_MAX_RETRIES, err, + ret, FPGA_ERR_UNRESPONSIVE, "exists=%u, failed for path=%s", exists, + sysfs_name); if (exists) { ret = fpga_pci_rescan(); fail_on(ret, err, "fpga_pci_rescan failed"); @@ -637,11 +670,11 @@ fpga_pci_check_app_pf_sysfs(char *dir_name, bool exists) retries++; } } - errno = 0; - return 0; + + ret = 0; err: errno = 0; - return FPGA_ERR_FAIL; + return ret; } /** @@ -658,11 +691,14 @@ fpga_pci_check_app_pf_sysfs(char *dir_name, bool exists) static int fpga_pci_check_app_pf(struct fpga_pci_resource_map *app_map, bool exists) { - fail_on(!app_map, err, "app_map is NULL"); + int ret = 0; + + fail_on_with_code(!app_map, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "app_map is NULL"); /** Construct the PCI device directory name using the PCI_DEV_FMT */ char dir_name[NAME_MAX + 1]; - int ret = snprintf(dir_name, sizeof(dir_name), PCI_DEV_FMT, + ret = snprintf(dir_name, sizeof(dir_name), PCI_DEV_FMT, app_map->domain, app_map->bus, app_map->dev, app_map->func); fail_on(ret < 0, err, "Error building the dir_name"); @@ -671,9 +707,9 @@ fpga_pci_check_app_pf(struct fpga_pci_resource_map *app_map, bool exists) ret = fpga_pci_check_app_pf_sysfs(dir_name, exists); fail_on(ret != 0, err, "fpga_check_app_pf_sysfs failed"); - return 0; + ret = 0; err: - return FPGA_ERR_FAIL; + return ret; } /** @@ -687,30 +723,35 @@ fpga_pci_check_app_pf(struct fpga_pci_resource_map *app_map, bool exists) static int fpga_pci_remove_app_pf(struct fpga_pci_resource_map *app_map) { - fail_on(!app_map, err, "app_map is NULL"); + int ret = 0; + fail_on_with_code(!app_map, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "app_map is NULL"); /** Construct the PCI device directory name using the PCI_DEV_FMT */ char dir_name[NAME_MAX + 1]; - int ret = snprintf(dir_name, sizeof(dir_name), PCI_DEV_FMT, + ret = snprintf(dir_name, sizeof(dir_name), PCI_DEV_FMT, app_map->domain, app_map->bus, app_map->dev, app_map->func); - fail_on(ret < 0, err, "Error building the dir_name"); - fail_on((size_t) ret >= sizeof(dir_name), err, "dir_name too long"); + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "Error building the dir_name"); + fail_on_with_code((size_t) ret >= sizeof(dir_name), err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "dir_name too long"); /** Setup the path to the device's remove file */ char sysfs_name[NAME_MAX + 1]; ret = snprintf(sysfs_name, sizeof(sysfs_name), "/sys/bus/pci/devices/%s/remove", dir_name); - fail_on(ret < 0, err, + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, "Error building the sysfs path for remove file"); - fail_on((size_t) ret >= sizeof(sysfs_name), err, - "sysfs path too long for remove file"); + fail_on_with_code((size_t) ret >= sizeof(sysfs_name), err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "sysfs path too long for remove file"); /** Write a "1" to the device's remove file */ ret = fpga_pci_write_one2file(sysfs_name); - fail_on(ret != 0, err, "cli_write_one2file failed"); - + fail_on_with_code(ret != 0, err, ret, FPGA_ERR_UNRESPONSIVE, + "cli_write_one2file failed"); + #if 0 /** Check that the app_pf does not exist */ /** @@ -722,13 +763,12 @@ fpga_pci_remove_app_pf(struct fpga_pci_resource_map *app_map) ret = fpga_pci_check_app_pf_sysfs(dir_name, false); /** exists==false */ fail_on(ret != 0, err, "fpga_pci_check_app_pf_sysfs failed"); #endif - - errno = 0; - return 0; + + ret = 0; err: errno = 0; - return FPGA_ERR_FAIL; -} + return ret; +} /** * PCI rescan. @@ -743,18 +783,19 @@ fpga_pci_rescan(void) char sysfs_name[NAME_MAX + 1]; int ret = snprintf(sysfs_name, sizeof(sysfs_name), "/sys/bus/pci/rescan"); - fail_on(ret < 0, err, - "Error building the sysfs path for PCI rescan file"); - fail_on((size_t) ret >= sizeof(sysfs_name), err, - "sysfs path too long for PCI rescan file"); + fail_on_with_code(ret < 0, err, ret, FPGA_ERR_SOFTWARE_PROBLEM, + "Error building the sysfs path for PCI rescan file"); + fail_on_with_code((size_t) ret >= sizeof(sysfs_name), err, ret, + FPGA_ERR_SOFTWARE_PROBLEM, "sysfs path too long for PCI rescan file"); /** Write a "1" to the PCI rescan file */ ret = fpga_pci_write_one2file(sysfs_name); - fail_on(ret != 0, err, "fpga_pci_write_one2file failed"); + fail_on_with_code(ret != 0, err, ret, FPGA_ERR_UNRESPONSIVE, + "fpga_pci_write_one2file failed"); - return 0; + ret = 0; err: - return FPGA_ERR_FAIL; + return ret; } int @@ -799,7 +840,7 @@ fpga_pci_rescan_slot_app_pfs(int slot_id) ret = fpga_pci_check_app_pf(app_map, true); /** exists==true */ fail_on(ret != 0, err, "fpga_pci_check_app_pf failed"); - return 0; + ret = 0; err: - return FPGA_ERR_FAIL; + return ret; } diff --git a/sdk/userspace/fpga_mgmt_tools/src/fpga_local_cmd.c b/sdk/userspace/fpga_mgmt_tools/src/fpga_local_cmd.c index dae73ad3..af1c910d 100644 --- a/sdk/userspace/fpga_mgmt_tools/src/fpga_local_cmd.c +++ b/sdk/userspace/fpga_mgmt_tools/src/fpga_local_cmd.c @@ -655,6 +655,10 @@ main(int argc, char *argv[]) */ if (ret && !f1.parser_completed) { printf("Error: (%d) %s\n", ret, fpga_mgmt_strerror(ret)); + const char *long_help = fpga_mgmt_strerror_long(ret); + if (long_help) { + printf(long_help); + } } cli_detach(); cli_destroy(); diff --git a/sdk/userspace/include/fpga_dma.h b/sdk/userspace/include/fpga_dma.h index f72ce6d4..7fa27fb1 100644 --- a/sdk/userspace/include/fpga_dma.h +++ b/sdk/userspace/include/fpga_dma.h @@ -105,6 +105,22 @@ int fpga_dma_burst_read(int fd, uint8_t *buffer, size_t xfer_sz, int fpga_dma_burst_write(int fd, uint8_t *buffer, size_t xfer_sz, size_t address); +/** + * The EDMA and XDMA drivers use a device number which does not map directly + * onto the slot number. Use this function to map a slot number onto this device + * number. The device number is the number used in the files found in /dev. + * + * @param which_driver - specifies which DMA driver to use. See + * @param slot_id - fpga_dma_driver_e which FPGA slot to use; this uses + * the same slot order as fpga_pci_get_resource_map + * @param[out] device_num - an out parameter for returning the device number + * requested + * + * @returns 0 on success, non-zero on failure + */ +int fpga_pci_get_dma_device_num(enum fpga_dma_driver which_driver, + int slot_id, int *device_num); + #ifdef __cplusplus } #endif diff --git a/sdk/userspace/include/fpga_mgmt.h b/sdk/userspace/include/fpga_mgmt.h index 25dcb5cd..588d28ae 100644 --- a/sdk/userspace/include/fpga_mgmt.h +++ b/sdk/userspace/include/fpga_mgmt.h @@ -48,6 +48,14 @@ int fpga_mgmt_close(void); */ const char *fpga_mgmt_strerror(int err); +/** + * Get a longer explanation of an error string. + * + * @param[in] err The error code to decode + * @returns a string with an explanation of the likely cause of this error. + */ +const char *fpga_mgmt_strerror_long(int err); + /** * Sets the command timeout value in multiples of the delay_msec value. * diff --git a/sdk/userspace/include/fpga_pci.h b/sdk/userspace/include/fpga_pci.h index 9c1f9d8d..7e9154c7 100644 --- a/sdk/userspace/include/fpga_pci.h +++ b/sdk/userspace/include/fpga_pci.h @@ -256,6 +256,8 @@ int fpga_pci_memset(pci_bar_handle_t handle, uint64_t offset, uint32_t value, * environment, it can use this lock to protect calls to readdir. */ extern pthread_mutex_t fpga_pci_readdir_mutex; +#else +#define FPGA_PCI_USE_READDIR_R #endif diff --git a/sdk/userspace/include/hal/fpga_common.h b/sdk/userspace/include/hal/fpga_common.h index c0bd3a80..0bb1e321 100644 --- a/sdk/userspace/include/hal/fpga_common.h +++ b/sdk/userspace/include/hal/fpga_common.h @@ -59,6 +59,7 @@ enum { FPGA_CMD_DRAM_DATA_RETENTION , }; + /** * FPGA specific errors * e.g. as returned by fpga-load-local-image, fpga-clear-local-image, @@ -70,6 +71,7 @@ enum { * * Any additions should also be added to FPGA_ERR2STR (see below). */ + enum { /** Negative values are compatible with standard errno returns */ @@ -105,15 +107,28 @@ enum { * possible. This prevents the loss of data when retention cannot work. */ FPGA_ERR_DRAM_DATA_RETENTION_NOT_POSSIBLE = 18, - /* Reserved: 19-21 */ + /** Reserved: 19 */ + + /** Unable to locate PCI devices/resources */ + FPGA_ERR_PCI_MISSING = 20, + + FPGA_ERR_AFI_CMD_MALFORMED = 21, /** Data retention was attempted, but failed and data was lost. All efforts * are made to avoid this condition. */ FPGA_ERR_DRAM_DATA_RETENTION_FAILED = 22, + /** Saving DDR control calibration failed and data retention will not be * possible. */ FPGA_ERR_DRAM_DATA_RETENTION_SETUP_FAILED = 23, + /** This error indicates a bug or unhandled external condition in the + * software. Report occurrences on github. */ + FPGA_ERR_SOFTWARE_PROBLEM = 24, + + /** Cannot communicate with the FPGA */ + FPGA_ERR_UNRESPONSIVE = 25, + FPGA_ERR_END }; @@ -131,6 +146,10 @@ enum { ((error) == FPGA_ERR_DRAM_DATA_RETENTION_NOT_POSSIBLE) ? "dram-data-retention-not-possible" : \ ((error) == FPGA_ERR_DRAM_DATA_RETENTION_FAILED) ? "dram-data-retention-failed" : \ ((error) == FPGA_ERR_DRAM_DATA_RETENTION_SETUP_FAILED) ? "dram-data-retention-setup-failed" : \ + ((error) == FPGA_ERR_PCI_MISSING) ? "pci-device-missing" : \ + ((error) == FPGA_ERR_SOFTWARE_PROBLEM) ? "software-problem": \ + ((error) == FPGA_ERR_UNRESPONSIVE) ? "unresponsive": \ + ((error) == FPGA_ERR_AFI_CMD_MALFORMED) ? "afi-command-malformed" : \ "internal-error" diff --git a/sdk/userspace/include/utils/io.h b/sdk/userspace/include/utils/io.h index b029956b..6e9476cc 100644 --- a/sdk/userspace/include/utils/io.h +++ b/sdk/userspace/include/utils/io.h @@ -19,6 +19,7 @@ #pragma once +#include #include #include #include diff --git a/sdk/userspace/include/utils/log.h b/sdk/userspace/include/utils/log.h index 09149785..c63221da 100644 --- a/sdk/userspace/include/utils/log.h +++ b/sdk/userspace/include/utils/log.h @@ -167,6 +167,19 @@ static inline __printf(1, 2) void log_dummy(const char *fmt, ...) } \ } while (0) +/** Usage: + * fail_on(condition, label, return code variable, return code value, + * message format string, [arg1, arg2, ...]) + */ +#define fail_on_with_code(CONDITION, LABEL, RET, RET_VALUE, ...) \ + do { \ + if (CONDITION) { \ + log_error(__VA_ARGS__); \ + RET = RET_VALUE; \ + goto LABEL; \ + } \ + } while (0) + #define fail_on_quiet(CONDITION, LABEL, ...) \ do { \ if (CONDITION) { \ diff --git a/sdk_setup.sh b/sdk_setup.sh index e027e536..06f2853b 100644 --- a/sdk_setup.sh +++ b/sdk_setup.sh @@ -30,6 +30,7 @@ current_dir=$(pwd) source $script_dir/shared/bin/set_common_functions.sh source $script_dir/shared/bin/set_common_env_vars.sh +sudo rm -f /tmp/sdk_root_env.exp typeset -f allow_non_root > /tmp/sdk_root_env.exp echo "export AWS_FPGA_SDK_GROUP=${AWS_FPGA_SDK_GROUP}" >> /tmp/sdk_root_env.exp echo "export SDK_NON_ROOT_USER=${SDK_NON_ROOT_USER}" >> /tmp/sdk_root_env.exp diff --git a/shared/bin/set_common_functions.sh b/shared/bin/set_common_functions.sh index 2e4d981a..519b5e83 100644 --- a/shared/bin/set_common_functions.sh +++ b/shared/bin/set_common_functions.sh @@ -100,24 +100,24 @@ function get_vivado_version { } function setup_patches { - # unset MYVIVADO so we always start with a clear non-patched version - unset MYVIVADO - - patch_AR70350 + patch_AR71715 } -function patch_AR70350 { - local bucket="aws-fpga-developer-ami/1.3.3/Patches" - local object="AR703530_SDx_patch.zip" - local patch_dirname="AR703530" - local patch_root="$AWS_FPGA_REPO_DIR/patches" - declare -a valid_vivado_versions=( "Vivado v2017.1_sdx (64-bit)" - "Vivado v2017.1_sdxop (64-bit)" - ) +function patch_AR71715 { + local bucket="aws-fpga-developer-ami/1.5.0/Patches" + local object="AR71715.zip" + local patch_dirname="AR71715" + local patch_root="$XILINX_SDX/patches" + local tool_dir="$XILINX_SDX" + + declare -a valid_vivado_versions=( "Vivado v2018.2_AR71275_op (64-bit)" + "Vivado v2018.2.op (64-bit)" + "Vivado v2018.2 (64-bit)" + ) local base_vivado_version=$(get_base_vivado_version) is_patch_valid=false - + info_msg "Base vivado version is $base_vivado_version ; Checking if patch AR71715 needs to be installed" for vivado_version in "${valid_vivado_versions[@]}" do if [ ":$vivado_version" == ":$base_vivado_version" ]; then @@ -126,28 +126,31 @@ function patch_AR70350 { done if [ "$is_patch_valid" == "true" ]; then + + info_msg " SDX patch $patch_dirname is valid for $base_vivado_version" + if [ ! -d $patch_root/$patch_dirname ]; then info_msg "Downloading the $patch_dirname patch." curl -s https://s3.amazonaws.com/$bucket/$object -o $object || { err_msg "Failed to download Patch $object from $bucket/$object"; return 2; } - mkdir -p $patch_root || { err_msg "Failed to create path $patch_root"; return 2; } + sudo mkdir -p $patch_root || { err_msg "Failed to create path $patch_root you need to have root permissions to install this patch. If you dont have root permissions please contact your system administrator"; return 2; } info_msg "Extracting the $patch_dirname patch." - unzip $object -d $patch_root/$patch_dirname || { err_msg "Failed to unzip $object into: $patch_root/$patch_dirname"; return 2; } + sudo unzip $object -d $patch_root/$patch_dirname || { err_msg "Failed to unzip $object into: $patch_root/$patch_dirname"; return 2; } + sudo cp $tool_dir/scripts/ocl/ocl_util.tcl $tool_dir/scripts/ocl/ocl_util.tcl.bkp + sudo cp -f $patch_root/$patch_dirname/sdx/scripts/ocl/ocl_util.tcl $tool_dir/scripts/ocl/ocl_util.tcl rm $object chmod -R 755 $patch_root/$patch_dirname fi - - munge_myvivado_var $patch_root/$patch_dirname/vivado fi - } + function allow_non_root { [ ! -z ${AWS_FPGA_ALLOW_NON_ROOT} ] } diff --git a/shared/lib/aws_fpga_test_utils/AwsFpgaTestBase.py b/shared/lib/aws_fpga_test_utils/AwsFpgaTestBase.py index a8fb7f1d..f0901f7e 100644 --- a/shared/lib/aws_fpga_test_utils/AwsFpgaTestBase.py +++ b/shared/lib/aws_fpga_test_utils/AwsFpgaTestBase.py @@ -66,6 +66,7 @@ class AwsFpgaTestBase(object): git_repo_dir = get_git_repo_root(dirname(__file__)) WORKSPACE = git_repo_dir + ADD_SIMULATOR = False ADD_EXAMPLEPATH = False ADD_RTENAME = False ADD_XILINX_VERSION = False @@ -401,15 +402,30 @@ def get_agfi_from_readme(cl): return (agfi, afi) @staticmethod - def fpga_clear_local_image(slot, request_timeout=6000, sync_timeout=180): + def exec_as_user(as_root, command): + if as_root: + return "sudo {}".format(command) + else: + return command + + @staticmethod + def fpga_clear_local_image(slot, request_timeout=6000, sync_timeout=180, + as_root=True): logger.info("Clearing FPGA slot {}".format(slot)) - (rc, stdout_lines, stderr_lines) = AwsFpgaTestBase.run_cmd("sudo fpga-clear-local-image -S {} --request-timeout {} --sync-timeout {}".format(slot, request_timeout, sync_timeout)) + cmd = "{} -S {} --request-timeout {} --sync-timeout {}".format( + AwsFpgaTestBase.exec_as_user(as_root, "fpga-clear-local-image"), slot, + request_timeout, sync_timeout) + (rc, stdout_lines, stderr_lines) = AwsFpgaTestBase.run_cmd(cmd) assert rc == 0, "Clearing FPGA slot {} failed.".format(slot) @staticmethod - def fpga_load_local_image(agfi, slot, request_timeout=6000, sync_timeout=180): + def fpga_load_local_image(agfi, slot, request_timeout=6000, + sync_timeout=180, as_root=True): logger.info("Loading {} into slot {}".format(agfi, slot)) - (rc, stdout_lines, stderr_lines) = AwsFpgaTestBase.run_cmd("sudo fpga-load-local-image -S {} -I {} --request-timeout {} --sync-timeout {}".format(slot, agfi, request_timeout, sync_timeout)) + cmd = "{} -S {} -I {} --request-timeout {} --sync-timeout {}".format( + AwsFpgaTestBase.exec_as_user(as_root, "fpga-load-local-image"), slot, agfi, + request_timeout, sync_timeout) + (rc, stdout_lines, stderr_lines) = AwsFpgaTestBase.run_cmd(cmd) assert rc == 0, "Failed to load {} in slot {}.".format(agfi, slot) @staticmethod @@ -423,8 +439,10 @@ def check_fpga_afi_loaded(agfi, slot): return fpgaLocalImage @staticmethod - def fpga_get_virtual_led(slot, remove_dashes=False): - (rc, stdout_lines, stderr_lines) = AwsFpgaTestBase.run_cmd("sudo fpga-get-virtual-led -S {}".format(slot)) + def fpga_get_virtual_led(slot, remove_dashes=False, as_root=True): + cmd = "{} -S {}".format(AwsFpgaTestBase.exec_as_user(as_root, "fpga-get-virtual-led"), + slot) + (rc, stdout_lines, stderr_lines) = AwsFpgaTestBase.run_cmd(cmd) assert rc == 0, "Failed to get virtual LEDs from slot {}.".format(slot) value = stdout_lines[1] if remove_dashes: @@ -432,8 +450,9 @@ def fpga_get_virtual_led(slot, remove_dashes=False): return value @staticmethod - def fpga_get_virtual_dip_switch(slot, remove_dashes=False): - (rc, stdout_lines, stderr_lines) = AwsFpgaTestBase.run_cmd("sudo fpga-get-virtual-dip-switch -S {}".format(slot)) + def fpga_get_virtual_dip_switch(slot, remove_dashes=False, as_root=True): + cmd = "{} -S {}".format(AwsFpgaTestBase.exec_as_user(as_root, "fpga-get-virtual-dip-switch"), slot) + (rc, stdout_lines, stderr_lines) = AwsFpgaTestBase.run_cmd(cmd) assert rc == 0, "Failed to get virtual DIP switches from slot {}.".format(slot) value = stdout_lines[1] if remove_dashes: @@ -441,9 +460,11 @@ def fpga_get_virtual_dip_switch(slot, remove_dashes=False): return value @staticmethod - def fpga_set_virtual_dip_switch(value, slot): + def fpga_set_virtual_dip_switch(value, slot, as_root=True): value = re.sub('-', '', value) - (rc, stdout_lines, stderr_lines) = AwsFpgaTestBase.run_cmd("sudo fpga-set-virtual-dip-switch -S {} -D {}".format(slot, value)) + cmd = "{} -S {} -D {}".format(AwsFpgaTestBase.exec_as_user(as_root, "fpga-set-virtual-dip-switch"), + slot, value) + (rc, stdout_lines, stderr_lines) = AwsFpgaTestBase.run_cmd(cmd) assert rc == 0, "Failed to set virtual DIP switches in slot {} to {}.".format(slot, value) @staticmethod diff --git a/shared/lib/aws_fpga_test_utils/__init__.py b/shared/lib/aws_fpga_test_utils/__init__.py index dabe74cd..ed36c461 100644 --- a/shared/lib/aws_fpga_test_utils/__init__.py +++ b/shared/lib/aws_fpga_test_utils/__init__.py @@ -139,6 +139,11 @@ def install_xdma_driver(mode='poll'): assert os.system(install_command) == 0 +def xocl_driver_installed(): + if os.system('/usr/sbin/lsmod | grep xocl') == 0: + return True + return False + def remove_xocl_driver(): logger.info("Removing the xocl driver.") # This fails if the driver isn't installed @@ -152,10 +157,28 @@ def remove_xocl_driver(): assert os.system('sudo rm -f /etc/udev/rules.d/10-xocl.rules') == 0 +def install_xocl_driver(): + logger.info("Installing the xocl driver") + #check if xocl is already installed and install only if not present + if xocl_driver_installed(): + logger.info("xocl driver is already installed.") + else: + logger.info("xocl driver is not installed. inserting") + assert os.system("sudo insmod xocl") == 0 + def remove_all_drivers(): - remove_xdma_driver() - remove_edma_driver() - remove_xocl_driver() + # Check if the file exists + if xdma_driver_installed(): + logger.info("xdma driver is installed. removing for teardown") + remove_xdma_driver() + + if edma_driver_installed(): + logger.info("Edma driver is installed. removing for teardown") + remove_edma_driver() + + if xocl_driver_installed(): + logger.info("xocl driver is installed. removing for teardown") + remove_xocl_driver() class FpgaLocalImage: def __init__(self): diff --git a/shared/tests/bin/setup_test_runtime_sdaccel_env.sh b/shared/tests/bin/setup_test_runtime_sdaccel_env.sh index 6d97f8ce..b16239f9 100644 --- a/shared/tests/bin/setup_test_runtime_sdaccel_env.sh +++ b/shared/tests/bin/setup_test_runtime_sdaccel_env.sh @@ -31,6 +31,10 @@ if ! source $script_dir/setup_test_env.sh; then return 1 fi +if ! source $script_dir/setup_test_xrtpatch.sh; then + return 1 +fi + if ! source $WORKSPACE/sdaccel_setup.sh; then return 1 fi diff --git a/shared/tests/bin/setup_test_xrtpatch.sh b/shared/tests/bin/setup_test_xrtpatch.sh new file mode 100644 index 00000000..47e381e1 --- /dev/null +++ b/shared/tests/bin/setup_test_xrtpatch.sh @@ -0,0 +1,74 @@ +# Amazon FPGA Hardware Development Kit +# +# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. + +# Script must be sourced from a bash shell or it will not work +# When being sourced $0 will be the interactive shell and $BASH_SOURCE_ will contain the script being sourced +# When being run $0 and $_ will be the same. + +script=${BASH_SOURCE[0]} +if [ $script == $0 ]; then + echo "ERROR: You must source this script" + exit 2 +fi + +full_script=$(readlink -f $script) +script_name=$(basename $full_script) +script_dir=$(dirname $full_script) + +s3_ami_bucket=aws-fpga-developer-ami +s3_ami_version=1.5.0 +xrt_rpm_name=xrt_201802.2.1.0_7.5.1804-xrt.rpm +aws_xrt_rpm_name=xrt_201802.2.1.0_7.5.1804-aws.rpm + +xrt_rpm_path=$s3_ami_bucket/$s3_ami_version/Patches/$xrt_rpm_name +aws_xrt_rpm_path=$s3_ami_bucket/$s3_ami_version/Patches/$aws_xrt_rpm_name + +VIVADO_TOOL_VERSION=`vivado -version | grep Vivado | head -1 | sed 's:Vivado *::' | sed 's: .*$::' | sed 's:v::'` +export VIVADO_TOOL_VERSION=${VIVADO_TOOL_VERSION:0:6} +echo "VIVADO_TOOL_VERSION is $VIVADO_TOOL_VERSION" + + +if [[ "$VIVADO_TOOL_VERSION" =~ .*2018\.2.* ]]; then + echo "Xilinx Vivado version is 2018.2" + + if [ -f "/opt/xilinx/xrt/include/version.h" ]; then + echo "XRT installed. proceeding to check version compatibility" + xrt_build_ver=$(grep 'xrt_build_version_hash\[\]' /opt/xilinx/xrt/include/version.h | sed 's/";//' | sed 's/^.*"//') + echo "Installed XRT version hash : $xrt_build_ver" + if grep -Fxq "$xrt_build_ver" $AWS_FPGA_REPO_DIR/SDAccel/sdaccel_xrt_version.txt + then + echo "XRT version $xrt_build_ver is up-to-date." + else + echo "$xrt_build_ver is stale. upgrading XRT to" + cat $AWS_FPGA_REPO_DIR/SDAccel/sdaccel_xrt_version.txt + curl -s https://s3.amazonaws.com/$xrt_rpm_path -o $xrt_rpm_name || { echo " Error: Failed to download xrt rpm from $xrt_rpm_path"; return 2; } + curl -s https://s3.amazonaws.com/$aws_xrt_rpm_path -o $aws_xrt_rpm_name || { echo " Error: Failed to download aws xrt rpm from $aws_xrt_rpm_path"; return 2; } + sudo yum reinstall -y $xrt_rpm_name + echo " XRT patch rpm installed successfully" + sudo yum install -y $aws_xrt_rpm_name + echo " XRT patch aws rpm installed successfully" + fi + else + echo "XRT not installed. Please install XRT" + curl -s https://s3.amazonaws.com/$xrt_rpm_path -o $xrt_rpm_name || { echo " Error: Failed to download xrt rpm from $xrt_rpm_path"; return 2; } + curl -s https://s3.amazonaws.com/$aws_xrt_rpm_path -o $aws_xrt_rpm_name || { echo " Error: Failed to download aws xrt rpm from $aws_xrt_rpm_path"; return 2; } + sudo yum reinstall -y $xrt_rpm_name + echo " XRT patch rpm installed successfully" + sudo yum install -y $aws_xrt_rpm_name + echo " XRT patch aws rpm installed successfully" + fi + else + echo "Xilinx Vivado version is $VIVADO_TOOL_VERSION " +fi