diff --git a/.gitmodules b/.gitmodules
index 7133941d..3cad5231 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -8,3 +8,6 @@
 [submodule "Vitis/examples/xilinx_2020.1"]
 	path = Vitis/examples/xilinx_2020.1
 	url = https://github.com/Xilinx/Vitis_Accel_Examples
+[submodule "Vitis/examples/xilinx_2020.2"]
+	path = Vitis/examples/xilinx_2020.2
+	url = https://github.com/Xilinx/Vitis_Accel_Examples
diff --git a/FAQs.md b/FAQs.md
index 493a49a5..52e5ce16 100644
--- a/FAQs.md
+++ b/FAQs.md
@@ -103,7 +103,15 @@ Every FPGA deployed in AWS cloud includes an AWS Shell, and the developer Custom
 
 It is the compiled FPGA code that is loaded into an FPGA in AWS for performing the Custom Logic (CL) function created by the developer. AFIs are maintained by AWS according and associated with the AWS account that created them. The AFI includes the CL and AWS FPGA Shell. An AFI ID is used to reference a particular AFI from an F1 instance.
 
-The developer can create multiple AFIs at no extra cost, up to a defined limited (typically 100 AFIs per region per AWS account). An AFI can be loaded into as many FPGAs as needed.
+The developer can create multiple AFIs at no extra cost, up to a defined limited (typically 500 AFIs per region per AWS account). An AFI can be loaded into as many FPGAs as needed.
+
+**Q: How do I increase my AFI limit?**
+
+You can increase your AFI limit by creating an [AWS Support Case](https://console.aws.amazon.com/support/home#/case/create). 
+1. Select the `Service Limit Increase` tab 
+2. In the `Limit Type`, select `EC2 FPGA`
+3. Select the region(s) where you want your limit to be increased
+4. Add justification for the limit increase. 
 
 
 **Q: What regions are supported?**
diff --git a/Jenkinsfile b/Jenkinsfile
index b1a1fd95..4f980364 100644
--- a/Jenkinsfile
+++ b/Jenkinsfile
@@ -126,9 +126,9 @@ task_label = [
 ]
 
 // Put the latest version last
-def xilinx_versions = [ '2019.1', '2019.2', '2020.1' ]
+def xilinx_versions = [ '2019.1', '2019.2', '2020.1' , '2020.2' ]
 
-def vitis_versions = ['2019.2', '2020.1']
+def vitis_versions = ['2019.2', '2020.1' , '2020.2' ]
 
 // We want the default to be the latest.
 def default_xilinx_version = xilinx_versions.last()
@@ -139,7 +139,8 @@ def dsa_map = [
 
 def xsa_map = [
     '2019.2' : [ 'DYNAMIC':'dyn'],
-    '2020.1' : [ 'DYNAMIC':'dyn']
+    '2020.1' : [ 'DYNAMIC':'dyn'],
+    '2020.2' : [ 'DYNAMIC':'dyn']
 ]
 
 def sdaccel_example_default_map = [
@@ -165,6 +166,14 @@ def vitis_example_default_map = [
         'RTL_Vadd_Debug': 'Vitis/examples/xilinx/rtl_kernels/rtl_vadd_hw_debug',
         'gemm_blas': 'Vitis/examples/xilinx/library_examples/gemm',
         'gzip_app': 'Vitis/examples/xilinx/library_examples/gzip_app'
+    ],
+    '2020.2' : [
+        'Hello_World_1ddr': 'Vitis/examples/xilinx/ocl_kernels/cl_helloworld',
+        'Gmem_2Banks_2ddr': 'Vitis/examples/xilinx/ocl_kernels/cl_gmem_2banks',
+        'Kernel_Global_Bw_4ddr': 'Vitis/examples/xilinx/cpp_kernels/kernel_global_bandwidth',
+        'RTL_Vadd_Debug': 'Vitis/examples/xilinx/rtl_kernels/rtl_vadd_hw_debug',
+        'gemm_blas': 'Vitis/examples/xilinx/library_examples/gemm',
+        'gzip_app': 'Vitis/examples/xilinx/library_examples/gzip_app'
     ]
 ]
 
@@ -186,6 +195,12 @@ def simulator_tool_default_map = [
          'vcs': 'synopsys/vcs-mx/P-2019.06-SP1-1',
          'questa': 'questa/2019.4',
          'ies': 'incisive/15.20.079'
+     ],
+     '2020.2' : [
+         'vivado': 'xilinx/Vivado/2020.2',
+         'vcs': 'synopsys/vcs-mx/Q-2020.03',
+         'questa': 'questa/2020.2',
+         'ies': 'incisive/15.20.083'
      ]
 ]
 
diff --git a/Jenkinsfile_int_sims b/Jenkinsfile_int_sims
index 7c8349c2..51a2d46f 100644
--- a/Jenkinsfile_int_sims
+++ b/Jenkinsfile_int_sims
@@ -36,7 +36,7 @@ task_label = [
 ]
 
 // Put the latest version last
-def xilinx_versions = [ '2019.2' ]
+def xilinx_versions = [ '2020.2' ]
 
 // We want the default to be the latest.
 def default_xilinx_version = xilinx_versions.last()
@@ -53,6 +53,12 @@ def simulator_tool_default_map = [
          'vcs': 'synopsys/vcs-mx/P-2019.06-SP1-1',
          'questa': 'questa/2019.4',
          'ies': 'incisive/15.20.079'
+     ],
+     '2020.2' : [
+         'vivado': 'xilinx/Vivado/2020.2',
+         'vcs': 'synopsys/vcs/Q-2020.03',
+         'questa': 'questa/2019.4_3',
+         'ies': 'incisive/15.20.083'
      ]
 ]
 
@@ -177,7 +183,7 @@ if (test_sims) {
                                         module purge
                                         module load python/3.7.2
                                         module load python/2.7.14
-                                        module load batch
+                                        module load slurm
                                         module load ${vivado_module}
                                         module load ${vcs_module}
                                         module load ${questa_module}
diff --git a/README.md b/README.md
index 08044245..3d851c6d 100644
--- a/README.md
+++ b/README.md
@@ -50,6 +50,7 @@ AWS marketplace offers multiple versions of the FPGA Developer AMI. The followin
 
 | Developer Kit Version | Tool Version Supported | Compatible FPGA Developer AMI Version |
 |-----------|-----------|------|
+| 1.4.18+ | 2020.2 | v1.10.X (Xilinx Vivado/Vitis 2020.2) |
 | 1.4.16+ | 2020.1 | v1.9.0-v1.9.X (Xilinx Vivado/Vitis 2020.1) |
 | 1.4.13+ | 2019.2 | v1.8.0-v1.8.X (Xilinx Vivado/Vitis 2019.2) |
 | 1.4.11+ | 2019.1 | v1.7.0-v1.7.X (Xilinx Vivado/SDx 2019.1) |
diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md
index 3b9b8ead..38d40175 100644
--- a/RELEASE_NOTES.md
+++ b/RELEASE_NOTES.md
@@ -1,5 +1,8 @@
 # AWS EC2 FPGA HDK+SDK Release Notes
 
+## Release 1.4.18 (See [ERRATA](./ERRATA.md) for unsupported features)
+* FPGA developer kit now supports Xilinx Vivado/Vitis 2020.2
+
 ## Release 1.4.17 (See [ERRATA](./ERRATA.md) for unsupported features)
 * Updated XDMA Driver to allow builds on newer kernels
 * Updated documentation on Alveo U200 to F1 platform porting
diff --git a/Vitis/docs/Create_Runtime_AMI.md b/Vitis/docs/Create_Runtime_AMI.md
index 087a4ba4..8cc3bc62 100644
--- a/Vitis/docs/Create_Runtime_AMI.md
+++ b/Vitis/docs/Create_Runtime_AMI.md
@@ -4,8 +4,9 @@
 
 | Vitis Version used for AFI Development | Compatible Xilinx Runtime |
 |--------------------------------------|-----------------------------|
-| 2020.1 | AWS FPGA Developer AMI 1.9.0 (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2020.1/html/build.html) |
-| 2019.2 | AWS FPGA Developer AMI 1.8.0 (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2019.2/html/build.html) |
+| 2020.2 | AWS FPGA Developer AMI 1.10.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2020.2/html/build.html) |
+| 2020.1 | AWS FPGA Developer AMI 1.9.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2020.1/html/build.html) |
+| 2019.2 | AWS FPGA Developer AMI 1.8.x (XRT is pre-installed) or [XRT](https://xilinx.github.io/XRT/2019.2/html/build.html) |
 
 ## 1. Launch a Runtime Instance & Install Required Packages 
 
diff --git a/Vitis/docs/XRT_installation_instructions.md b/Vitis/docs/XRT_installation_instructions.md
index 85c30bb6..8a1afb9b 100644
--- a/Vitis/docs/XRT_installation_instructions.md
+++ b/Vitis/docs/XRT_installation_instructions.md
@@ -4,8 +4,9 @@
 * We provide pre-built RPM's for Centos/RHEL/AL2 and instructions for building XRT 
 * Use the below table as reference to install and use the correct XRT version for your applications.
 
-| Xilinx Vitis Tool Version | XRT Release Tag | SHA | `xrt`|`xrt-aws` RPM's (Centos/RHEL) |`xrt`|`xrt-aws` RPM's (AL2) 
-|---|---|---|---|
+| Xilinx Vitis Tool Version | XRT Release Tag | SHA | `xrt` or `xrt-aws` RPM's (Centos/RHEL) |`xrt` or`xrt-aws` RPM's (AL2) |
+|---|---|---|---|---|
+|2020.2| [202020.2.8.743](https://github.com/Xilinx/XRT/releases/tag/202020.2.8.743) | 77d5484b5c4daa691a7f78235053fb036829b1e9 | [xrt_202020.2.8.0_7.9.2009-x86_64-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.10.0/Patches/XRT_2020_2/xrt_202020.2.8.0_7.9.2009-x86_64-xrt.rpm) [xrt_202020.2.8.0_7.9.2009-x86_64-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.10.0/Patches/XRT_2020_2/xrt_202020.2.8.0_7.9.2009-x86_64-aws.rpm) | [xrt_202020.2.8.0_2-x86_64-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.10.0/Patches/XRT_2020_2/xrt_202020.2.8.0_2-x86_64-xrt.rpm) [xrt_202020.2.8.0_2-x86_64-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.10.0/Patches/XRT_2020_2/xrt_202020.2.8.0_2-x86_64-aws.rpm)|
 |2020.1| [202010.2.6.AWS](https://github.com/Xilinx/XRT/releases/tag/202010.2.6.AWS) | d09c4a458c16e8d843b3165dcf929c38f7a32b6f | [xrt_202010.2.6.0_7.7.1908-x86_64-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.9.0/Patches/XRT_2020_1/xrt_202010.2.6.0_7.7.1908-x86_64-xrt.rpm) [xrt_202010.2.6.0_7.7.1908-x86_64-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.9.0/Patches/XRT_2020_1/xrt_202010.2.6.0_7.7.1908-x86_64-aws.rpm) | [xrt_202010.2.6.0_2-x86_64-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.9.0/Patches/XRT_2020_1/xrt_202010.2.6.0_2-x86_64-xrt.rpm) [xrt_202010.2.6.0_2-x86_64-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.9.0/Patches/XRT_2020_1/xrt_202010.2.6.0_2-x86_64-aws.rpm)|
 |2019.2| [2019.2.0.3](https://github.com/Xilinx/XRT/releases/tag/2019.2.0.3) | 9e13d57c4563e2c19bf5f518993f6e5a8dadc18a | [xrt_201920.2.3.0_7.7.1908-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.8.0/Patches/XRT_2019_2/xrt_201920.2.3.0_7.7.1908-xrt.rpm) [xrt_201920.2.3.0_7.7.1908-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.8.0/Patches/XRT_2019_2/xrt_201920.2.3.0_7.7.1908-aws.rpm) | N/A |
 
diff --git a/Vitis/examples/xilinx_2020.2 b/Vitis/examples/xilinx_2020.2
new file mode 160000
index 00000000..f72dff9e
--- /dev/null
+++ b/Vitis/examples/xilinx_2020.2
@@ -0,0 +1 @@
+Subproject commit f72dff9eea45a76e9ee0713774589624e2b52c9f
diff --git a/Vitis/tools/create_vitis_afi.sh b/Vitis/tools/create_vitis_afi.sh
index c7bd9b9a..5f19c848 100755
--- a/Vitis/tools/create_vitis_afi.sh
+++ b/Vitis/tools/create_vitis_afi.sh
@@ -279,4 +279,10 @@ echo ${timestamp}_agfi_id.txt
 
 #STEP 6
 #Create .awsxclbin
-/opt/xilinx/xrt/bin/xclbinutil -i $xclbin --remove-section PARTITION_METADATA --remove-section SYSTEM_METADATA --replace-section BITSTREAM:RAW:${timestamp}_agfi_id.txt -o ${awsxclbin}.awsxclbin
+
+if [ "$RELEASE_VER" == "2020.2" ]
+then                            
+	/opt/xilinx/xrt/bin/xclbinutil -i $xclbin --remove-section PARTITION_METADATA --replace-section BITSTREAM:RAW:${timestamp}_agfi_id.txt -o ${awsxclbin}.awsxclbin
+else
+	/opt/xilinx/xrt/bin/xclbinutil -i $xclbin --remove-section PARTITION_METADATA --remove-section SYSTEM_METADATA --replace-section BITSTREAM:RAW:${timestamp}_agfi_id.txt -o ${awsxclbin}.awsxclbin
+fi                                              
diff --git a/Vitis/vitis_xrt_version.txt b/Vitis/vitis_xrt_version.txt
index 3c06762f..df3ef470 100644
--- a/Vitis/vitis_xrt_version.txt
+++ b/Vitis/vitis_xrt_version.txt
@@ -1,4 +1,4 @@
 2019.2:9e13d57c4563e2c19bf5f518993f6e5a8dadc18a
 2020.1:12115fd4054cb46a5ade62fafa74c523f59116e6
 2020.1:d09c4a458c16e8d843b3165dcf929c38f7a32b6f
-
+2020.2:77d5484b5c4daa691a7f78235053fb036829b1e9
diff --git a/docs/on_premise_licensing_help.md b/docs/on_premise_licensing_help.md
index d58903e6..8b8f2af6 100644
--- a/docs/on_premise_licensing_help.md
+++ b/docs/on_premise_licensing_help.md
@@ -3,6 +3,11 @@
 **NOTE: If you are developing on the AWS cloud and using AWS FPGA Developer AMI provided on AWS Marketplace, you can skip this document.**
 
 This document helps developers who choose to develop on-premises with specifying and licensing AWS-compatible Xilinx tools for use with the AWS FPGA HDK.
+## Requirements for AWS HDK 1.4.18+ (2020.2)
+ * Xilinx Vivado or Vitis v2020.2
+ * License: EF-VIVADO-SDX-VU9P-OP
+ * URL: https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Unified_2020.2_1118_1232.tar.gz
+ * MD5 SUM Value: 523e8596f114ab5e389c14df50ecb1d8
 
 ## Requirements for AWS HDK 1.4.16+ (2020.1)
  * Xilinx Vivado or Vitis v2020.1
@@ -10,7 +15,7 @@ This document helps developers who choose to develop on-premises with specifying
  * URL: https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Unified_2020.1_0602_1208.tar.gz
  * MD5 SUM Value: b018f7b331ab0446137756156ff944d9
  
- ## Requirements for AWS HDK 1.4.13+ (2019.2)
+## Requirements for AWS HDK 1.4.13+ (2019.2)
  * Xilinx Vivado or Vitis v2019.2
  * License: EF-VIVADO-SDX-VU9P-OP
  * URL: https://www.xilinx.com/member/forms/download/xef-vitis.html?filename=Xilinx_Vitis_2019.2_1106_2127.tar.gz
diff --git a/hdk/README.md b/hdk/README.md
index f3b74fa9..6e3e3954 100644
--- a/hdk/README.md
+++ b/hdk/README.md
@@ -66,6 +66,8 @@ For more details on the examples, see the [examples table](./cl/examples/cl_exam
 | 1.4.11-1.4.x | 2019.1 | v1.7.0 (Xilinx Vivado 2019.1) |
 | 1.4.11-1.4.x | 2019.2 | v1.8.x (Xilinx Vivado 2019.2) |
 | 1.4.16-1.4.x | 2020.1 | v1.9.x (Xilinx Vivado 2020.1) |
+| 1.4.18-1.4.x | 2020.2 | v1.10.x (Xilinx Vivado 2020.2) |
+
 
 * The FPGA Developer Kit version is listed in [hdk_version.txt](./hdk_version.txt)
 
diff --git a/hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl
index f044ed7b..fdae02f6 100644
--- a/hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl
+++ b/hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl
@@ -19,7 +19,7 @@ package require tar
 set TOP top_sp
 
 ## Replace with the name of your module
-set CL_MODULE cl_dram_dma 
+set CL_MODULE cl_dram_dma
 
 #################################################
 ## Command-line Arguments
@@ -39,7 +39,7 @@ set uram_option         [lindex $argv 11]
 set notify_via_sns      [lindex $argv 12]
 set VDEFINES            [lindex $argv 13]
 ##################################################
-## Flow control variables 
+## Flow control variables
 ##################################################
 set cl.synth   1
 set implement  1
@@ -147,6 +147,9 @@ set_msg_config -id {DRC CKLD-2}          -suppress
 set_msg_config -id {DRC REQP-1853}       -suppress
 set_msg_config -id {Timing 38-436}       -suppress
 
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 # Check that an email address has been set, else unset notify_via_sns
 
 if {[string compare $notify_via_sns "1"] == 0} {
@@ -159,7 +162,7 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 ##################################################
-### Strategy options 
+### Strategy options
 ##################################################
 switch $strategy {
     "BASIC" {
@@ -200,7 +203,7 @@ source $HDK_SHELL_DIR/build/scripts/device_type.tcl
 source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
 
 ########################################
-## Generate clocks based on Recipe 
+## Generate clocks based on Recipe
 ########################################
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
@@ -254,7 +257,7 @@ if {$implement} {
       # Apply Clock Properties for Clock Table Recipes
       ##################################################
       puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
-      
+
       # Apply properties to clocks
       source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl
 
@@ -385,5 +388,3 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";
-
-
diff --git a/hdk/cl/examples/cl_dram_dma_hlx/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_dram_dma_hlx/build/scripts/create_dcp_from_cl.tcl
index 90553f00..63445b80 100755
--- a/hdk/cl/examples/cl_dram_dma_hlx/build/scripts/create_dcp_from_cl.tcl
+++ b/hdk/cl/examples/cl_dram_dma_hlx/build/scripts/create_dcp_from_cl.tcl
@@ -37,6 +37,10 @@ if {[string compare $notify_via_sns "1"] == 0} {
   }
 }
 
+# suppress warnings coming from Shell
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 #################################################
 ## Create BD (Block Design) of example Hello World design
 #################################################
diff --git a/hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl
index 8f7b975c..d36310e6 100644
--- a/hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl
+++ b/hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl
@@ -39,7 +39,7 @@ set uram_option         [lindex $argv 11]
 set notify_via_sns      [lindex $argv 12]
 set VDEFINES            [lindex $argv 13]
 ##################################################
-## Flow control variables 
+## Flow control variables
 ##################################################
 set cl.synth   1
 set implement  1
@@ -134,6 +134,9 @@ set_msg_config -id {Synth 8-3848}        -suppress
 set_msg_config -id {Synth 8-3917}        -suppress
 set_msg_config -id {Opt 31-430}          -suppress
 
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
 
 # Check that an email address has been set, else unset notify_via_sns
@@ -148,7 +151,7 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 ##################################################
-### Strategy options 
+### Strategy options
 ##################################################
 switch $strategy {
     "BASIC" {
@@ -187,14 +190,14 @@ source $HDK_SHELL_DIR/build/scripts/device_type.tcl
 source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
 
 ########################################
-## Generate clocks based on Recipe 
+## Generate clocks based on Recipe
 ########################################
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
 
 source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
 #################################################################
-#### Do not remove this setting. Need to workaround bug 
+#### Do not remove this setting. Need to workaround bug
 ##################################################################
 set_param hd.clockRoutingWireReduction false
 ##################################################
@@ -236,7 +239,7 @@ if {$implement} {
       # Apply Clock Properties for Clock Table Recipes
       ##################################################
       puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
-      
+
       # Apply properties to clocks
       source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl
 
@@ -365,5 +368,3 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";
-
-
diff --git a/hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl b/hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl
index f5819636..8d1d5c04 100644
--- a/hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl
+++ b/hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl
@@ -21,7 +21,7 @@ set VDEFINES $VDEFINES
 create_project -in_memory -part [DEVICE_TYPE] -force
 
 ########################################
-## Generate clocks based on Recipe 
+## Generate clocks based on Recipe
 ########################################
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
diff --git a/hdk/cl/examples/cl_hello_world_hlx/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_hello_world_hlx/build/scripts/create_dcp_from_cl.tcl
index af16971c..06938eee 100755
--- a/hdk/cl/examples/cl_hello_world_hlx/build/scripts/create_dcp_from_cl.tcl
+++ b/hdk/cl/examples/cl_hello_world_hlx/build/scripts/create_dcp_from_cl.tcl
@@ -37,6 +37,10 @@ if {[string compare $notify_via_sns "1"] == 0} {
   }
 }
 
+# suppress warnings coming from Shell
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 #################################################
 ## Create BD (Block Design) of example Hello World design
 #################################################
diff --git a/hdk/cl/examples/cl_hello_world_ref_hlx/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_hello_world_ref_hlx/build/scripts/create_dcp_from_cl.tcl
index 385782dc..99ff2a68 100755
--- a/hdk/cl/examples/cl_hello_world_ref_hlx/build/scripts/create_dcp_from_cl.tcl
+++ b/hdk/cl/examples/cl_hello_world_ref_hlx/build/scripts/create_dcp_from_cl.tcl
@@ -29,6 +29,10 @@ if {[string compare $notify_via_sns "1"] == 0} {
   }
 }
 
+# suppress warnings coming from Shell
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 #################################################
 ## Create BD (Block Design) of example Hello World design
 #################################################
diff --git a/hdk/cl/examples/cl_hello_world_vhdl/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_hello_world_vhdl/build/scripts/create_dcp_from_cl.tcl
index ad7a216c..75a28a7b 100644
--- a/hdk/cl/examples/cl_hello_world_vhdl/build/scripts/create_dcp_from_cl.tcl
+++ b/hdk/cl/examples/cl_hello_world_vhdl/build/scripts/create_dcp_from_cl.tcl
@@ -39,7 +39,7 @@ set uram_option         [lindex $argv 11]
 set notify_via_sns      [lindex $argv 12]
 set VDEFINES            [lindex $argv 13]
 ##################################################
-## Flow control variables 
+## Flow control variables
 ##################################################
 set cl.synth   1
 set implement  1
@@ -133,6 +133,10 @@ set_msg_config -id {Synth 8-350}         -suppress
 set_msg_config -id {Synth 8-3848}        -suppress
 set_msg_config -id {Synth 8-3917}        -suppress
 
+# suppress warnings coming from Shell
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
 
 # Check that an email address has been set, else unset notify_via_sns
@@ -147,7 +151,7 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 ##################################################
-### Strategy options 
+### Strategy options
 ##################################################
 switch $strategy {
     "BASIC" {
@@ -186,14 +190,14 @@ source $HDK_SHELL_DIR/build/scripts/device_type.tcl
 source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
 
 ########################################
-## Generate clocks based on Recipe 
+## Generate clocks based on Recipe
 ########################################
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
 
 source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
 #################################################################
-#### Do not remove this setting. Need to workaround bug 
+#### Do not remove this setting. Need to workaround bug
 #################################################################
 set_param hd.clockRoutingWireReduction false
 
@@ -235,7 +239,7 @@ if {$implement} {
       # Apply Clock Properties for Clock Table Recipes
       ##################################################
       puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
-      
+
       # Apply properties to clocks
       source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl
 
@@ -359,5 +363,3 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";
-
-
diff --git a/hdk/cl/examples/cl_hls_dds_hlx/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_hls_dds_hlx/build/scripts/create_dcp_from_cl.tcl
index 43d7d6d4..7e942750 100755
--- a/hdk/cl/examples/cl_hls_dds_hlx/build/scripts/create_dcp_from_cl.tcl
+++ b/hdk/cl/examples/cl_hls_dds_hlx/build/scripts/create_dcp_from_cl.tcl
@@ -29,6 +29,10 @@ if {[string compare $notify_via_sns "1"] == 0} {
   }
 }
 
+# suppress warnings coming from Shell
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 #################################################
 ## Create BD (Block Design) of example Hello World design
 #################################################
diff --git a/hdk/cl/examples/cl_ipi_cdma_test_hlx/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_ipi_cdma_test_hlx/build/scripts/create_dcp_from_cl.tcl
index e146e23c..911f471d 100755
--- a/hdk/cl/examples/cl_ipi_cdma_test_hlx/build/scripts/create_dcp_from_cl.tcl
+++ b/hdk/cl/examples/cl_ipi_cdma_test_hlx/build/scripts/create_dcp_from_cl.tcl
@@ -29,6 +29,10 @@ if {[string compare $notify_via_sns "1"] == 0} {
   }
 }
 
+# suppress warnings coming from Shell
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 #################################################
 ## Create BD (Block Design) of example Hello World design
 #################################################
diff --git a/hdk/cl/examples/cl_sde/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_sde/build/scripts/create_dcp_from_cl.tcl
index 1f16f71b..699332f1 100644
--- a/hdk/cl/examples/cl_sde/build/scripts/create_dcp_from_cl.tcl
+++ b/hdk/cl/examples/cl_sde/build/scripts/create_dcp_from_cl.tcl
@@ -19,7 +19,7 @@ package require tar
 set TOP top_sp
 
 ## Replace with the name of your module
-set CL_MODULE cl_sde 
+set CL_MODULE cl_sde
 
 #################################################
 ## Command-line Arguments
@@ -39,7 +39,7 @@ set uram_option         [lindex $argv 11]
 set notify_via_sns      [lindex $argv 12]
 
 ##################################################
-## Flow control variables 
+## Flow control variables
 ##################################################
 set cl.synth   1
 set implement  1
@@ -142,6 +142,9 @@ set_msg_config -id {DRC CKLD-2}          -suppress
 set_msg_config -id {DRC REQP-1853}       -suppress
 set_msg_config -id {Timing 38-436}       -suppress
 
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
 
 # Check that an email address has been set, else unset notify_via_sns
@@ -156,7 +159,7 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 ##################################################
-### Strategy options 
+### Strategy options
 ##################################################
 switch $strategy {
     "BASIC" {
@@ -195,7 +198,7 @@ source $HDK_SHELL_DIR/build/scripts/device_type.tcl
 source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
 
 ########################################
-## Generate clocks based on Recipe 
+## Generate clocks based on Recipe
 ########################################
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
@@ -245,7 +248,7 @@ if {$implement} {
       # Apply Clock Properties for Clock Table Recipes
       ##################################################
       puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
-      
+
       # Apply properties to clocks
       source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl
 
@@ -369,5 +372,3 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";
-
-
diff --git a/hdk/cl/examples/cl_uram_example/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_uram_example/build/scripts/create_dcp_from_cl.tcl
index 0b21940d..2c1a0888 100644
--- a/hdk/cl/examples/cl_uram_example/build/scripts/create_dcp_from_cl.tcl
+++ b/hdk/cl/examples/cl_uram_example/build/scripts/create_dcp_from_cl.tcl
@@ -39,7 +39,7 @@ set uram_option         [lindex $argv 11]
 set notify_via_sns      [lindex $argv 12]
 set VDEFINES            [lindex $argv 13]
 ##################################################
-## Flow control variables 
+## Flow control variables
 ##################################################
 set cl.synth   1
 set implement  1
@@ -133,6 +133,9 @@ set_msg_config -id {Synth 8-350}         -suppress
 set_msg_config -id {Synth 8-3848}        -suppress
 set_msg_config -id {Synth 8-3917}        -suppress
 
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
 
 # Check that an email address has been set, else unset notify_via_sns
@@ -147,7 +150,7 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 ##################################################
-### Strategy options 
+### Strategy options
 ##################################################
 switch $strategy {
     "BASIC" {
@@ -186,7 +189,7 @@ source $HDK_SHELL_DIR/build/scripts/device_type.tcl
 source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
 
 ########################################
-## Generate clocks based on Recipe 
+## Generate clocks based on Recipe
 ########################################
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
@@ -235,7 +238,7 @@ if {$implement} {
       # Apply Clock Properties for Clock Table Recipes
       ##################################################
       puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
-      
+
       # Apply properties to clocks
       source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl
 
@@ -300,7 +303,7 @@ if {$implement} {
 
    # This is what will deliver to AWS
    puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Writing final DCP to to_aws directory.";
-   
+
    #writing unencrypted dcp for analysis to checkpoints dir.
    write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.SH_CL_routed.dcp
 
@@ -363,5 +366,3 @@ if {[string compare $notify_via_sns "1"] == 0} {
 }
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";
-
-
diff --git a/hdk/cl/examples/hello_world_hlx/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/hello_world_hlx/build/scripts/create_dcp_from_cl.tcl
index 59246c89..5a5d24f5 100755
--- a/hdk/cl/examples/hello_world_hlx/build/scripts/create_dcp_from_cl.tcl
+++ b/hdk/cl/examples/hello_world_hlx/build/scripts/create_dcp_from_cl.tcl
@@ -29,6 +29,10 @@ if {[string compare $notify_via_sns "1"] == 0} {
   }
 }
 
+# suppress warnings coming from Shell
+set_msg_config -severity "CRITICAL WARNING" -string "WRAPPER_INST/SH" -suppress
+set_msg_config -severity "WARNING"          -string "WRAPPER_INST/SH" -suppress
+
 #################################################
 ## Create BD (Block Design) of example Hello World design
 #################################################
diff --git a/hdk/common/shell_v04261818/build/scripts/params.tcl b/hdk/common/shell_v04261818/build/scripts/params.tcl
index 96103532..1ad16bb1 100755
--- a/hdk/common/shell_v04261818/build/scripts/params.tcl
+++ b/hdk/common/shell_v04261818/build/scripts/params.tcl
@@ -25,3 +25,6 @@ if {$uram_option != 2} {
 ####Enable support of clocking from one RP to another (SH-->CL)
 set_param hd.supportClockNetCrossDiffReconfigurablePartitions 1 
 
+# Maintain DONT TOUCH functionality for 2020.2 onwards
+if {[string match *2020.2* [version -short]]} {set_param project.replaceDontTouchWithKeepHierarchySoft false}
+
diff --git a/hdk/common/shell_v04261818/hlx/hlx_setup.tcl b/hdk/common/shell_v04261818/hlx/hlx_setup.tcl
index 90fbb653..727dbaac 100644
--- a/hdk/common/shell_v04261818/hlx/hlx_setup.tcl
+++ b/hdk/common/shell_v04261818/hlx/hlx_setup.tcl
@@ -45,4 +45,6 @@ set aws::make_faas::public::bd_faas_examples_directory [file normalize [file joi
 set aws::make_faas::public::bd_faas_initscript [file join $aws::make_faas::public::bd_faas_build_directory scripts aws_bd_faas_initscript.tcl]
 set ::env(FAAS_HOOK_TCL) $::aws::make_faas::public::bd_faas_initscript
 
-
+# Maintain DONT TOUCH functionality for 2020.2 onwards
+if {[string match *2020.2* [version -short]]} {set_param project.replaceDontTouchWithKeepHierarchySoft false}
+#
diff --git a/hdk/docs/AFI_Manifest.md b/hdk/docs/AFI_Manifest.md
index b120f362..e6509387 100644
--- a/hdk/docs/AFI_Manifest.md
+++ b/hdk/docs/AFI_Manifest.md
@@ -40,6 +40,7 @@ The manifest file is a text file formatted with key=value pairs. Some keys are m
      
 | vivado tool version | field value |
 |------------------- | -----------|
+| 2020.2 |  tool_version=v2020.2 |
 | 2020.1 |  tool_version=v2020.1 |
 | 2019.2 |  tool_version=v2019.2 |
 | 2019.1 |  tool_version=v2019.1 |
diff --git a/hdk/docs/AWS_Shell_Interface_Specification.md b/hdk/docs/AWS_Shell_Interface_Specification.md
index 8016dae2..2733f9db 100644
--- a/hdk/docs/AWS_Shell_Interface_Specification.md
+++ b/hdk/docs/AWS_Shell_Interface_Specification.md
@@ -99,9 +99,9 @@ Starting from 1.4, The shell is reconfigurable, allowing, in most cases, develop
 
 **DW –** Doubleword: referring to 4-byte (32-bit) data size.
 
-[**AXI-4** ARM Advanced eXtensible Interface.](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.amba/index.html)
+[**AXI-4** ARM Advanced eXtensible Interface.](https://developer.arm.com/architectures/system-architectures/amba/amba-4)
 
-[**AXI-4 Stream –** ARM Advanced eXtensible Stream Interface.](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.amba/index.html)
+[**AXI-4 Stream –** ARM Advanced eXtensible Stream Interface.](https://developer.arm.com/architectures/system-architectures/amba/amba-4)
 
 **M –** Typically refers to the Master side of an AXI bus.
 
diff --git a/hdk/docs/RTL_Simulating_CL_Designs.md b/hdk/docs/RTL_Simulating_CL_Designs.md
index d071bd12..c940c719 100644
--- a/hdk/docs/RTL_Simulating_CL_Designs.md
+++ b/hdk/docs/RTL_Simulating_CL_Designs.md
@@ -4,12 +4,12 @@
 
 Developers tend to simulate their designs to validate the RTL design and functionality, before hitting the build stage and registering it with AWS EC2 as Amazon FPGA Image (AFI). AWS FPGA HDK comes with a shell simulation model that supports RTL-level simulation using Xilinx' Vivado XSIM,  MentorGraphics' Questa, Cadence Incisive and Synopsys' VCS RTL simulators. See table below for supported simulator versions. 
 
-| Simulator | Vivado 2017.4 | Vivado 2018.2 | Vivado 2018.3 | Vivado 2019.1 |
-|--------------------------|--------------------|--------------------|--------------------|---|
-| Xilinx Vivado XSIM | Vivado v2017.4 | Vivado v2018.2 | Vivado v2018.3 |Vivado v2019.1 |
-| Synopsys VCS | M-2017.03-SP2-11 | N-2017.12-SP1-1 | N-2017.12-SP2 | O-2018.09 |
-| Mentor Graphics Questa | 10.6b | 10.6c_1 | 10.6c_1 | 10.7c |
-| Cadence Incisive Enterprise Simulator(IES) | 15.20.063 | 15.20.063 | 15.20.063 | 15.20.065 |
+| Simulator | Vivado 2019.1 |  Vivado 2019.2 | Vivado 2020.1 | Vivado 2020.2 | 
+|-----------| --- | --- | --- | --- |
+| Xilinx Vivado XSIM | Vivado v2019.1 | Vivado v2019.2 | Vivado v2020.1 | Vivado v2020.2 |
+| Synopsys VCS | O-2018.09 | O-2018.09-SP2-1 | P-2019.06-SP1-1 | Q-2020.03 |
+| Mentor Graphics Questa | 10.7c | 2019.2 | 2019.4 | 2020.2 |
+| Cadence Incisive Enterprise Simulator(IES) | 15.20.065 | 15.20.073 | 15.20.079 | 15.20.083 |
 
 Developers can write their tests in SystemVerilog and/or C languages. If a developer chooses to use the supplied C framework, he/she can use the same C code for simulation and for runtime on your FPGA-enabled instance like F1.
 
diff --git a/hdk/docs/images/AWS_Shell_CL_overview.jpg b/hdk/docs/images/AWS_Shell_CL_overview.jpg
old mode 100755
new mode 100644
index 3369a711..cd1508ea
Binary files a/hdk/docs/images/AWS_Shell_CL_overview.jpg and b/hdk/docs/images/AWS_Shell_CL_overview.jpg differ
diff --git a/hdk/hdk_version.txt b/hdk/hdk_version.txt
index cc4e772e..8d821ae0 100644
--- a/hdk/hdk_version.txt
+++ b/hdk/hdk_version.txt
@@ -1 +1 @@
-HDK_VERSION=1.4.17
+HDK_VERSION=1.4.18
diff --git a/hdk/tests/simulation_tests/run_sim.sh b/hdk/tests/simulation_tests/run_sim.sh
index b4b9a083..af00f668 100755
--- a/hdk/tests/simulation_tests/run_sim.sh
+++ b/hdk/tests/simulation_tests/run_sim.sh
@@ -63,7 +63,10 @@ done
 
 vivado_version=${vivado_version//./_}
 if [ $batch == "TRUE" ]; then
-COMMAND="batch_submit.py -q vcs-lo --jd Cad-centos7_2 --jn github_regress_${test_name}_${test_type}_${vivado_version}_${simulator} --wait --echo -c make"
+# COMMAND="batch_submit.py -q vcs-lo --jd Cad-centos7_2 --jn github_regress_${test_name}_${test_type}_${vivado_version}_${simulator} --wait --echo -c make"
+# COMMAND="sbatch -c 1 --mem 64GB -p regress -J github_regress_${test_name}_${test_type}_${vivado_version}_${simulator} -L VCSMXRunTime_Net -W -o ${test_name}_${test_type}_${simulator}.stdout.sim.log -e ${test_name}_${test_type}_${simulator}.stderr.sim.log sbatch_wrap.sh make"
+COMMAND="srun -c 1 --mem 64GB -p regress -J github_regress_${test_name}_${test_type}_${vivado_version}_${simulator} -L VCSMXRunTime_Net make"
+
 else
 COMMAND="make"
 fi
diff --git a/hdk/tests/simulation_tests/test_sims.py b/hdk/tests/simulation_tests/test_sims.py
index 0c725c49..9e526d3d 100644
--- a/hdk/tests/simulation_tests/test_sims.py
+++ b/hdk/tests/simulation_tests/test_sims.py
@@ -39,7 +39,7 @@
 class TestSims(AwsFpgaTestBase):
     """
     Pytest test class.
-    
+
     NOTE: Cannot have an __init__ method.
     """
 
@@ -197,7 +197,7 @@ def test_cl_dram_dma__dram_dma_axi_mstr__sv(self, simulator, batch):
         test_dir = self.WORKSPACE + '/hdk/cl/examples/cl_dram_dma/verif/scripts'
         test_name = 'test_dram_dma_axi_mstr'
         test_type = 'sv'
-        
+
         self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, simulator=simulator, batch=batch)
 
     def test_cl_dram_dma__dram_dma_rnd__sv(self, simulator, batch):
@@ -599,8 +599,8 @@ def test_cl_uram_example__uram_example__c(self, simulator, batch):
         test_name = 'test_uram_example'
         test_type = 'c'
 
-        self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, simulator=simulator, batch=batch)    
-    
+        self.run_sim(test_dir=test_dir, test_name=test_name, test_type=test_type, simulator=simulator, batch=batch)
+
     # cl_dram_dma c
 
     def test_cl_dram_dma__sda__sv(self, simulator, batch):
diff --git a/hdk/tests/test_gen_dcp.py b/hdk/tests/test_gen_dcp.py
index 24ba04ad..e1c7e764 100644
--- a/hdk/tests/test_gen_dcp.py
+++ b/hdk/tests/test_gen_dcp.py
@@ -71,7 +71,7 @@ def set_allowed_warnings(cls):
         cls.allowed_warnings = (
             (('.*',), r'^WARNING: \[Constraints 18-838\] Failed to create SRL placer macro for cell SH/SH/MGT_TOP.*'),
             (('.*',), r'^WARNING: \[Shape Builder 18-838\] Failed to create SRL placer macro for cell WRAPPER_INST/SH/SH/MGT_TOP.*'),
-	    (('.*',), r'^WARNING: \[Common 17-576\] \'fanout_opt\' is deprecated.*'),
+	        (('.*',), r'^WARNING: \[Common 17-576\] \'fanout_opt\' is deprecated.*'),
             (('.*',), r'^CRITICAL WARNING: \[Place 30-823\] Failed to process clock nets that should have matching clock routes\. Reason: Found incompatible user defined or fixed clock roots for related clocks \'CL/SH_DDR/ddr_cores\.DDR4'),
             (('.*',), r'^CRITICAL WARNING: \[Constraints 18-850\] Failed to place register with ASYNC_REG property shape that starts with register SH/SH/MGT_TOP/SH_ILA_0/inst/ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer\.arm_in_transfer_inst/dout_reg0_reg\. '),
             (('.*',), r'^CRITICAL WARNING: \[Constraints 18-850\] Failed to place register with ASYNC_REG property shape that starts with register SH/SH/MGT_TOP/SH_ILA_0/inst/ila_core_inst/capture_qual_ctrl_2_reg\[0\]\. '),
@@ -84,7 +84,7 @@ def set_allowed_warnings(cls):
             (('.*',), r'^CRITICAL WARNING: \[Opt 31-430\].*'),
             (('.*',), r'WARNING: \[Vivado 12-3731\].*'),
             (('.*',), r'WARNING: \[Constraints 18-619\] A clock with name \'CLK_300M_DIMM._DP\'.*'),
-	    (('.*',), r'WARNING: \[Constraints 18-5648\] .*'),
+	        (('.*',), r'WARNING: \[Constraints 18-5648\] .*'),
             (('.*',), r'WARNING: \[Vivado_Tcl 4-391\] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.*'),
             (('.*',), r'WARNING: \[DRC RPBF-3\] IO port buffering.*'),
             (('.*',), r'WARNING: \[Place 46-14\] The placer has determined that this design is highly congested and may have difficulty routing. Run report_design_analysis -congestion for a detailed report\.'),
@@ -96,8 +96,10 @@ def set_allowed_warnings(cls):
             (('.*',), r'WARNING: \[Synth 8-689\] .*'),
             (('.*',), r'WARNING: \[Synth 8-6896\] .*'),
             (('.*',), r'WARNING: \[Synth 8-7023\] .*'),
-	    (('.*',), r'WARNING: \[Synth 8-7071\] .*'),
-	    (('.*',), r'WARNING: \[Synth 8-7129\] .*'),
+            (('.*',), r'CRITICAL WARNING: \[DRC HDPR-113\] Check for INOUT ports in RP: Reconfigurable module WRAPPER_INST/SH contains an INOUT port named .*'),
+            (('.*',), r'WARNING: \[Synth 8-7071\] .*'),
+	        (('.*',), r'WARNING: \[Synth 8-7129\] .*'),
+            (('.*',), r'WARNING: \[Route 35-3387\] .*'),
             (('cl_sde_*',), r'WARNING: \[Vivado 12-180\] No cells matched .*'),
             (('cl_sde_*',), r'WARNING: \[Vivado 12-1008\] No clocks found for command.*'),
             (('cl_sde_*',), r'CRITICAL WARNING: \[Designutils 20-1280\] .*'),
@@ -123,6 +125,8 @@ def set_allowed_warnings(cls):
             (('.*',), r'WARNING: \[Memdata 28-146\] Could not find a netlist instance for the specified SCOPED_TO_REF value of: bd_bf3f'),
             (('cl_dram_dma_*',), r'WARNING: \[Place 46-14\] The placer has determined'),
             (('cl_dram_dma_*',), r'WARNING: \[Synth 8-5856\]*'),
+            (('cl_dram_dma_*',), r'WARNING: \[Physopt 32-894\].*'),
+            (('cl_dram_dma_*',), r'CRITICAL WARNING: \[Vivado 12-1433\] Expecting a non-empty list of cells to be added to the pblock.*'),
             (('cl_hello_world_vhdl_A.*',), r'WARNING: \[Memdata 28-146\] Could not find a netlist instance for the specified SCOPED_TO_REF value of: ddr4_core'),
             (('cl_hello_world_vhdl_A.*',), r'WARNING: \[Memdata 28-146\] Could not find a netlist instance for the specified SCOPED_TO_REF value of: bd_bf3f'),
             (('cl_hello_world_vhdl_A.*',), r'CRITICAL WARNING: \[Designutils 20-1280\] Could not find module \'bd_bf3f_microblaze_I_0\''),
diff --git a/sdk/linux_kernel_drivers/xdma/xdma_install.md b/sdk/linux_kernel_drivers/xdma/xdma_install.md
index b0803b3f..30b440f4 100644
--- a/sdk/linux_kernel_drivers/xdma/xdma_install.md
+++ b/sdk/linux_kernel_drivers/xdma/xdma_install.md
@@ -194,12 +194,12 @@ DEVAMI 1.5.0 or Later instances come with preinstalled Xilinx Runtime Environmen
  lsmod | grep xocl
  
  ```
- To Remove XOCL driver
+ To Remove XRT and XOCL driver
  
  ```
- sudo rmmod xocl
- 
+ sudo systemctl stop mpd
+ sudo yum remove -y xrt xrt-aws
  ```
 
- XDMA driver install can proceed once XOCL driver is removed.
+ XDMA driver install can proceed once XRT is removed.
  
diff --git a/supported_vivado_versions.txt b/supported_vivado_versions.txt
index 26e509fb..261b08e1 100644
--- a/supported_vivado_versions.txt
+++ b/supported_vivado_versions.txt
@@ -7,3 +7,4 @@ Vivado v2019.2 (64-bit)
 Vivado v2019.2_AR73068_op (64-bit)
 Vivado v2019.2_AR73068 (64-bit)
 Vivado v2020.1 (64-bit)
+Vivado v2020.2 (64-bit)
diff --git a/vitis_runtime_setup.sh b/vitis_runtime_setup.sh
index c6fb0681..68af3c6b 100644
--- a/vitis_runtime_setup.sh
+++ b/vitis_runtime_setup.sh
@@ -152,7 +152,7 @@ check_kernel_ver
 check_xdma_driver
 check_edma_driver
 
-if [[ "$VIVADO_TOOL_VERSION" =~ .*2019\.2.*  || "$VIVADO_TOOL_VERSION" =~ .*2020\.1.* ]]; then
+if [[ "$VIVADO_TOOL_VERSION" =~ .*2019\.2.*  || "$VIVADO_TOOL_VERSION" =~ .*2020\.1.* || "$VIVADO_TOOL_VERSION" =~ .*2020\.2.* ]]; then
     info_msg "Xilinx Vivado version is $VIVADO_TOOL_VERSION"
     
     if [ $override == 1 ]; then
@@ -193,7 +193,7 @@ if [[ "$VIVADO_TOOL_VERSION" =~ .*2019\.2.*  || "$VIVADO_TOOL_VERSION" =~ .*2020
        return 1
     fi
 else
-   err_msg "Xilinx Vivado version is $VIVADO_TOOL_VERSION , only 2019.2 or 2020.1 are supported for Vitis "
+   err_msg "Xilinx Vivado version is $VIVADO_TOOL_VERSION , only 2019.2, 2020.1 or 2020.2 are supported for Vitis "
    return 1
 fi
 
diff --git a/vitis_setup.sh b/vitis_setup.sh
index 9d79d3ac..37848da7 100644
--- a/vitis_setup.sh
+++ b/vitis_setup.sh
@@ -171,7 +171,7 @@ setup_patches
 
 # Update Xilinx Vitis Examples from GitHub
 info_msg "Using Vitis $RELEASE_VER"
-if [[ $RELEASE_VER =~ .*2019\.2.*  ||  $RELEASE_VER =~ .*2020\.1.* ]]; then
+if [[ $RELEASE_VER =~ .*2019\.2.*  ||  $RELEASE_VER =~ .*2020\.1.* ||  $RELEASE_VER =~ .*2020\.2.* ]]; then
     info_msg "Updating Xilinx Vitis Examples $RELEASE_VER"
     git submodule update --init -- Vitis/examples/xilinx_$RELEASE_VER
     export VIVADO_TOOL_VER=$RELEASE_VER
@@ -183,7 +183,7 @@ if [[ $RELEASE_VER =~ .*2019\.2.*  ||  $RELEASE_VER =~ .*2020\.1.* ]]; then
     fi
     ln -sf $VITIS_DIR/examples/xilinx_$RELEASE_VER $VITIS_DIR/examples/xilinx
 else
-   echo " $RELEASE_VER is not supported (2019.2 or 2020.1 is supported).\n"
+   echo " $RELEASE_VER is not supported (2019.2, 2020.1 or 2020.2 are supported).\n"
    return 2
 fi