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at91sam9x5.dtsi
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at91sam9x5.dtsi
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/*
* at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
* applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
* AT91SAM9X25, AT91SAM9X35 SoC
*
* Copyright (C) 2012 Atmel,
* 2012 Nicolas Ferre <[email protected]>
*
* Licensed under GPLv2 or later.
*/
/include/ "skeleton.dtsi"
/ {
model = "Atmel AT91SAM9x5 family SoC";
compatible = "atmel,at91sam9x5";
interrupt-parent = <&aic>;
aliases {
serial0 = &dbgu;
serial1 = &usart0;
serial2 = &usart1;
serial3 = &usart2;
serial4 = &usart3;
gpio0 = &pioA;
gpio1 = &pioB;
gpio2 = &pioC;
gpio3 = &pioD;
tcb0 = &tcb0;
tcb1 = &tcb1;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
};
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
};
};
memory {
reg = <0x20000000 0x10000000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
spi0: spi@f0000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9x5-spi";
reg = <0xf0000000 0x100>;
interrupts = <13 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
dma-mask = <0xffffffff>;
dma = <&dma0 0x10002212>;
status = "disabled";
};
rtc@fffffeb0 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffeb0 0x40>;
interrupts = <1 4 7>;
};
spi1: spi@f0004000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9x5-spi";
reg = <0xf0004000 0x100>;
interrupts = <14 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
dma-mask = <0xffffffff>;
dma = <&dma1 0x10002212>;
status = "disabled";
};
mmc0: mmc@f0008000 {
compatible = "atmel,hsmci";
reg = <0xf0008000 0x600>;
interrupts = <12 4 0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
dma = <&dma0 0x10002200>;
pinctrl-names = "default";
};
mmc1: mmc@f000c000 {
compatible = "atmel,hsmci";
reg = <0xf000c000 0x600>;
interrupts = <26 4 0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
dma = <&dma1 0x10002200>;
pinctrl-names = "default";
};
ssc0: ssc@f0010000 {
compatible = "atmel,at91sam9g45-ssc";
reg = <0xf0010000 0x4000>;
interrupts = <28 4 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
dma = <&dma0 0x100022de>;
status = "disabled";
};
can0: can@f8000000 {
compatible = "atmel,at91sam9x5-can";
reg = <0xf8000000 0x300>;
interrupts = <29 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_rx_tx>;
status = "disabled";
};
can1: can@f8004000 {
compatible = "atmel,at91sam9x5-can";
reg = <0xf8004000 0x300>;
interrupts = <30 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_rx_tx>;
status = "disabled";
};
tcb0: timer@f8008000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 4 0>;
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 4 0>;
};
i2c0: i2c@f8010000 {
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8010000 0x100>;
interrupts = <9 4 6>;
dma = <&dma0 0x10002278>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
status = "disabled";
};
i2c1: i2c@f8014000 {
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8014000 0x100>;
interrupts = <10 4 6>;
dma = <&dma1 0x10002256>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "disabled";
};
i2c2: i2c@f8018000 {
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8018000 0x100>;
interrupts = <11 4 6>;
dma = <&dma0 0x1000229A>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "disabled";
};
usart0: serial@f801c000 {
compatible = "atmel,at91sam9x5-usart";
reg = <0xf801c000 0x200>;
interrupts = <5 4 5>;
atmel,use-dma-rx;
dma-rx = <&dma0 0x20000204>;
atmel,use-dma-tx;
dma-tx = <&dma0 0x10002030>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0
&pinctrl_usart0_rts_cts>;
status = "disabled";
};
usart1: serial@f8020000 {
compatible = "atmel,at91sam9x5-usart";
reg = <0xf8020000 0x200>;
interrupts = <6 4 5>;
atmel,use-dma-rx;
dma-rx = <&dma0 0x20000206>;
atmel,use-dma-tx;
dma-tx = <&dma0 0x10002050>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1
&pinctrl_usart1_rts_cts>;
status = "disabled";
};
usart2: serial@f8024000 {
compatible = "atmel,at91sam9x5-usart";
reg = <0xf8024000 0x200>;
interrupts = <7 4 5>;
atmel,use-dma-rx;
dma-rx = <&dma1 0x2000020d>;
atmel,use-dma-tx;
dma-tx = <&dma1 0x100020c0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
status = "disabled";
};
usart3: serial@f8028000 {
compatible = "atmel,at91sam9x5-usart";
reg = <0xf8028000 0x200>;
interrupts = <8 4 5>;
atmel,use-dma-rx;
dma-rx = <&dma1 0x2000020f>;
atmel,use-dma-tx;
dma-tx = <&dma1 0x100020e0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3
&pinctrl_usart3_rts_cts>;
status = "disabled";
};
macb0: ethernet@f802c000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
interrupts = <24 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
status = "disabled";
};
macb1: ethernet@f8030000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xf8030000 0x100>;
interrupts = <27 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb1_rmii>;
status = "disabled";
};
lcd_bus@f8038000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91sam9x5-lcd-bus", "simple-bus";
ranges = <0xf8038000 0xf8038000 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
status = "disabled";
lcd@f8038000 {
compatible = "atmel,at91sam9x5-lcd";
reg = <0xf8038000 0xff
0xf8038400 0x3ff>;
interrupts = <25 4 3>;
status = "disabled";
};
lcdovl1@f8038100 {
compatible = "atmel,at91sam9x5-lcd";
reg = <0xf8038100 0xff
0xf8038800 0x3ff>;
status = "disabled";
};
lcdheo1@f8038280 {
compatible = "atmel,at91sam9x5-heo";
reg = <0xf8038280 0xbf>;
interrupts = <25 4 3>;
status = "disabled";
};
};
tsadcc: tsadcc@f804c000 {
compatible = "atmel,at91sam9x5-tsadcc";
reg = <0xf804c000 0x4000>;
interrupts = <19 4 5>;
atmel,tsadcc_clock = <300000>;
atmel,filtering_average = <0x03>;
atmel,pendet_debounce = <0x08>;
atmel,pendet_sensitivity = <0x02>;
atmel,ts_sample_hold_time = <0x0a>;
status = "disabled";
};
adc0: adc@f804c000 {
compatible = "atmel,at91sam9260-adc";
reg = <0xf804c000 0x100>;
interrupts = <19 4 0>;
pinctrl-names = "default";
atmel,adc-use-external;
atmel,adc-num-channels = <12>;
atmel,adc-startup-time = <40>;
atmel,adc-channel-base = <0x50>;
atmel,adc-drdy-mask = <0x1000000>;
atmel,adc-status-register = <0x30>;
atmel,adc-trigger-register = <0xc0>;
atmel,adc-res = <8 10>;
atmel,adc-res-names = "lowres", "highres";
status = "disabled";
trigger@0 {
trigger-name = "external-rising";
trigger-value = <0x1>;
trigger-external;
};
trigger@1 {
trigger-name = "external-falling";
trigger-value = <0x2>;
trigger-external;
};
trigger@2 {
trigger-name = "external-any";
trigger-value = <0x3>;
trigger-external;
};
trigger@3 {
trigger-name = "continuous";
trigger-value = <0x6>;
};
};
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
};
dma0: dma-controller@ffffec00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <20 4 0>;
#dma-cells = <1>;
};
dma1: dma-controller@ffffee00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffee00 0x200>;
interrupts = <21 4 0>;
#dma-cells = <1>;
};
aic: interrupt-controller@fffff000 {
#interrupt-cells = <3>;
compatible = "atmel,at91rm9200-aic";
interrupt-controller;
reg = <0xfffff000 0x200>;
atmel,external-irqs = <31>;
};
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9x5-usart";
reg = <0xfffff200 0x200>;
interrupts = <1 4 7>;
/*atmel,use-dma-rx;
dma-rx = <&dma1 0x20000209>;*/
atmel,use-dma-tx;
dma-tx = <&dma1 0x10002080>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
status = "disabled";
};
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
/* shared pinctrl settings */
adc0 {
pinctrl_adc0_adtrg: adc0_adtrg {
atmel,pins =
<1 18 0x2 0x0>; /* PB18 periph B ADTRG */
};
/*
* Hardware don't care about the following pin configurations
* but it has to be done to prevent pin request from other drivers.
*/
pinctrl_adc0_ad0: adc0_ad0 {
atmel,pins =
<1 11 0x1 0x0>; /* PB11 alternate AD0 */
};
pinctrl_adc0_ad1: adc0_ad1 {
atmel,pins =
<1 12 0x1 0x0>; /* PB12 alternate AD1 */
};
pinctrl_adc0_ad2: adc0_ad2 {
atmel,pins =
<1 13 0x1 0x0>; /* PB13 alternate AD2 */
};
pinctrl_adc0_ad3: adc0_ad3 {
atmel,pins =
<1 14 0x1 0x0>; /* PB14 alternate AD3 */
};
pinctrl_adc0_ad4: adc0_ad4 {
atmel,pins =
<1 15 0x1 0x0>; /* PB15 alternate AD4 */
};
pinctrl_adc0_ad5: adc0_ad5 {
atmel,pins =
<1 16 0x1 0x0>; /* PB16 alternate AD5 */
};
pinctrl_adc0_ad6: adc0_ad6 {
atmel,pins =
<1 17 0x1 0x0>; /* PB17 alternate AD6 */
};
pinctrl_adc0_ad7: adc0_ad7 {
atmel,pins =
<1 6 0x1 0x0>; /* PB6 alternate AD7 */
};
pinctrl_adc0_ad8: adc0_ad8 {
atmel,pins =
<1 7 0x1 0x0>; /* PB7 alternate AD8 */
};
pinctrl_adc0_ad9: adc0_ad9 {
atmel,pins =
<1 8 0x1 0x0>; /* PB8 alternate AD9 */
};
pinctrl_adc0_ad10: adc0_ad10 {
atmel,pins =
<1 9 0x1 0x0>; /* PB9 alternate AD10 */
};
pinctrl_adc0_ad11: adc0_ad11 {
atmel,pins =
<1 10 0x1 0x0>; /* PB10 alternate AD11 */
};
};
can0 {
pinctrl_can0_rx_tx: can0_rx_tx {
atmel,pins =
<0 9 0x2 0x0 /* PA9 periph B CANRX0 */
0 10 0x2 0x0>; /* PA10 periph B CANTX0 */
};
};
can1 {
pinctrl_can1_rx_tx: can1_rx_tx {
atmel,pins =
<0 5 0x2 0x0 /* PA5 periph B CANTX1 */
0 6 0x2 0x0>; /* PA6 periph B CANRX1 */
};
};
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<0 9 0x1 0x0 /* PA9 periph A */
0 10 0x1 0x1>; /* PA10 periph A with pullup */
};
};
macb0 {
pinctrl_macb0_rmii: macb0_rmii-0 {
atmel,pins =
<1 0 0x1 0x0 /* PB0 periph A ERX0 */
1 1 0x1 0x0 /* PB1 periph A ERX1 */
1 2 0x1 0x0 /* PB2 periph A ERXER */
1 3 0x1 0x0 /* PB3 periph A ERXDV */
1 4 0x1 0x0 /* PB4 periph A ETXCK */
1 5 0x1 0x0 /* PB5 periph A EMDIO */
1 6 0x1 0x0 /* PB6 periph A EMDC */
1 7 0x1 0x0 /* PB7 periph A ETXEN */
1 9 0x1 0x0 /* PB9 periph A ETX0 */
1 10 0x1 0x0>; /* PB10 periph A ETX1 */
};
};
macb1 {
pinctrl_macb1_rmii: macb1_rmii-0 {
atmel,pins =
<2 20 0x2 0x0 /* PC20 periph B E1_RX0 */
2 21 0x2 0x0 /* PC21 periph B E1_RX1 */
2 16 0x2 0x0 /* PC16 periph B E1_RXER */
2 28 0x2 0x0 /* PC28 periph B E1_CRSDV */
2 29 0x2 0x0 /* PC29 periph B E1_TXCK */
2 31 0x2 0x0 /* PC31 periph B E1_MDIO */
2 30 0x2 0x0 /* PC30 periph B E1_MDC */
2 27 0x2 0x0 /* PC27 periph B E1_TXEN */
2 18 0x2 0x0 /* PC18 periph B E1_TX0 */
2 19 0x2 0x0>; /* PC19 periph B E1_TX1 */
};
};
spi0 {
pinctrl_spi0: spi0-0 {
atmel,pins =
<0 11 0x1 0x0 /* PA11 periph A SPI0_MISO */
0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI */
0 13 0x1 0x0 /* PA13 periph A SPI0_SPCK */
0 14 0x1 0x0>; /* PA14 periph A SPI0_NPCS0 */
};
};
spi1 {
pinctrl_spi1: spi1-0 {
atmel,pins =
<0 21 0x2 0x0 /* PA21 periph B SPI1_MISO */
0 22 0x2 0x0 /* PA12 periph B SPI1_MOSI */
0 23 0x2 0x0 /* PA23 periph B SPI1_SPCK */
0 8 0x2 0x0>; /* PA8 periph B SPI1_NPCS0 */
};
};
ssc0 {
pinctrl_ssc0_tx: ssc0_tx {
atmel,pins =
<0 24 0x2 0x0 /* PA24 periph B TK */
0 25 0x2 0x0 /* PA25 periph B TF */
0 26 0x2 0x0>; /* PA26 periph B TD */
};
pinctrl_ssc0_rx: ssc0_rx {
atmel,pins =
<0 27 0x2 0x0 /* PA27 periph B RD */
0 28 0x2 0x0 /* PA28 periph B RK */
0 29 0x2 0x0>; /* PA29 periph B RF */
};
};
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
<0 0 0x1 0x1 /* PA0 periph A with pullup */
0 1 0x1 0x0>; /* PA1 periph A */
};
pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
atmel,pins =
<0 2 0x1 0x0 /* PA2 periph A */
0 3 0x1 0x0>; /* PA3 periph A */
};
};
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
<0 5 0x1 0x1 /* PA5 periph A with pullup */
0 6 0x1 0x0>; /* PA6 periph A */
};
pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
atmel,pins =
<2 27 0x3 0x0 /* PC27 periph C */
2 28 0x3 0x0>; /* PC28 periph C */
};
};
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
<0 7 0x1 0x1 /* PA7 periph A with pullup */
0 8 0x1 0x0>; /* PA8 periph A */
};
pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
atmel,pins =
<1 0 0x2 0x0 /* PB0 periph B */
1 1 0x2 0x0>; /* PB1 periph B */
};
};
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
<2 22 0x2 0x1 /* PC22 periph B with pullup */
2 23 0x2 0x0>; /* PC23 periph B */
};
pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
atmel,pins =
<2 24 0x2 0x0 /* PC24 periph B */
2 25 0x2 0x0>; /* PC25 periph B */
};
};
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
<2 8 0x3 0x0 /* PC8 periph C */
2 9 0x3 0x1>; /* PC9 periph C with pullup */
};
};
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
<2 16 0x3 0x0 /* PC16 periph C */
2 17 0x3 0x1>; /* PC17 periph C with pullup */
};
};
nand {
pinctrl_nand_rdy_enable: nand_rdy_enable-0 {
atmel,pins =
<3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up */
3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
};
pinctrl_nand_oe_we_ale_cle: nand_oe_we_ale_cle-0 {
atmel,pins =
<3 0 0x1 0x1 /* PD0 periph A with pullup */
3 1 0x1 0x1 /* PD1 periph A with pullup */
3 2 0x1 0x1 /* PD2 periph A with pullup */
3 3 0x1 0x1>; /* PD3 periph A with pullup */
};
pinctrl_nand_bus_on_d16_8bit: nand_bus_on_d16_8bit-0 {
atmel,pins =
<3 6 0x1 0x1 /* PD6 periph A with pullup */
3 7 0x1 0x1 /* PD7 periph A with pullup */
3 8 0x1 0x1 /* PD8 periph A with pullup */
3 9 0x1 0x1 /* PD9 periph A with pullup */
3 10 0x1 0x1 /* PD10 periph A with pullup */
3 11 0x1 0x1 /* PD11 periph A with pullup */
3 12 0x1 0x1 /* PD12 periph A with pullup */
3 13 0x1 0x1>; /* PD13 periph A with pullup */
};
pinctrl_nand_bus_on_d16_16bit: nand_bus_on_d16_16bit-0 {
atmel,pins =
<3 14 0x1 0x1 /* PD14 periph A with pullup */
3 15 0x1 0x1 /* PD15 periph A with pullup */
3 16 0x1 0x1 /* PD16 periph A with pullup */
3 17 0x1 0x1 /* PD17 periph A with pullup */
3 18 0x1 0x1 /* PD18 periph A with pullup */
3 19 0x1 0x1 /* PD19 periph A with pullup */
3 20 0x1 0x1 /* PD20 periph A with pullup */
3 21 0x1 0x1>; /* PD21 periph A with pullup */
};
};
i2c0 {
pinctrl_i2c0: i2c0-0 {
atmel,pins =
<0 30 0x1 0x0 /* PA30 periph A TWD0 */
0 31 0x1 0x0>; /* PA31 periph A TWCK0 */
};
};
i2c1 {
pinctrl_i2c1: i2c1-0 {
atmel,pins =
<2 0 0x3 0x0 /* PC0 periph C TWD1 */
2 1 0x3 0x0>; /* PC1 periph C TWCK1 */
};
};
i2c2 {
pinctrl_i2c2: i2c2-0 {
atmel,pins =
<1 4 0x2 0x0 /* PB4 periph B TWD2 */
1 5 0x2 0x0>; /* PB5 periph B TWCK2 */
};
};
mmc0 {
pinctrl_mmc0_clk_cmd_dat0: mm0_clk_cmd_dat0 {
atmel,pins =
<0 17 0x1 0x0 /* PA17 periph A */
0 16 0x1 0x1 /* PA16 periph A with pullpup */
0 15 0x1 0x1>; /* PA15 periph A with pullpup */
};
pinctrl_mmc0_dat1_3: mm0_dat1_3 {
atmel,pins =
<0 18 0x1 0x1 /* PA18 periph A with pullpup */
0 19 0x1 0x1 /* PA19 periph A with pullpup */
0 20 0x1 0x1>; /* PA20 periph A with pullpup */
};
};
mmc1 {
pinctrl_mmc1_clk_cmd_dat0: mm1_clk_cmd_dat0 {
atmel,pins =
<0 13 0x2 0x0 /* PA13 periph B */
0 12 0x2 0x1 /* PA12 periph B with pullpup */
0 11 0x2 0x1>; /* PA11 periph B with pullpup */
};
pinctrl_mmc1_dat1_3: mm1_dat1_3 {
atmel,pins =
<0 2 0x2 0x1 /* PA2 periph B with pullpup */
0 3 0x2 0x1 /* PA3 periph B with pullpup */
0 4 0x2 0x1>; /* PA4 periph B with pullpup */
};
};
lcd {
pinctrl_lcd: lcd-0 {
atmel,pins =
<2 26 0x1 0x1 /* PC26 periph A */
2 27 0x1 0x1 /* PC27 periph A */
2 28 0x1 0x1 /* PC28 periph A */
2 24 0x1 0x1 /* PC24 periph A */
2 29 0x1 0x1 /* PC29 periph A */
2 30 0x1 0x1 /* PC30 periph A */
2 0 0x1 0x1 /* PC0 periph A */
2 1 0x1 0x1 /* PC1 periph A */
2 2 0x1 0x1 /* PC2 periph A */
2 3 0x1 0x1 /* PC3 periph A */
2 4 0x1 0x1 /* PC4 periph A */
2 5 0x1 0x1 /* PC5 periph A */
2 6 0x1 0x1 /* PC6 periph A */
2 7 0x1 0x1 /* PC7 periph A */
2 8 0x1 0x1 /* PC8 periph A */
2 9 0x1 0x1 /* PC9 periph A */
2 10 0x1 0x1 /* PC10 periph A */
2 11 0x1 0x1 /* PC11 periph A */
2 12 0x1 0x1 /* PC12 periph A */
2 13 0x1 0x1 /* PC13 periph A */
2 14 0x1 0x1 /* PC14 periph A */
2 15 0x1 0x1 /* PC15 periph A */
2 16 0x1 0x1 /* PC16 periph A */
2 17 0x1 0x1 /* PC17 periph A */
2 18 0x1 0x1 /* PC18 periph A */
2 19 0x1 0x1 /* PC19 periph A */
2 20 0x1 0x1 /* PC20 periph A */
2 21 0x1 0x1 /* PC21 periph A */
2 22 0x1 0x1 /* PC22 periph A */
2 23 0x1 0x1>; /* PC23 periph A */
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 4 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <2 4 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <19>;
interrupt-controller;
#interrupt-cells = <2>;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <3 4 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <3 4 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
};
rstc@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
};
shdwc@fffffe10 {
compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfffffe10 0x10>;
};
pit: timer@fffffe30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 4 7>;
};
watchdog@fffffe40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffe40 0x10>;
status = "disabled";
};
};
nand0: nand@40000000 {
compatible = "atmel,at91rm9200-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x10000000
0xffffe000 0x600 /* PMECC Registers */
0xffffe600 0x200 /* PMECC Error Location Registers */
0x00100000 0x100000 /* ROM code */
>;
atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_rdy_enable &pinctrl_nand_oe_we_ale_cle>;
gpios = <&pioD 5 0
&pioD 4 0
0
>;
status = "disabled";
};
usb0: ohci@00600000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <22 4 2>;
status = "disabled";
};
usb1: ehci@00700000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <22 4 2>;
status = "disabled";
};
};
};