From dffbe48e9163f54a9316a8b80a88e1777f7b898e Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 2 Sep 2021 01:40:33 +0000 Subject: [PATCH 1/7] rcc: typo: clarify that we're setting the selected clock. It may or may not be the PLL clock. Signed-off-by: Karl Palsson --- src/rcc/mod.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index d86e1a1..0e6c90e 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -83,7 +83,7 @@ impl Rcc { }) }); - // Configure SYSCLK mux to use PLL clock + // Configure SYSCLK mux to use selected clock self.rb .cfgr .modify(|_r, w| unsafe { w.sw().bits(sysclk_bits) }); From 3bf59b0956039050f3e27db95caabf44146d8fba Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 3 Sep 2021 12:23:08 +0000 Subject: [PATCH 2/7] deps: semihosting isn't a dependency of the hal, only the demos Signed-off-by: Karl Palsson --- Cargo.toml | 1 - 1 file changed, 1 deletion(-) diff --git a/Cargo.toml b/Cargo.toml index 4d72e96..6bc3317 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -26,7 +26,6 @@ embedded-dma = "0.1" nb = "0.1.1" stm32wb-pac = "0.2" as-slice = "0.1" -cortex-m-semihosting = { version = "0.3.5", features = ["jlink-quirks"] } bit_field = "0.10.0" heapless = "0.5.3" From f0b71d18a5730534549868e414785a54a0f98037 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 3 Sep 2021 12:23:27 +0000 Subject: [PATCH 3/7] docs.rs support building by choosing all features Fixes: https://github.com/eupn/stm32wb-hal/issues/13 Signed-off-by: Karl Palsson --- Cargo.toml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Cargo.toml b/Cargo.toml index 6bc3317..fa5806e 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -81,3 +81,6 @@ codegen-units = 1 codegen-units = 1 debug = true lto = true + +[package.metadata.docs.rs] +features = ["xG-package", "stm32-usbd"] From 6633057b198fe9fd1f31cdcc98505191a6539457 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 3 Sep 2021 12:23:54 +0000 Subject: [PATCH 4/7] deps: Update to latest cortex-m dependency No reason to stay on the older package, and easier for other applications to move forwards. Signed-off-by: Karl Palsson --- Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Cargo.toml b/Cargo.toml index fa5806e..c368734 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -21,7 +21,7 @@ exclude = [ edition = "2018" [dependencies] -cortex-m = "0.6.2" +cortex-m = "0.7" embedded-dma = "0.1" nb = "0.1.1" stm32wb-pac = "0.2" From dce8d18dbeac9a67c0f7b4804ef0192e7072be19 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 3 Sep 2021 13:39:03 +0000 Subject: [PATCH 5/7] Export FlashExt in prelude for consistency Fixes: https://github.com/eupn/stm32wb-hal/issues/15 Fixes: 28886ae5af Signed-off-by: Karl Palsson --- src/prelude.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/prelude.rs b/src/prelude.rs index 657303d..6ee9095 100644 --- a/src/prelude.rs +++ b/src/prelude.rs @@ -7,7 +7,7 @@ pub use embedded_hal::digital::v2::OutputPin; pub use crate::datetime::U32Ext as _stm32wb_hal_datetime_U32Ext; pub use crate::ipcc::IpccExt as _stm32wb_hal_ipcc_IpccExt; //pub use crate::dma::DmaExt as _stm32wb_hal_DmaExt; -//pub use crate::flash::FlashExt as _stm32wb_hal_FlashExt; +pub use crate::flash::FlashExt as _stm32wb_hal_FlashExt; pub use crate::gpio::GpioExt as _stm32wb_hal_GpioExt; pub use crate::pwm::PwmExt1 as _stm32l4_hal_PwmExt1; pub use crate::pwm::PwmExt2 as _stm32l4_hal_PwmExt2; From 1f4230757362003172dbacd6bc7acd303469133c Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 6 Sep 2021 11:11:25 +0000 Subject: [PATCH 6/7] rcc: fix HSE for sysclock. HSE wasn't actually being turned on, so even though the SW bits were set to HSE, the SWS bits never switched over, and we continued running from MSI. Fixes: https://github.com/eupn/stm32wb-hal/issues/16 Signed-off-by: Karl Palsson --- src/rcc/mod.rs | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index 0e6c90e..b42002d 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -51,12 +51,17 @@ impl Rcc { SysClkSrc::Msi(_msi_range) => todo!(), SysClkSrc::Hsi => todo!(), SysClkSrc::HseSys(hse_div) => { - self.clocks.hse = Some(HSE_FREQ.hz()); - - self.clocks.sysclk = match hse_div { - HseDivider::NotDivided => HSE_FREQ.hz(), - HseDivider::Div2 => (HSE_FREQ / 2).hz(), + // Actually turn on and use HSE.... + let (divided, f_input) = match hse_div { + HseDivider::NotDivided => (false, HSE_FREQ), + HseDivider::Div2 => (true, HSE_FREQ / 2), }; + self.rb.cr.modify(|_, w| w.hsepre().bit(divided).hseon().set_bit()); + // Wait for HSE startup + while !self.rb.cr.read().hserdy().bit_is_set() {} + + self.clocks.hse = Some(HSE_FREQ.hz()); + self.clocks.sysclk = f_input.hz(); 0b10 } From e7cf6196246a045828849539ea0df61c44c26932 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 6 Sep 2021 11:14:40 +0000 Subject: [PATCH 7/7] gpio: Make trigger edge edge naming consistent with L4 Use the same naming style as the L4 HAL, given that the WB is an L4 with a radio attached. This makes it easier to use l4 example code. Signed-off-by: Karl Palsson --- src/gpio.rs | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/src/gpio.rs b/src/gpio.rs index 1ec530e..e0012ba 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -95,12 +95,11 @@ pub struct AF14; /// Alternate function 15 (type state) pub struct AF15; -#[allow(non_camel_case_types)] #[derive(Debug, PartialEq)] pub enum Edge { - RISING, - FALLING, - RISING_FALLING, + Rising, + Falling, + RisingFalling, } /// External Interrupt Pin @@ -318,15 +317,15 @@ macro_rules! gpio { /// Generate interrupt on rising edge, falling edge or both fn trigger_on_edge(&mut self, exti: &mut EXTI, edge: Edge) { match edge { - Edge::RISING => { + Edge::Rising => { exti.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.i)) }); exti.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.i)) }); }, - Edge::FALLING => { + Edge::Falling => { exti.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.i)) }); exti.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.i)) }); }, - Edge::RISING_FALLING => { + Edge::RisingFalling => { exti.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.i)) }); exti.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.i)) }); } @@ -583,15 +582,15 @@ macro_rules! gpio { /// Generate interrupt on rising edge, falling edge or both fn trigger_on_edge(&mut self, exti: &mut EXTI, edge: Edge) { match edge { - Edge::RISING => { + Edge::Rising => { exti.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << $i)) }); exti.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << $i)) }); }, - Edge::FALLING => { + Edge::Falling => { exti.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << $i)) }); exti.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << $i)) }); }, - Edge::RISING_FALLING => { + Edge::RisingFalling => { exti.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << $i)) }); exti.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << $i)) }); }