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chen.qian
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[Test] rename testcases and change sqrt/fird
1 parent 45f4abc commit e116ff0

15 files changed

+238
-238
lines changed

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/add.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_add_f32_ansi.ll

File renamed without changes.

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/addc.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_addc_f32_ansi.ll

File renamed without changes.

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/ccorr.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_ccorr_f32_ansi.ll

File renamed without changes.

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dotprod_template_complex.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_complicated_dotprod_f32_ansi.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
22
; RUN: opt -S -mtriple=riscv32-esp-unknown-elf -passes=riscv-loop-unroll-and-remainder -riscv-loop-unroll-and-remainder=true < %s | FileCheck %s
3-
define dso_local float @test_loop(ptr nocapture noundef readonly %data1, ptr nocapture noundef readonly %data2, i32 noundef %start_index, i32 noundef %end_index, i32 noundef %update1, i32 noundef %update2, float noundef %offset) local_unnamed_addr {
4-
; CHECK-LABEL: define dso_local float @test_loop(
3+
define dso_local float @dsps_complicated_dotprod_f32_ansi(ptr nocapture noundef readonly %data1, ptr nocapture noundef readonly %data2, i32 noundef %start_index, i32 noundef %end_index, i32 noundef %update1, i32 noundef %update2, float noundef %offset) local_unnamed_addr {
4+
; CHECK-LABEL: define dso_local float @dsps_complicated_dotprod_f32_ansi(
55
; CHECK-SAME: ptr noalias nocapture noundef readonly [[DATA1:%.*]], ptr noalias nocapture noundef readonly [[DATA2:%.*]], i32 noundef [[START_INDEX:%.*]], i32 noundef [[END_INDEX:%.*]], i32 noundef [[UPDATE1:%.*]], i32 noundef [[UPDATE2:%.*]], float noundef [[OFFSET:%.*]]) local_unnamed_addr {
66
; CHECK-NEXT: entry:
77
; CHECK-NEXT: [[INVARIANT_GEP:%.*]] = getelementptr float, ptr [[DATA1]], i32 [[UPDATE1]]

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/conv.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_conv_f32_ansi.ll

File renamed without changes.

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/corr.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_corr_f32_ansi.ll

File renamed without changes.

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dotprod.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_dotprod_f32_ansi.ll

File renamed without changes.

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dotprode.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_dotprode_f32_ansi.ll

File renamed without changes.

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/fir.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_fir_f32_ansi.ll

File renamed without changes.

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/fird.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_fird_f32_ansi.ll

+166-166
Large diffs are not rendered by default.

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/mul.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_mul_f32_ansi.ll

File renamed without changes.

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/mulc.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_mulc_f32_ansi.ll

File renamed without changes.

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/loopsecvconstant.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_simple_dotprod_f32_ansi.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
22
; RUN: opt -S -mtriple=riscv32-esp-unknown-elf -passes=riscv-loop-unroll-and-remainder -riscv-loop-unroll-and-remainder=true < %s | FileCheck %s
3-
define dso_local float @test_loop(ptr nocapture noundef readonly %data1, ptr nocapture noundef readonly %data2) local_unnamed_addr {
4-
; CHECK-LABEL: define dso_local float @test_loop(
3+
define dso_local float @dsps_simple_dotprod_f32_ansi(ptr nocapture noundef readonly %data1, ptr nocapture noundef readonly %data2) local_unnamed_addr {
4+
; CHECK-LABEL: define dso_local float @dsps_simple_dotprod_f32_ansi(
55
; CHECK-SAME: ptr noalias nocapture noundef readonly [[DATA1:%.*]], ptr noalias nocapture noundef readonly [[DATA2:%.*]]) local_unnamed_addr {
66
; CHECK-NEXT: entry:
77
; CHECK-NEXT: br label [[FOR_BODY:%.*]]

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/sqrt.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_sqrt_f32_ansi.ll

+68-68
Original file line numberDiff line numberDiff line change
@@ -19,130 +19,130 @@ define dso_local noundef i32 @dsps_sqrt_f32_ansi(ptr noundef readonly %input, pt
1919
; CHECK-NEXT: [[CMP6_NOT207:%.*]] = icmp ult i32 [[LEN]], 16
2020
; CHECK-NEXT: br i1 [[CMP6_NOT207]], label [[FOR_COND_PREHEADER_NEW2:%.*]], label [[FOR_BODY_MODIFY:%.*]]
2121
; CHECK: for.cond.preheader.new2:
22-
; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[TMP32:%.*]], [[FOR_BODY_MODIFY]] ], [ 0, [[FOR_COND_PREHEADER_NEW]] ]
22+
; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[TMP47:%.*]], [[FOR_BODY_MODIFY]] ], [ 0, [[FOR_COND_PREHEADER_NEW]] ]
2323
; CHECK-NEXT: [[CMP85209:%.*]] = icmp slt i32 [[TMP0]], [[LEN]]
2424
; CHECK-NEXT: br i1 [[CMP85209]], label [[FOR_BODY:%.*]], label [[RETURN]]
2525
; CHECK: for.body.modify:
26-
; CHECK-NEXT: [[I_012_MODIFY:%.*]] = phi i32 [ [[TMP32]], [[FOR_BODY_MODIFY]] ], [ 0, [[FOR_COND_PREHEADER_NEW]] ]
26+
; CHECK-NEXT: [[I_012_MODIFY:%.*]] = phi i32 [ [[TMP47]], [[FOR_BODY_MODIFY]] ], [ 0, [[FOR_COND_PREHEADER_NEW]] ]
2727
; CHECK-NEXT: [[ARRAYIDX_MODIFY:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[I_012_MODIFY]]
2828
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX_MODIFY]], align 4
2929
; CHECK-NEXT: [[SHR_I_MODIFY:%.*]] = ashr i32 [[TMP1]], 1
30-
; CHECK-NEXT: [[ADD48:%.*]] = or disjoint i32 [[SHR_I_MODIFY]], 532365312
30+
; CHECK-NEXT: [[ADD_I_MODIFY:%.*]] = add nsw i32 [[SHR_I_MODIFY]], 532365312
3131
; CHECK-NEXT: [[ARRAYIDX5_MODIFY:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[I_012_MODIFY]]
32-
; CHECK-NEXT: store i32 [[ADD48]], ptr [[ARRAYIDX5_MODIFY]], align 4
32+
; CHECK-NEXT: store i32 [[ADD_I_MODIFY]], ptr [[ARRAYIDX5_MODIFY]], align 4
3333
; CHECK-NEXT: [[ADD:%.*]] = or disjoint i32 [[I_012_MODIFY]], 1
3434
; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD]]
3535
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4
3636
; CHECK-NEXT: [[TMP3:%.*]] = ashr i32 [[TMP2]], 1
37-
; CHECK-NEXT: [[ADD50:%.*]] = or disjoint i32 [[TMP3]], 532365312
37+
; CHECK-NEXT: [[TMP4:%.*]] = add nsw i32 [[TMP3]], 532365312
3838
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD]]
39-
; CHECK-NEXT: store i32 [[ADD50]], ptr [[ARRAYIDX2]], align 4
39+
; CHECK-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX2]], align 4
4040
; CHECK-NEXT: [[ADD3:%.*]] = or disjoint i32 [[I_012_MODIFY]], 2
4141
; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD3]]
42-
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4
43-
; CHECK-NEXT: [[TMP5:%.*]] = ashr i32 [[TMP4]], 1
44-
; CHECK-NEXT: [[ADD52:%.*]] = or disjoint i32 [[TMP5]], 532365312
42+
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4
43+
; CHECK-NEXT: [[TMP6:%.*]] = ashr i32 [[TMP5]], 1
44+
; CHECK-NEXT: [[TMP7:%.*]] = add nsw i32 [[TMP6]], 532365312
4545
; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD3]]
46-
; CHECK-NEXT: store i32 [[ADD52]], ptr [[ARRAYIDX6]], align 4
46+
; CHECK-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX6]], align 4
4747
; CHECK-NEXT: [[ADD7:%.*]] = or disjoint i32 [[I_012_MODIFY]], 3
4848
; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD7]]
49-
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX8]], align 4
50-
; CHECK-NEXT: [[TMP7:%.*]] = ashr i32 [[TMP6]], 1
51-
; CHECK-NEXT: [[ADD54:%.*]] = or disjoint i32 [[TMP7]], 532365312
49+
; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX8]], align 4
50+
; CHECK-NEXT: [[TMP9:%.*]] = ashr i32 [[TMP8]], 1
51+
; CHECK-NEXT: [[TMP10:%.*]] = add nsw i32 [[TMP9]], 532365312
5252
; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD7]]
53-
; CHECK-NEXT: store i32 [[ADD54]], ptr [[ARRAYIDX9]], align 4
53+
; CHECK-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX9]], align 4
5454
; CHECK-NEXT: [[ADD10:%.*]] = or disjoint i32 [[I_012_MODIFY]], 4
5555
; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD10]]
56-
; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4
57-
; CHECK-NEXT: [[TMP9:%.*]] = ashr i32 [[TMP8]], 1
58-
; CHECK-NEXT: [[ADD56:%.*]] = or disjoint i32 [[TMP9]], 532365312
56+
; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4
57+
; CHECK-NEXT: [[TMP12:%.*]] = ashr i32 [[TMP11]], 1
58+
; CHECK-NEXT: [[TMP13:%.*]] = add nsw i32 [[TMP12]], 532365312
5959
; CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD10]]
60-
; CHECK-NEXT: store i32 [[ADD56]], ptr [[ARRAYIDX12]], align 4
60+
; CHECK-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX12]], align 4
6161
; CHECK-NEXT: [[ADD13:%.*]] = or disjoint i32 [[I_012_MODIFY]], 5
6262
; CHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD13]]
63-
; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX14]], align 4
64-
; CHECK-NEXT: [[TMP11:%.*]] = ashr i32 [[TMP10]], 1
65-
; CHECK-NEXT: [[ADD58:%.*]] = or disjoint i32 [[TMP11]], 532365312
63+
; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX14]], align 4
64+
; CHECK-NEXT: [[TMP15:%.*]] = ashr i32 [[TMP14]], 1
65+
; CHECK-NEXT: [[TMP16:%.*]] = add nsw i32 [[TMP15]], 532365312
6666
; CHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD13]]
67-
; CHECK-NEXT: store i32 [[ADD58]], ptr [[ARRAYIDX15]], align 4
67+
; CHECK-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX15]], align 4
6868
; CHECK-NEXT: [[ADD16:%.*]] = or disjoint i32 [[I_012_MODIFY]], 6
6969
; CHECK-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD16]]
70-
; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX17]], align 4
71-
; CHECK-NEXT: [[TMP13:%.*]] = ashr i32 [[TMP12]], 1
72-
; CHECK-NEXT: [[ADD60:%.*]] = or disjoint i32 [[TMP13]], 532365312
70+
; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARRAYIDX17]], align 4
71+
; CHECK-NEXT: [[TMP18:%.*]] = ashr i32 [[TMP17]], 1
72+
; CHECK-NEXT: [[TMP19:%.*]] = add nsw i32 [[TMP18]], 532365312
7373
; CHECK-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD16]]
74-
; CHECK-NEXT: store i32 [[ADD60]], ptr [[ARRAYIDX18]], align 4
74+
; CHECK-NEXT: store i32 [[TMP19]], ptr [[ARRAYIDX18]], align 4
7575
; CHECK-NEXT: [[ADD19:%.*]] = or disjoint i32 [[I_012_MODIFY]], 7
7676
; CHECK-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD19]]
77-
; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4
78-
; CHECK-NEXT: [[TMP15:%.*]] = ashr i32 [[TMP14]], 1
79-
; CHECK-NEXT: [[ADD62:%.*]] = or disjoint i32 [[TMP15]], 532365312
77+
; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4
78+
; CHECK-NEXT: [[TMP21:%.*]] = ashr i32 [[TMP20]], 1
79+
; CHECK-NEXT: [[TMP22:%.*]] = add nsw i32 [[TMP21]], 532365312
8080
; CHECK-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD19]]
81-
; CHECK-NEXT: store i32 [[ADD62]], ptr [[ARRAYIDX21]], align 4
81+
; CHECK-NEXT: store i32 [[TMP22]], ptr [[ARRAYIDX21]], align 4
8282
; CHECK-NEXT: [[ADD22:%.*]] = or disjoint i32 [[I_012_MODIFY]], 8
8383
; CHECK-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD22]]
84-
; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX23]], align 4
85-
; CHECK-NEXT: [[TMP17:%.*]] = ashr i32 [[TMP16]], 1
86-
; CHECK-NEXT: [[ADD64:%.*]] = or disjoint i32 [[TMP17]], 532365312
84+
; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX23]], align 4
85+
; CHECK-NEXT: [[TMP24:%.*]] = ashr i32 [[TMP23]], 1
86+
; CHECK-NEXT: [[TMP25:%.*]] = add nsw i32 [[TMP24]], 532365312
8787
; CHECK-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD22]]
88-
; CHECK-NEXT: store i32 [[ADD64]], ptr [[ARRAYIDX24]], align 4
88+
; CHECK-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX24]], align 4
8989
; CHECK-NEXT: [[ADD25:%.*]] = or disjoint i32 [[I_012_MODIFY]], 9
9090
; CHECK-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD25]]
91-
; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4
92-
; CHECK-NEXT: [[TMP19:%.*]] = ashr i32 [[TMP18]], 1
93-
; CHECK-NEXT: [[ADD66:%.*]] = or disjoint i32 [[TMP19]], 532365312
91+
; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4
92+
; CHECK-NEXT: [[TMP27:%.*]] = ashr i32 [[TMP26]], 1
93+
; CHECK-NEXT: [[TMP28:%.*]] = add nsw i32 [[TMP27]], 532365312
9494
; CHECK-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD25]]
95-
; CHECK-NEXT: store i32 [[ADD66]], ptr [[ARRAYIDX27]], align 4
95+
; CHECK-NEXT: store i32 [[TMP28]], ptr [[ARRAYIDX27]], align 4
9696
; CHECK-NEXT: [[ADD28:%.*]] = or disjoint i32 [[I_012_MODIFY]], 10
9797
; CHECK-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD28]]
98-
; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX29]], align 4
99-
; CHECK-NEXT: [[TMP21:%.*]] = ashr i32 [[TMP20]], 1
100-
; CHECK-NEXT: [[ADD68:%.*]] = or disjoint i32 [[TMP21]], 532365312
98+
; CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[ARRAYIDX29]], align 4
99+
; CHECK-NEXT: [[TMP30:%.*]] = ashr i32 [[TMP29]], 1
100+
; CHECK-NEXT: [[TMP31:%.*]] = add nsw i32 [[TMP30]], 532365312
101101
; CHECK-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD28]]
102-
; CHECK-NEXT: store i32 [[ADD68]], ptr [[ARRAYIDX30]], align 4
102+
; CHECK-NEXT: store i32 [[TMP31]], ptr [[ARRAYIDX30]], align 4
103103
; CHECK-NEXT: [[ADD31:%.*]] = or disjoint i32 [[I_012_MODIFY]], 11
104104
; CHECK-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD31]]
105-
; CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX32]], align 4
106-
; CHECK-NEXT: [[TMP23:%.*]] = ashr i32 [[TMP22]], 1
107-
; CHECK-NEXT: [[ADD70:%.*]] = or disjoint i32 [[TMP23]], 532365312
105+
; CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[ARRAYIDX32]], align 4
106+
; CHECK-NEXT: [[TMP33:%.*]] = ashr i32 [[TMP32]], 1
107+
; CHECK-NEXT: [[TMP34:%.*]] = add nsw i32 [[TMP33]], 532365312
108108
; CHECK-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD31]]
109-
; CHECK-NEXT: store i32 [[ADD70]], ptr [[ARRAYIDX33]], align 4
109+
; CHECK-NEXT: store i32 [[TMP34]], ptr [[ARRAYIDX33]], align 4
110110
; CHECK-NEXT: [[ADD34:%.*]] = or disjoint i32 [[I_012_MODIFY]], 12
111111
; CHECK-NEXT: [[ARRAYIDX35:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD34]]
112-
; CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[ARRAYIDX35]], align 4
113-
; CHECK-NEXT: [[TMP25:%.*]] = ashr i32 [[TMP24]], 1
114-
; CHECK-NEXT: [[ADD72:%.*]] = or disjoint i32 [[TMP25]], 532365312
112+
; CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[ARRAYIDX35]], align 4
113+
; CHECK-NEXT: [[TMP36:%.*]] = ashr i32 [[TMP35]], 1
114+
; CHECK-NEXT: [[TMP37:%.*]] = add nsw i32 [[TMP36]], 532365312
115115
; CHECK-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD34]]
116-
; CHECK-NEXT: store i32 [[ADD72]], ptr [[ARRAYIDX36]], align 4
116+
; CHECK-NEXT: store i32 [[TMP37]], ptr [[ARRAYIDX36]], align 4
117117
; CHECK-NEXT: [[ADD37:%.*]] = or disjoint i32 [[I_012_MODIFY]], 13
118118
; CHECK-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD37]]
119-
; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARRAYIDX38]], align 4
120-
; CHECK-NEXT: [[TMP27:%.*]] = ashr i32 [[TMP26]], 1
121-
; CHECK-NEXT: [[ADD74:%.*]] = or disjoint i32 [[TMP27]], 532365312
119+
; CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX38]], align 4
120+
; CHECK-NEXT: [[TMP39:%.*]] = ashr i32 [[TMP38]], 1
121+
; CHECK-NEXT: [[TMP40:%.*]] = add nsw i32 [[TMP39]], 532365312
122122
; CHECK-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD37]]
123-
; CHECK-NEXT: store i32 [[ADD74]], ptr [[ARRAYIDX39]], align 4
123+
; CHECK-NEXT: store i32 [[TMP40]], ptr [[ARRAYIDX39]], align 4
124124
; CHECK-NEXT: [[ADD40:%.*]] = or disjoint i32 [[I_012_MODIFY]], 14
125125
; CHECK-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD40]]
126-
; CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX41]], align 4
127-
; CHECK-NEXT: [[TMP29:%.*]] = ashr i32 [[TMP28]], 1
128-
; CHECK-NEXT: [[ADD76:%.*]] = or disjoint i32 [[TMP29]], 532365312
126+
; CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[ARRAYIDX41]], align 4
127+
; CHECK-NEXT: [[TMP42:%.*]] = ashr i32 [[TMP41]], 1
128+
; CHECK-NEXT: [[TMP43:%.*]] = add nsw i32 [[TMP42]], 532365312
129129
; CHECK-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD40]]
130-
; CHECK-NEXT: store i32 [[ADD76]], ptr [[ARRAYIDX42]], align 4
130+
; CHECK-NEXT: store i32 [[TMP43]], ptr [[ARRAYIDX42]], align 4
131131
; CHECK-NEXT: [[ADD43:%.*]] = or disjoint i32 [[I_012_MODIFY]], 15
132132
; CHECK-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[ADD43]]
133-
; CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[ARRAYIDX44]], align 4
134-
; CHECK-NEXT: [[TMP31:%.*]] = ashr i32 [[TMP30]], 1
135-
; CHECK-NEXT: [[ADD78:%.*]] = or disjoint i32 [[TMP31]], 532365312
133+
; CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[ARRAYIDX44]], align 4
134+
; CHECK-NEXT: [[TMP45:%.*]] = ashr i32 [[TMP44]], 1
135+
; CHECK-NEXT: [[TMP46:%.*]] = add nsw i32 [[TMP45]], 532365312
136136
; CHECK-NEXT: [[ARRAYIDX45:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[ADD43]]
137-
; CHECK-NEXT: store i32 [[ADD78]], ptr [[ARRAYIDX45]], align 4
138-
; CHECK-NEXT: [[TMP32]] = add nuw i32 [[I_012_MODIFY]], 16
139-
; CHECK-NEXT: [[EXITCOND_NOT_MODIFY:%.*]] = icmp sgt i32 [[TMP32]], [[SUB]]
137+
; CHECK-NEXT: store i32 [[TMP46]], ptr [[ARRAYIDX45]], align 4
138+
; CHECK-NEXT: [[TMP47]] = add nuw i32 [[I_012_MODIFY]], 16
139+
; CHECK-NEXT: [[EXITCOND_NOT_MODIFY:%.*]] = icmp sgt i32 [[TMP47]], [[SUB]]
140140
; CHECK-NEXT: br i1 [[EXITCOND_NOT_MODIFY]], label [[FOR_COND_PREHEADER_NEW2]], label [[FOR_BODY_MODIFY]]
141141
; CHECK: for.body:
142142
; CHECK-NEXT: [[I_012:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[TMP0]], [[FOR_COND_PREHEADER_NEW2]] ]
143143
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[I_012]]
144-
; CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
145-
; CHECK-NEXT: [[SHR_I:%.*]] = ashr i32 [[TMP33]], 1
144+
; CHECK-NEXT: [[TMP48:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
145+
; CHECK-NEXT: [[SHR_I:%.*]] = ashr i32 [[TMP48]], 1
146146
; CHECK-NEXT: [[ADD_I:%.*]] = add nsw i32 [[SHR_I]], 532365312
147147
; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[I_012]]
148148
; CHECK-NEXT: store i32 [[ADD_I]], ptr [[ARRAYIDX5]], align 4
@@ -152,8 +152,8 @@ define dso_local noundef i32 @dsps_sqrt_f32_ansi(ptr noundef readonly %input, pt
152152
; CHECK: for.body.clone:
153153
; CHECK-NEXT: [[I_012_CLONE:%.*]] = phi i32 [ [[INC_CLONE:%.*]], [[FOR_BODY_CLONE]] ], [ 0, [[FOR_COND_PREHEADER]] ]
154154
; CHECK-NEXT: [[ARRAYIDX_CLONE:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[I_012_CLONE]]
155-
; CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[ARRAYIDX_CLONE]], align 4
156-
; CHECK-NEXT: [[SHR_I_CLONE:%.*]] = ashr i32 [[TMP34]], 1
155+
; CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[ARRAYIDX_CLONE]], align 4
156+
; CHECK-NEXT: [[SHR_I_CLONE:%.*]] = ashr i32 [[TMP49]], 1
157157
; CHECK-NEXT: [[ADD_I_CLONE:%.*]] = add nsw i32 [[SHR_I_CLONE]], 532365312
158158
; CHECK-NEXT: [[ARRAYIDX5_CLONE:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[I_012_CLONE]]
159159
; CHECK-NEXT: store i32 [[ADD_I_CLONE]], ptr [[ARRAYIDX5_CLONE]], align 4

‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/sub.ll renamed to ‎llvm/test/CodeGen/RISCV/RISCVLoopUnrollAndRemainder/dsps_sub_f32_ansi.ll

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