Skip to content

Commit 7507e37

Browse files
committed
Xtensa] Use B0 register for FP cmp operations.
The virtual bool registers allocation from BR class may cause situation when we need to spill such 1-bit registers, this would cause performance degradation due to load/store operations of the 32-bit BR register. The performance improvement from using virtual bool registers is not significant. So, just use only B0 register for FP compare operations.
1 parent ce86f67 commit 7507e37

File tree

1 file changed

+9
-10
lines changed

1 file changed

+9
-10
lines changed

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2052,15 +2052,15 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI,
20522052
(MI.getOpcode() == Xtensa::SELECT_CC_FP_INT)) {
20532053
int BrKind = 0;
20542054
int CmpKind = 0;
2055-
MachineFunction *MF = BB->getParent();
2056-
MachineRegisterInfo &RegInfo = MF->getRegInfo();
2057-
const TargetRegisterClass *RC = &Xtensa::BRRegClass;
2058-
unsigned b = RegInfo.createVirtualRegister(RC);
2055+
unsigned b = Xtensa::B0;
2056+
20592057
GetFPBranchKind(Cond.getImm(), BrKind, CmpKind);
20602058
BuildMI(BB, DL, TII.get(CmpKind), b)
20612059
.addReg(LHS.getReg())
20622060
.addReg(RHS.getReg());
2063-
BuildMI(BB, DL, TII.get(BrKind)).addReg(b).addMBB(sinkMBB);
2061+
BuildMI(BB, DL, TII.get(BrKind))
2062+
.addReg(b, RegState::Kill)
2063+
.addMBB(sinkMBB);
20642064
} else {
20652065
bool BrInv = false;
20662066
int BrKind = GetBranchKind(Cond.getImm(), BrInv);
@@ -3115,16 +3115,15 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter(
31153115
MachineBasicBlock *TargetBB = MI.getOperand(3).getMBB();
31163116
int BrKind = 0;
31173117
int CmpKind = 0;
3118-
MachineFunction *MF = MBB->getParent();
3119-
MachineRegisterInfo &RegInfo = MF->getRegInfo();
3120-
const TargetRegisterClass *RC = &Xtensa::BRRegClass;
3118+
unsigned RegB = Xtensa::B0;
31213119

3122-
unsigned RegB = RegInfo.createVirtualRegister(RC);
31233120
GetFPBranchKind(Cond.getImm(), BrKind, CmpKind);
31243121
BuildMI(*MBB, MI, DL, TII.get(CmpKind), RegB)
31253122
.addReg(LHS.getReg())
31263123
.addReg(RHS.getReg());
3127-
BuildMI(*MBB, MI, DL, TII.get(BrKind)).addReg(RegB).addMBB(TargetBB);
3124+
BuildMI(*MBB, MI, DL, TII.get(BrKind))
3125+
.addReg(RegB, RegState::Kill)
3126+
.addMBB(TargetBB);
31283127

31293128
MI.eraseFromParent();
31303129
return MBB;

0 commit comments

Comments
 (0)