From cf0a05d72911eaf88b17ed948939fdd184a717e4 Mon Sep 17 00:00:00 2001 From: Eduardo Lacerda Campos Date: Fri, 1 Sep 2023 18:33:08 -0400 Subject: [PATCH 1/2] Update uart_ll.h - Fixing division by zero I have faced the division by zero when the baud rate is higher than 1Mbits/s. It happens because the integer division returns zero for sclk_div while slightly below 1.0. I also added 0.5 to improve the roundup process of converting float to integer. With that fix, I can reach 3.125Mbits/s. --- components/hal/esp32s3/include/hal/uart_ll.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h index 9496f0d5978e..80db7ec3b870 100644 --- a/components/hal/esp32s3/include/hal/uart_ll.h +++ b/components/hal/esp32s3/include/hal/uart_ll.h @@ -131,9 +131,12 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source */ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { -#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) +#define DIV_UP(a, b) ((float)((a) + (b) - 1) / (b)) const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits - int sclk_div = DIV_UP(sclk_freq, max_div * baud); + int sclk_div = DIV_UP(sclk_freq, max_div * baud) + 0.5; + + if (sclk_div == 0) + sclk_div = 1; uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); // The baud rate configuration register is divided into From 3f40c80c06b2d9057fd651db98f6c5b18f64a8b6 Mon Sep 17 00:00:00 2001 From: Eduardo Lacerda Campos Date: Wed, 6 Sep 2023 23:48:21 -0400 Subject: [PATCH 2/2] Update uart_ll.h Use uint64_t instead of float to calculate the clock division for the baudrate --- components/hal/esp32s3/include/hal/uart_ll.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h index 80db7ec3b870..077abd8266ad 100644 --- a/components/hal/esp32s3/include/hal/uart_ll.h +++ b/components/hal/esp32s3/include/hal/uart_ll.h @@ -131,9 +131,9 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source */ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { -#define DIV_UP(a, b) ((float)((a) + (b) - 1) / (b)) +#define DIV_UP(a, b) ((uint64_t)((a) + (b) - 1) / (b)) const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits - int sclk_div = DIV_UP(sclk_freq, max_div * baud) + 0.5; + uint32_t sclk_div = DIV_UP(sclk_freq, max_div * baud); if (sclk_div == 0) sclk_div = 1;