diff --git a/MCAL_Drivers/AFIO/include/AFIO_config.h b/MCAL_Drivers/AFIO/include/AFIO_config.h
new file mode 100755
index 0000000..c5714ac
--- /dev/null
+++ b/MCAL_Drivers/AFIO/include/AFIO_config.h
@@ -0,0 +1,11 @@
+/**********************************************************/
+/* Author    : Gehad Elkoumy                              */
+/* Date      : 30 NOV 2022                                */
+/* Version   : V01                                        */
+/**********************************************************/
+
+#ifndef AFIO_CONFIG_H
+#define AFIO_CONFIG_H
+
+
+#endif
\ No newline at end of file
diff --git a/MCAL_Drivers/AFIO/include/AFIO_interface.h b/MCAL_Drivers/AFIO/include/AFIO_interface.h
new file mode 100755
index 0000000..eae133f
--- /dev/null
+++ b/MCAL_Drivers/AFIO/include/AFIO_interface.h
@@ -0,0 +1,19 @@
+/**********************************************************/
+/* Author    : Gehad Elkoumy                              */
+/* Date      : 30 NOV 2022                                */
+/* Version   : V01                                        */
+/**********************************************************/
+
+#ifndef AFIO_INTERFACE_H
+#define AFIO_INTERFACE_H
+
+void	MAFIO_voidSetEXTIConfiguration(u8 Copy_u8Line ,u8 Copy_u8PortMap);
+
+/*portmap used as an interrupt*/
+#define AFIOA   0b0000
+#define AFIOB   0b0001
+#define AFIOC   0b0010
+
+/*lines are in EXTI driver*/
+
+#endif
\ No newline at end of file
diff --git a/MCAL_Drivers/AFIO/include/AFIO_private.h b/MCAL_Drivers/AFIO/include/AFIO_private.h
new file mode 100755
index 0000000..0e37d13
--- /dev/null
+++ b/MCAL_Drivers/AFIO/include/AFIO_private.h
@@ -0,0 +1,23 @@
+/**********************************************************/
+/* Author    : Gehad Elkoumy                              */
+/* Date      : 30 NOV 2022                                */
+/* Version   : V01                                        */
+/**********************************************************/
+
+#ifndef AFIO_PRIVATE_H
+#define AFIO_PRIVATE_H
+
+
+typedef struct{
+	volatile u32 EVCR;
+	volatile u32 MAPR;
+	volatile u32 EXTICR[4];
+	volatile u32 MAPR2;
+	
+}AFIO_t;
+
+
+#define 	AFIO 		((volatile AFIO_t *) 0x40010000 )
+
+
+#endif
\ No newline at end of file
diff --git a/MCAL_Drivers/AFIO/src/AFIO_program.c b/MCAL_Drivers/AFIO/src/AFIO_program.c
new file mode 100755
index 0000000..9aa48f7
--- /dev/null
+++ b/MCAL_Drivers/AFIO/src/AFIO_program.c
@@ -0,0 +1,48 @@
+/**********************************************************/
+/* Author    : Gehad Elkoumy                              */
+/* Date      : 30 NOV 2022                                */
+/* Version   : V01                                        */
+/**********************************************************/
+#include "STD_TYPES.h"
+#include "BIT_MATH.h"
+
+#include "AFIO_interface.h"
+#include "AFIO_config.h"
+#include "AFIO_private.h"
+
+
+void	MAFIO_voidSetEXTIConfiguration(u8 Copy_u8EXTILine ,u8 Copy_u8PortMap)
+{
+	u8 Local_u8RegIndex = 0 ;		
+	/* Assign to EXTICRX register									*/
+	if(Copy_u8EXTILine <= 3 )
+	{
+			Local_u8RegIndex = 0;
+	}
+	else if(Copy_u8EXTILine <= 7)
+	{	
+		Local_u8RegIndex = 1;
+		
+		/*bit0 to bit3 not 4 to 7*/
+		Copy_u8EXTILine -= 4;
+	}
+	else if(Copy_u8EXTILine <= 11)
+	{
+		Local_u8RegIndex = 2;
+		/*4bits from 0 to 3*/
+		Copy_u8EXTILine -= 8;
+	
+	}
+	else if(Copy_u8EXTILine <= 15)
+	{
+		Local_u8RegIndex = 3;
+		/*4bits from 0 to 3*/
+		Copy_u8EXTILine -= 12;
+	}
+
+	/*reset first --> (avoiding overwrite)*/
+	AFIO->EXTICR[Local_u8RegIndex] &= ~((0b1111) << (Copy_u8EXTILine * 4));
+	
+	/*set*/
+	AFIO->EXTICR[Local_u8RegIndex]  |= ((Copy_u8PortMap) << (Copy_u8EXTILine * 4));	
+}
diff --git a/MCAL_Drivers/EXTI/include/EXTI_config.h b/MCAL_Drivers/EXTI/include/EXTI_config.h
new file mode 100755
index 0000000..f20b879
--- /dev/null
+++ b/MCAL_Drivers/EXTI/include/EXTI_config.h
@@ -0,0 +1,22 @@
+/**********************************************************/
+/* Author    : Gehad Elkoumy                              */
+/* Date      : 6 DEC 2022                                 */
+/* Version   : V01                                        */
+/**********************************************************/
+#ifndef EXTI_CONFIG_H
+#define EXTI_CONFIG_H
+
+
+/*options : from LINE0 to LINE15*/
+#define		EXTI_LINE			LINE0	
+ 
+ 
+ 
+ /*options : RISING
+			 FALLING
+			 ON_CHANGE  */
+#define		EXTI_MODE			FALLING
+
+
+
+#endif
diff --git a/MCAL_Drivers/EXTI/include/EXTI_interface.h b/MCAL_Drivers/EXTI/include/EXTI_interface.h
new file mode 100755
index 0000000..4499e3e
--- /dev/null
+++ b/MCAL_Drivers/EXTI/include/EXTI_interface.h
@@ -0,0 +1,44 @@
+/**********************************************************/
+/* Author    : Gehad Elkoumy                              */
+/* Date      : 6 DEC 2022                                 */
+/* Version   : V01                                        */
+/**********************************************************/
+#ifndef EXTI_INTERFACE_H
+#define EXTI_INTERFACE_H
+
+
+void MEXTI_voidInit();
+void MEXTI_voidEnableEXTI(u8 Copy_u8EXTILine);
+void MEXTI_voidDisableEXTI(u8 Copy_u8EXTILine);
+void MEXTI_voidSoftwareTrigger(u8 Copy_u8EXTILine);
+void MEXTI_voidSetSignalLatch(u8 Copy_u8EXTILine , u8 Copy_u8EXTIMode);
+
+/*pointer to function*/
+void EXTI_voidSetCallBack(void (*ptr) (void) , u8 Copy_u8EXTILine);
+
+
+#define			LINE0				0
+#define			LINE1				1
+#define			LINE2				2
+#define			LINE3				3
+#define			LINE4				4
+#define			LINE5				5
+#define			LINE6				6
+#define			LINE7				7
+#define			LINE8				8
+#define			LINE9				9
+#define			LINE10				10
+#define			LINE11				11
+#define			LINE12				12
+#define			LINE13				13
+#define			LINE14				14
+#define			LINE15				15
+
+
+
+#define			RISING				0
+#define			FALLING				1
+#define			ON_CHANGE			2   /*any change (rising & falling)*/
+
+
+#endif
diff --git a/MCAL_Drivers/EXTI/include/EXTI_private.h b/MCAL_Drivers/EXTI/include/EXTI_private.h
new file mode 100755
index 0000000..0f4e2f1
--- /dev/null
+++ b/MCAL_Drivers/EXTI/include/EXTI_private.h
@@ -0,0 +1,25 @@
+/**********************************************************/
+/* Author    : Gehad Elkoumy                              */
+/* Date      : 6 DEC 2022                                 */
+/* Version   : V01                                        */
+/**********************************************************/
+#ifndef EXTI_PRIVATE_H
+#define EXTI_PRIVATE_H
+
+/*must be ordered*/
+typedef struct{
+	volatile u32 IMR;
+	volatile u32 EMR;
+	volatile u32 RTSR;
+	volatile u32 FTSR;
+	volatile u32 SWIER;
+	volatile u32 PR;
+	
+}EXTI_t;
+
+/*without dereference as it act as pointer*/
+#define		EXTI  	 	((volatile EXTI_t *) 0x40010400 )
+
+static void (*EXTI_GlobalPtr[16]) (void) ;
+
+#endif
diff --git a/MCAL_Drivers/EXTI/src/EXTI_program.c b/MCAL_Drivers/EXTI/src/EXTI_program.c
new file mode 100755
index 0000000..0b49d77
--- /dev/null
+++ b/MCAL_Drivers/EXTI/src/EXTI_program.c
@@ -0,0 +1,206 @@
+/**********************************************************/
+/* Author    : Gehad Elkoumy                              */
+/* Date      : 6 DEC 2022                                 */
+/* Version   : V01                                        */
+/**********************************************************/
+
+#include "STD_TYPES.h"
+#include "BIT_MATH.h"
+
+#include "EXTI_interface.h"
+#include "EXTI_config.h"  
+#include "EXTI_private.h"
+
+
+
+void MEXTI_voidInit()
+{
+	#if 	EXTI_MODE	== 	RISING
+		SET_BIT(EXTI -> RTSR , EXTI_LINE);
+	#elif 	EXTI_MODE	== 	FALLING
+		SET_BIT(EXTI -> FTSR , EXTI_LINE);
+	#elif	EXTI_MODE	==	ON_CHANGE
+		SET_BIT(EXTI -> RTSR , EXTI_LINE);
+		SET_BIT(EXTI -> FTSR , EXTI_LINE);
+	#else 	
+		#error "Wrong Mode"
+	#endif
+	
+	/*Disable interrupt*/
+	CLR_BIT(EXTI -> IMR , EXTI_LINE);
+}
+
+
+void MEXTI_voidEnableEXTI(u8 Copy_u8EXTILine)
+{
+	SET_BIT(EXTI -> IMR , Copy_u8EXTILine);
+}
+
+
+void MEXTI_voidDisableEXTI(u8 Copy_u8EXTILine)
+{
+	CLR_BIT(EXTI -> IMR , Copy_u8EXTILine);
+}
+
+
+void MEXTI_voidSoftwareTrigger(u8 Copy_u8EXTILine)
+{
+	SET_BIT(EXTI -> IMR , Copy_u8EXTILine);
+	CLR_BIT(EXTI -> PR , Copy_u8EXTILine);
+	SET_BIT(EXTI -> SWIER , Copy_u8EXTILine);
+}
+
+ 
+             /*changing mode & line in run time*/
+void MEXTI_voidSetSignalLatch(u8 Copy_u8EXTILine , u8 Copy_u8EXTIMode)
+{
+	switch(Copy_u8EXTIMode)
+	{
+		case RISING :
+			SET_BIT(EXTI -> RTSR , Copy_u8EXTILine);
+			break;
+		
+		case FALLING :
+			SET_BIT(EXTI -> FTSR , Copy_u8EXTILine); 	
+			break;
+		
+		case ON_CHANGE :
+			SET_BIT(EXTI -> RTSR , Copy_u8EXTILine);
+			SET_BIT(EXTI -> FTSR , Copy_u8EXTILine); 	
+			break;
+	}
+	SET_BIT(EXTI -> IMR , Copy_u8EXTILine);
+}
+
+
+void EXTI_voidSetCallBack(void (*ptr) (void) , u8 Copy_u8EXTILine)
+{
+	EXTI_GlobalPtr[Copy_u8EXTILine] = ptr;
+}
+
+
+void EXTI0_IRQHandler(void)
+{
+	EXTI_GlobalPtr[0]();
+	/*clear pending bit*/
+	SET_BIT(EXTI -> PR , 0);
+}
+
+void EXTI1_IRQHandler(void)
+{
+	EXTI_GlobalPtr[1]();
+	/*clear pending bit*/
+	SET_BIT(EXTI -> PR , 1);
+}
+
+void EXTI2_IRQHandler(void)
+{
+	EXTI_GlobalPtr[2]();
+	/*clear pending bit*/
+	SET_BIT(EXTI -> PR , 2);
+}
+
+void EXTI3_IRQHandler(void)
+{
+	EXTI_GlobalPtr[3]();
+	/*clear pending bit*/
+	SET_BIT(EXTI -> PR , 3);
+}
+
+void EXTI4_IRQHandler(void)
+{
+	EXTI_GlobalPtr[4]();
+	/*clear pending bit*/
+	SET_BIT(EXTI -> PR , 4);
+}
+
+void EXTI9_5_IRQHandler(void)
+{
+	u8 PinValue_5 , PinValue_6 , PinValue_7 , PinValue_8 , PinValue_9;
+
+	PinValue_5 = GET_BIT(EXTI->PR,5);
+	PinValue_6 = GET_BIT(EXTI->PR,6);
+	PinValue_7 = GET_BIT(EXTI->PR,7);
+	PinValue_8 = GET_BIT(EXTI->PR,8);
+	PinValue_9 = GET_BIT(EXTI->PR,9);
+
+	if (PinValue_5 == 1)
+	{
+		EXTI_GlobalPtr[5]();
+		SET_BIT(EXTI -> PR , 5);
+	}
+
+	if (PinValue_6 == 1)
+	{
+		EXTI_GlobalPtr[6]();
+		SET_BIT(EXTI -> PR , 6);
+	}
+
+	if (PinValue_7 == 1)
+	{
+		EXTI_GlobalPtr[7]();
+		SET_BIT(EXTI -> PR , 7);
+	}
+
+	if (PinValue_8 == 1)
+	{
+		EXTI_GlobalPtr[8]();
+		SET_BIT(EXTI -> PR , 8);
+	}
+
+	if (PinValue_9 == 1)
+	{
+		EXTI_GlobalPtr[9]();
+		SET_BIT(EXTI -> PR , 9);
+	}
+
+}
+
+void EXTI15_10_IRQHandler(void)
+{
+	u8 PinValue_10 , PinValue_11 , PinValue_12 , PinValue_13 , PinValue_14 , PinValue_15;
+
+	PinValue_10 = GET_BIT(EXTI->PR,10);
+	PinValue_11 = GET_BIT(EXTI->PR,11);
+	PinValue_12 = GET_BIT(EXTI->PR,12);
+	PinValue_13 = GET_BIT(EXTI->PR,13);
+	PinValue_14 = GET_BIT(EXTI->PR,14);
+	PinValue_15 = GET_BIT(EXTI->PR,14);
+
+	if (PinValue_10 == 1)
+	{
+		EXTI_GlobalPtr[10]();
+		SET_BIT(EXTI -> PR , 10);
+	}
+
+	if (PinValue_11 == 1)
+	{
+		EXTI_GlobalPtr[11]();
+		SET_BIT(EXTI -> PR , 11);
+	}
+
+	if (PinValue_12 == 1)
+	{
+		EXTI_GlobalPtr[12]();
+		SET_BIT(EXTI -> PR , 12);
+	}
+
+	if (PinValue_13 == 1)
+	{
+		EXTI_GlobalPtr[13]();
+		SET_BIT(EXTI -> PR , 13);
+	}
+
+	if (PinValue_14 == 1)
+	{
+		EXTI_GlobalPtr[14]();
+		SET_BIT(EXTI -> PR , 14);
+	}
+
+	if (PinValue_15 == 1)
+	{
+		EXTI_GlobalPtr[15]();
+		SET_BIT(EXTI -> PR , 15);
+	}
+
+}
diff --git a/MCAL_Drivers/EXTI/src/main.c b/MCAL_Drivers/EXTI/src/main.c
new file mode 100755
index 0000000..c3efa0c
--- /dev/null
+++ b/MCAL_Drivers/EXTI/src/main.c
@@ -0,0 +1,74 @@
+/*
+ * main.c
+ *
+ *  Created on: Feb 18, 2023
+ *      Author: Gehad
+ */
+
+#include"STD_TYPES.h"
+#include"BIT_MATH.h"
+
+#include"RCC_interface.h"
+#include"DIO_interface.h"
+#include"NVIC_interface.h"
+#include"AFIO_interface.h"
+#include"EXTI_interface.h"
+
+void TakeAction8(void)
+{
+	MGPIO_VoidSetPinValue(GPIOA,PIN0,HIGH);
+}
+
+void TakeAction9(void)
+{
+	MGPIO_VoidSetPinValue(GPIOA,PIN1,HIGH);
+}
+
+
+void main (void)
+{
+	/*initialize clocks*/
+	RCC_voidInitSysClock();
+	/*Enable GPIOA clock */
+	RCC_voidEnableClock(RCC_APB2,2);
+	//RCC_voidEnableClock(RCC_APB2,3);
+	/*Enable AFIO clock */
+	RCC_voidEnableClock(RCC_APB2,0);
+
+	/*AFIO*//**/
+	MAFIO_voidSetEXTIConfiguration(LINE8 , AFIOA);
+	MAFIO_voidSetEXTIConfiguration(LINE9 , AFIOA);
+
+
+	EXTI_voidSetCallBack(TakeAction9 , LINE9);
+	EXTI_voidSetCallBack(TakeAction8 , LINE8);
+
+	/*pin modes*/
+	MGPIO_VoidSetPinDirection(GPIOA,PIN8,INPUT_PULLUP_PULLDOWN);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN9,INPUT_PULLUP_PULLDOWN);
+
+	MGPIO_VoidSetPinDirection(GPIOA,PIN0,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN1,OUTPUT_2MHZ_PP);
+
+	MGPIO_VoidSetPinValue(GPIOA,PIN8,HIGH);
+	MGPIO_VoidSetPinValue(GPIOA,PIN9,HIGH);
+
+	/*initialize EXTI*/
+	MEXTI_voidInit();
+	MEXTI_voidSetSignalLatch(LINE8 , FALLING);
+	MEXTI_voidSetSignalLatch(LINE9 , FALLING);
+
+
+	/*Enable EXTI0 interrupt from NVIC*/
+	MNVIC_voidEnableInterrupt(23);
+	/*set priority for EXT0*/
+	//MNVIC_voidSetPriority(23,1,0);
+
+
+
+	while(1)
+	{
+
+	}
+}
+
diff --git a/MCAL_Drivers/GPIO/include/DIO_config.h b/MCAL_Drivers/GPIO/include/DIO_config.h
new file mode 100755
index 0000000..d3ee654
--- /dev/null
+++ b/MCAL_Drivers/GPIO/include/DIO_config.h
@@ -0,0 +1,11 @@
+/*********************************************************************************/
+/* Author    : Gehad Elkoumy                                                     */
+/* Version   : V01                                                               */
+/* Date      : 29 NOV 2022                                                       */
+/*********************************************************************************/
+#ifndef _DIO_CONFIG_H
+#define _DIO_CONFIG_H
+
+
+
+#endif
\ No newline at end of file
diff --git a/MCAL_Drivers/GPIO/include/DIO_interface.h b/MCAL_Drivers/GPIO/include/DIO_interface.h
new file mode 100755
index 0000000..ab301d3
--- /dev/null
+++ b/MCAL_Drivers/GPIO/include/DIO_interface.h
@@ -0,0 +1,65 @@
+/*********************************************************************************/
+/* Author    : Gehad Elkoumy                                                     */
+/* Version   : V01                                                               */
+/* Date      : 29 NOV 2022                                                       */
+/*********************************************************************************/
+#ifndef DIO_INTERFACE_H
+#define DIO_INTERFACE_H
+
+#define HIGH    1
+#define LOW     0
+
+/* Port Id */
+#define GPIOA   0
+#define GPIOB   1
+#define GPIOC   2
+
+/* Pin Id*/
+#define PIN0    0
+#define PIN1    1
+#define PIN2    2
+#define PIN3    3
+#define PIN4    4
+#define PIN5    5
+#define PIN6    6
+#define PIN7    7
+#define PIN8    8
+#define PIN9    9
+#define PIN10    10
+#define PIN11    11
+#define PIN12    12
+#define PIN13    13
+#define PIN14    14
+#define PIN15    15
+
+/*Input mode with configuration*/
+#define INPUT_ANALOG              0b0000
+#define INPUT_FLOATING            0b0100
+#define INPUT_PULLUP_PULLDOWN     0b1000
+
+/*Output mode 10MHZ with configuration*/
+#define OUTPUT_10MHZ_PP           0b0001     //push pull
+#define OUTPUT_10MHZ_OD           0b0101     //open drain
+#define OUTPUT_10MHZ_AFPP         0b1001     //Alternative function push pull
+#define OUTPUT_10MHZ_AFOD         0b1101     //Alernative function open drain 
+
+/*Output mode 2MHZ with configuration*/
+#define OUTPUT_2MHZ_PP            0b0010     //push pull
+#define OUTPUT_2MHZ_OD            0b0110     //open drain
+#define OUTPUT_2MHZ_AFPP          0b1010     //Alternative function push pull
+#define OUTPUT_2MHZ_AFOD          0b1110     //Alernative function open drain
+
+/*Output mode 50MHZ with configuration*/
+#define OUTPUT_50MHZ_PP           0b0011     //push pull
+#define OUTPUT_50MHZ_OD           0b0111     //open drain
+#define OUTPUT_50MHZ_AFPP         0b1011     //Alternative function push pull
+#define OUTPUT_50MHZ_AFOD         0b1111     //Alernative function open drain
+
+
+void MGPIO_VoidSetPinDirection(u8 Copy_u8Port , u8 Copy_u8Pin , u8 Copy_u8Mode);
+void MGPIO_VoidSetPinValue(u8 Copy_u8Port , u8 Copy_u8Pin , u8 Copy_u8Value);
+u8 MGPIO_u8GetPinValue(u8 Copy_u8Port , u8 Copy_u8Pin);
+void MGPIO_VoidLockPin(u8 Copy_u8Port , u8 Copy_u8Pin);
+
+
+#endif
diff --git a/MCAL_Drivers/GPIO/include/DIO_private.h b/MCAL_Drivers/GPIO/include/DIO_private.h
new file mode 100755
index 0000000..d75dc1f
--- /dev/null
+++ b/MCAL_Drivers/GPIO/include/DIO_private.h
@@ -0,0 +1,49 @@
+/*********************************************************************************/
+/* Author    : Gehad Elkoumy                                                     */
+/* Version   : V01                                                               */
+/* Date      : 29 NOV 2022                                                       */
+/*********************************************************************************/
+#ifndef DIO_PRIVATE_H
+#define DIO_PRIVATE_H
+
+
+#define GPIOA_Base_Address        0x40010800            // Base address of GPIO port A
+#define GPIOB_Base_Address        0x40010C00            // Base address of GPIO port B
+#define GPIOC_Base_Address        0x40011000            // Base address of GPIO port C
+
+/*  Register Definitions for Port A (Base address + offset)  */
+		
+#define GPIOA_CRL         *((volatile u32*)(GPIOA_Base_Address + 0x00))
+#define GPIOA_CRH         *((volatile u32*)(GPIOA_Base_Address + 0x04))
+#define GPIOA_IDR         *((volatile u32*)(GPIOA_Base_Address + 0x08))
+#define GPIOA_ODR         *((volatile u32*)(GPIOA_Base_Address + 0x0c))
+#define GPIOA_BSRR        *((volatile u32*)(GPIOA_Base_Address + 0x10))
+#define GPIOA_BRR         *((volatile u32*)(GPIOA_Base_Address + 0x14))
+#define GPIOA_LCKR        *((volatile u32*)(GPIOA_Base_Address + 0x18))
+
+
+/*  Register Definitions for Port B (Base address + offset)  */
+		
+#define GPIOB_CRL         *((volatile u32*)(GPIOB_Base_Address + 0x00))
+#define GPIOB_CRH         *((volatile u32*)(GPIOB_Base_Address + 0x04))
+#define GPIOB_IDR         *((volatile u32*)(GPIOB_Base_Address + 0x08))
+#define GPIOB_ODR         *((volatile u32*)(GPIOB_Base_Address + 0x0c))
+#define GPIOB_BSRR        *((volatile u32*)(GPIOB_Base_Address + 0x10))
+#define GPIOB_BRR         *((volatile u32*)(GPIOB_Base_Address + 0x14))
+#define GPIOB_LCKR        *((volatile u32*)(GPIOB_Base_Address + 0x18))
+
+
+/*  Register Definitions for Port C (Base address + offset)  */
+		
+#define GPIOC_CRL         *((volatile u32*)(GPIOC_Base_Address + 0x00))
+#define GPIOC_CRH         *((volatile u32*)(GPIOC_Base_Address + 0x04))
+#define GPIOC_IDR         *((volatile u32*)(GPIOC_Base_Address + 0x08))
+#define GPIOC_ODR         *((volatile u32*)(GPIOC_Base_Address + 0x0c))
+#define GPIOC_BSRR        *((volatile u32*)(GPIOC_Base_Address + 0x10))
+#define GPIOC_BRR         *((volatile u32*)(GPIOC_Base_Address + 0x14))
+#define GPIOC_LCKR        *((volatile u32*)(GPIOC_Base_Address + 0x18))
+
+/*lock key bit*/
+#define LCKK  16
+
+#endif
\ No newline at end of file
diff --git a/MCAL_Drivers/GPIO/src/DIO_program.c b/MCAL_Drivers/GPIO/src/DIO_program.c
new file mode 100755
index 0000000..7126040
--- /dev/null
+++ b/MCAL_Drivers/GPIO/src/DIO_program.c
@@ -0,0 +1,208 @@
+/*********************************************************************************/
+/* Author    : Gehad Elkoumy                                                     */
+/* Version   : V01                                                               */
+/* Date      : 29 NOV 2022                                                       */
+/*********************************************************************************/
+
+#include "STD_TYPES.h"
+#include "BIT_MATH.h"
+
+#include "DIO_interface.h"
+#include "DIO_private.h"
+#include "DIO_config.h"
+
+void MGPIO_VoidSetPinDirection(u8 Copy_u8Port , u8 Copy_u8Pin , u8 Copy_u8Mode)
+{
+	switch(Copy_u8Port)
+	{
+	case GPIOA:
+		/*CRL controls form pin0 to pin7 (each pin has 4 bits)*/
+		if(Copy_u8Pin <= 7 )
+		{
+			GPIOA_CRL &= ~ ( ( 0b1111 )  << ( Copy_u8Pin * 4 ));  /*Reset or clear pin (4bits)*/
+			GPIOA_CRL |= ( Copy_u8Mode ) << ( Copy_u8Pin * 4 );   /*apply mode on pin (interface file)*/
+		}
+		
+		/*CRH controls form pin8 to pin15 (each pin has 4 bits)*/
+		else if(Copy_u8Pin <= 15 )
+		{
+			Copy_u8Pin = Copy_u8Pin - 8;
+			GPIOA_CRH &= ~ ( ( 0b1111 )  << ( Copy_u8Pin * 4 ) );
+			GPIOA_CRH |= ( Copy_u8Mode ) << ( Copy_u8Pin * 4 );
+		}
+
+		break;
+
+	case GPIOB:
+		/*CRL controls form pin0 to pin7 (each pin has 4 bits)*/
+		if(Copy_u8Pin <= 7 )
+		{
+			/*Reset pin then overwrite*/
+			GPIOB_CRL &= ~ ( ( 0b1111 )  << ( Copy_u8Pin * 4 ) );    /*Reset or clear pin*/
+			GPIOB_CRL |= ( Copy_u8Mode ) << ( Copy_u8Pin * 4 )  ;    /*apply mode on pin*/
+		}
+		
+		/*CRH controls form pin8 to pin15 (each pin has 4 bits)*/
+		else if(Copy_u8Pin <= 15 )
+		{
+			Copy_u8Pin = Copy_u8Pin - 8;
+			GPIOB_CRH &= ~ ( ( 0b1111 )  << ( Copy_u8Pin * 4 ) );
+			GPIOB_CRH |= ( Copy_u8Mode ) << ( Copy_u8Pin * 4 )  ;
+		}
+		
+		break;
+		
+	case GPIOC:
+		/*CRL controls form pin0 to pin7 (each pin has 4 bits)*/
+		if(Copy_u8Pin <= 7 )
+		{
+			GPIOC_CRL &= ~ ( ( 0b1111 )  << ( Copy_u8Pin * 4 ) );// R M W
+			GPIOC_CRL |= ( Copy_u8Mode ) << ( Copy_u8Pin * 4 )  ;
+		}
+		
+		/*CRH controls form pin8 to pin15 (each pin has 4 bits)*/
+		else if(Copy_u8Pin <= 15 )
+		{
+			Copy_u8Pin = Copy_u8Pin - 8;
+			GPIOC_CRH &= ~ ( ( 0b1111 )  << ( Copy_u8Pin * 4 ) );
+			GPIOC_CRH |= ( Copy_u8Mode ) << ( Copy_u8Pin * 4 )  ;
+		}
+		
+		break;
+
+	}
+}
+
+
+void MGPIO_VoidSetPinValue(u8 Copy_u8Port , u8 Copy_u8Pin , u8 Copy_u8Value)
+{
+	switch(Copy_u8Port)
+	{
+	/*output data high or low for each pin*/
+	case GPIOA:
+		if( Copy_u8Value == HIGH )
+		{
+			//SET_BIT( GPIOA_ODR , Copy_u8Pin );
+			GPIOA_BSRR = (1 << Copy_u8Pin);     /*speed up -- 0 has no effect*/
+		}
+		else if( Copy_u8Value == LOW )
+		{
+			//CLR_BIT( GPIOA_ODR , Copy_u8Pin );
+			GPIOA_BRR = (1 << Copy_u8Pin);    /*speed up*/
+			//GPIOA_BSRR = (1 << (Copy_u8Pin + 16));
+		}
+		break;
+		
+	case GPIOB:
+		if( Copy_u8Value == HIGH )
+		{
+			//SET_BIT( GPIOB_ODR  , Copy_u8Pin );
+			GPIOB_BSRR = (1 << Copy_u8Pin);
+		}
+		else if( Copy_u8Value == LOW )
+		{
+			//CLR_BIT( GPIOB_ODR  , Copy_u8Pin );
+			GPIOB_BRR = (1 << Copy_u8Pin);
+		}
+		break;
+		
+	case GPIOC:
+		if( Copy_u8Value == HIGH )
+		{
+			//SET_BIT( GPIOC_ODR , Copy_u8Pin );
+			GPIOC_BSRR = (1 << Copy_u8Pin);
+		}
+		else if( Copy_u8Value == LOW )
+		{
+			//CLR_BIT( GPIOC_ODR , Copy_u8Pin );
+			GPIOC_BRR = (1 << Copy_u8Pin);
+		}
+		break;
+
+	}
+}
+
+
+u8 MGPIO_u8GetPinValue(u8 Copy_u8Port , u8 Copy_u8Pin)
+{
+	u8 LOC_u8Result = 0 ;   //return value
+
+	switch(Copy_u8Port)
+	{
+	/*get input data*/
+	case GPIOA:
+		LOC_u8Result = GET_BIT( GPIOA_IDR , Copy_u8Pin );
+		break;
+		
+	case GPIOB:
+		LOC_u8Result = GET_BIT( GPIOB_IDR , Copy_u8Pin );
+		break;
+		
+	case GPIOC:
+		LOC_u8Result = GET_BIT( GPIOC_IDR , Copy_u8Pin );
+		break;
+	}
+	
+	return LOC_u8Result;
+}
+
+
+                             /*lock pin mode*/
+/*Each lock bit freezes the corresponding 4 bits of the control register(CRL,CRH)*/
+void MGPIO_VoidLockPin(u8 Copy_u8Port , u8 Copy_u8Pin)
+{
+	switch(Copy_u8Port)
+	{
+	case GPIOA:
+	
+		/*locked pin*/
+		CLR_BIT(GPIOA_LCKR , LCKK);
+		GPIOA_LCKR = (1 << Copy_u8Pin);
+		
+		/*activate the lock key*/
+		SET_BIT(GPIOA_LCKR , LCKK);
+		
+		/*writing sequence*/
+		SET_BIT(GPIOA_LCKR , LCKK);
+		CLR_BIT(GPIOA_LCKR , LCKK);
+		SET_BIT(GPIOA_LCKR , LCKK);
+		CLR_BIT(GPIOA_LCKR , LCKK);
+		
+		break;
+		
+		
+	case GPIOB:
+		/*locked pin*/
+		CLR_BIT(GPIOB_LCKR , LCKK);
+		GPIOB_LCKR = (1 << Copy_u8Pin);
+		
+		/*activate the lock key*/
+		SET_BIT(GPIOB_LCKR , LCKK);
+		
+		/*writing sequence*/
+		SET_BIT(GPIOB_LCKR , LCKK);
+		CLR_BIT(GPIOB_LCKR , LCKK);
+		SET_BIT(GPIOB_LCKR , LCKK);
+		CLR_BIT(GPIOB_LCKR , LCKK);
+		
+		break;
+		
+		
+	case GPIOC:
+		/*locked pin*/
+		CLR_BIT(GPIOC_LCKR , LCKK);
+		GPIOC_LCKR = (1 << Copy_u8Pin);
+		
+		/*activate the lock key*/
+		SET_BIT(GPIOC_LCKR , LCKK);
+		
+		/*writing sequence*/
+		SET_BIT(GPIOC_LCKR , LCKK);
+		CLR_BIT(GPIOC_LCKR , LCKK);
+		SET_BIT(GPIOC_LCKR , LCKK);
+		CLR_BIT(GPIOC_LCKR , LCKK);
+		
+		break;
+	}
+	
+}
diff --git a/MCAL_Drivers/GPIO/src/main.c b/MCAL_Drivers/GPIO/src/main.c
new file mode 100755
index 0000000..f4fdedf
--- /dev/null
+++ b/MCAL_Drivers/GPIO/src/main.c
@@ -0,0 +1,92 @@
+/*
+ * main.c
+ *
+ *  Created on: Dec 8, 2022
+ *      Author: Gehad Elkoumy
+ */
+
+#include"STD_TYPES.h"
+#include"BIT_MATH.h"
+
+#include"RCC_interface.h"
+#include"DIO_interface.h"
+
+
+void main(void)
+{
+	/*initialize clock system*/
+	RCC_voidInitSysClock();
+
+	/*enable peripheral clk (GPIOA&B)*/
+	RCC_voidEnableClock(RCC_APB2 , 2);
+	RCC_voidEnableClock(RCC_APB2 , 3);
+
+
+    /*mode for pin*/
+	MGPIO_VoidSetPinDirection(GPIOA,PIN0,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN1,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN2,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN3,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN4,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN5,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN6,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN7,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN8,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN9,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN10,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN11,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN12,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN13,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN14,OUTPUT_2MHZ_PP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN15,OUTPUT_2MHZ_PP);
+	//u16 w = 500;
+
+
+	while(1)
+	{
+
+		MGPIO_VoidSetPinValue(GPIOA,PIN0,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN1,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN2,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN3,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN4,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN5,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN6,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN7,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN8,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN9,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN10,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN11,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN12,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN13,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN14,HIGH);
+		MGPIO_VoidSetPinValue(GPIOA,PIN15,HIGH);
+
+		/*delay with assembly (loop 500)*/
+		/*for(u16 i=0;i<w;i++)
+		{
+			for(u16 j=0;j<w;j++)
+			{
+				asm("NOP");
+			}
+
+		}
+
+		MGPIO_VoidSetPinValue(GPIOA,PIN0,HIGH);*/
+		/*delay with assembly (loop 500)*/
+		/*for(u16 i=0;i<w;i++)
+		{
+			for(u16 j=0;j<w;j++)
+			{
+				asm("NOP");
+			}
+
+		}*/
+
+	}
+
+
+}
+
+
+
diff --git a/MCAL_Drivers/TIM2/include/TIM2_config.h b/MCAL_Drivers/TIM2/include/TIM2_config.h
new file mode 100755
index 0000000..055e540
--- /dev/null
+++ b/MCAL_Drivers/TIM2/include/TIM2_config.h
@@ -0,0 +1,19 @@
+/*****************************************/
+/* Author  :  Gehad Elkoumy              */
+/* Version :  V02                        */
+/* Date    :  10 MAR 2023                */
+/*****************************************/
+
+#ifndef TIM2_CONFIG_H
+#define TIM2_CONFIG_H
+
+/* Options : 0 -- upcounter 
+			 1 -- downcounter  */
+#define		  CR1_DIR			1
+
+
+/* Options : 0 to 65535 	*/
+#define 	TIM_PRESCALER 		8
+
+
+#endif
diff --git a/MCAL_Drivers/TIM2/include/TIM2_interface.h b/MCAL_Drivers/TIM2/include/TIM2_interface.h
new file mode 100755
index 0000000..9fd90ab
--- /dev/null
+++ b/MCAL_Drivers/TIM2/include/TIM2_interface.h
@@ -0,0 +1,27 @@
+/*****************************************/
+/* Author  :  Gehad Elkoumy              */
+/* Version :  V02                        */
+/* Date    :  10 MAR 2023                */
+/*****************************************/
+
+#ifndef TIM2_INTERFACE_H
+#define TIM2_INTERFACE_H
+
+void MTIM2_voidInit (void);
+void MTIM2_voidSetBusyWait(u32 Copy_u16Ticks);
+void MTIM2_voidOutputPWM (u16 Copy_16CompareValue);
+
+#endif
+
+
+
+
+/*
+
+PWM freq = Fclk/(PSC*ARR)
+PWM duty cycle = CCR / ARR
+
+ex: if we want freq of 1KHz then Fclk = 8MHZ , ARR = 1000 , PSC = 8
+ pwm freq = 8M/(8*1000) = 1KHZ
+
+*/
diff --git a/MCAL_Drivers/TIM2/include/TIM2_private.h b/MCAL_Drivers/TIM2/include/TIM2_private.h
new file mode 100755
index 0000000..10d0143
--- /dev/null
+++ b/MCAL_Drivers/TIM2/include/TIM2_private.h
@@ -0,0 +1,41 @@
+/*****************************************/
+/* Author  :  Gehad Elkoumy              */
+/* Version :  V02                        */
+/* Date    :  10 MAR 2023                */
+/*****************************************/
+
+#ifndef TIM2_PRIVATE_H
+#define TIM2_PRIVATE_H
+
+#define 	TIM2_Base_Address		0x40000000
+
+typedef struct
+{
+	volatile u32 CR1   ;
+	volatile u32 CR2   ;
+	volatile u32 SMCR  ;
+	volatile u32 DIER  ;
+	volatile u32 SR    ;
+	volatile u32 EGR   ;
+	volatile u32 CCMR1 ;
+	volatile u32 CCMR2 ;
+	volatile u32 CCER  ;
+	volatile u32 CNT   ;
+	volatile u32 PSC   ; 
+	volatile u32 ARR   ;
+	
+}TIMER_t;
+
+#define     TIM2    ((TIMER_t*) TIM2_Base_Address)
+
+
+#define 	CCR1	*((volatile u32*)(TIM2_Base_Address + 0x34))
+#define 	CCR2	*((volatile u32*)(TIM2_Base_Address + 0x38)) 
+#define 	CCR3	*((volatile u32*)(TIM2_Base_Address + 0x3C)) 
+#define 	CCR4	*((volatile u32*)(TIM2_Base_Address + 0x40))
+#define 	DCR		*((volatile u32*)(TIM2_Base_Address + 0x48)) 
+#define 	DMAR	*((volatile u32*)(TIM2_Base_Address + 0x4C)) 
+
+
+
+#endif
diff --git a/MCAL_Drivers/TIM2/src/TIM2_program.c b/MCAL_Drivers/TIM2/src/TIM2_program.c
new file mode 100755
index 0000000..d1e9bc2
--- /dev/null
+++ b/MCAL_Drivers/TIM2/src/TIM2_program.c
@@ -0,0 +1,70 @@
+/*****************************************/
+/* Author  :  Gehad Elkoumy              */
+/* Version :  V02                        */
+/* Date    :  10 MAR 2023                */
+/*****************************************/
+
+#include "STD_TYPES.h"
+#include "BIT_MATH.h"
+
+#include "TIM2_interface.h"
+#include "TIM2_private.h"
+#include "TIM2_config.h"
+
+void MTIM2_voidInit (void)
+{
+	
+	/*direction of counter when it is edge aligned mode , no need for this bit if centered aligned*/
+	CLR_BIT(TIM2 -> CR1 , 4);
+	TIM2->CR1 |= (CR1_DIR << 4);
+	
+	/*prescaler value*/
+	TIM2->PSC = TIM_PRESCALER;
+	
+	/*if there is interrupt then DIER_UIE must be enabled*/
+	SET_BIT(TIM2 -> DIER , 0);
+	
+	/*enable channel*/
+	SET_BIT(TIM2->CCER , 12);
+
+	/*enable pwm mode 1*/
+	CLR_BIT(TIM2->CCMR2 , 12);
+	SET_BIT(TIM2->CCMR2 , 13);
+	SET_BIT(TIM2->CCMR2 , 14);
+
+	/*enable output compare -- update value after overflow or immediately*/
+	CLR_BIT(TIM2->CCMR2 , 11);   //immediately
+
+	/*enable auto reload preload for PWM*/
+	SET_BIT(TIM2 -> CR1 , 7);
+
+	/*load desired value of ARR*/
+	TIM2->ARR  = 100;
+
+	/*enable counter*/
+	SET_BIT(TIM2 -> CR1 , 0);
+	/*enable update generation*/
+	SET_BIT(TIM2 -> EGR , 0);
+
+}
+
+void MTIM2_voidSetBusyWait(u32 Copy_u16Ticks)
+{
+	/* Load ticks to ARR register */
+	TIM2 -> ARR = Copy_u16Ticks;
+	/*start counter*/
+	SET_BIT(TIM2 -> CR1 , 0);
+	/* Wait till flag is raised */
+	while( (GET_BIT(TIM2 -> SR , 0)) == 0);
+	/*Stop counter*/
+	CLR_BIT(TIM2 -> CR1 , 0);
+	/*Clear flag*/
+	CLR_BIT(TIM2 -> SR , 0);
+	
+}
+
+void MTIM2_voidOutputPWM (u16 Copy_16CompareValue)
+{
+	/*load the desired value -- channel4*/
+	CCR4 = Copy_16CompareValue;
+}
diff --git a/MCAL_Drivers/TIM2/src/main.c b/MCAL_Drivers/TIM2/src/main.c
new file mode 100755
index 0000000..d8616ae
--- /dev/null
+++ b/MCAL_Drivers/TIM2/src/main.c
@@ -0,0 +1,42 @@
+//*
+ * main.c
+ *
+ *  Created on: Mar 10, 2023
+ *      Author: Gehad
+ */
+
+#include"STD_TYPES.h"
+#include"BIT_MATH.h"
+
+#include"RCC_interface.h"
+#include"DIO_interface.h"
+#include"TIM2_interface.h"
+
+void main (void)
+{
+	/*initialize clocks*/
+	RCC_voidInitSysClock();
+	/*Enable GPIOA clock */
+	RCC_voidEnableClock(RCC_APB2,2);
+	RCC_voidEnableClock(RCC_APB2,3);
+	/*Enable AFIO clock */
+	RCC_voidEnableClock(RCC_APB2,0);
+	/*Enable Timer2 clock*/
+	RCC_voidEnableClock(RCC_APB1,0);
+
+	/*mode must be alternative function push pull*/
+	MGPIO_VoidSetPinDirection(GPIOA,PIN3,OUTPUT_2MHZ_AFPP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN2,OUTPUT_2MHZ_PP);
+	//MGPIO_VoidSetPinDirection(GPIOA,PIN0,OUTPUT_2MHZ_PP);
+
+	MTIM2_voidInit();
+
+	while(1)
+	{
+
+		MGPIO_VoidSetPinValue(GPIOA , PIN2 ,HIGH);
+		MTIM2_voidOutputPWM(0);
+
+	}
+}
+
diff --git a/MCAL_Drivers/TIM3/include/TIM3_config.h b/MCAL_Drivers/TIM3/include/TIM3_config.h
new file mode 100755
index 0000000..ff17fb2
--- /dev/null
+++ b/MCAL_Drivers/TIM3/include/TIM3_config.h
@@ -0,0 +1,19 @@
+/*****************************************/
+/* Author  :  Gehad Elkoumy              */
+/* Version :  V02                        */
+/* Date    :  10 MAR 2023                */
+/*****************************************/
+
+#ifndef TIM3_CONFIG_H
+#define TIM3_CONFIG_H
+
+/* Options : 0 -- upcounter 
+			 1 -- downcounter  */
+#define		  CR1_DIR			0
+
+
+/* Options : 0 to 65535 	*/
+#define 	TIM_PRESCALER 		8
+
+
+#endif
diff --git a/MCAL_Drivers/TIM3/include/TIM3_interface.h b/MCAL_Drivers/TIM3/include/TIM3_interface.h
new file mode 100755
index 0000000..f330279
--- /dev/null
+++ b/MCAL_Drivers/TIM3/include/TIM3_interface.h
@@ -0,0 +1,27 @@
+/*****************************************/
+/* Author  :  Gehad Elkoumy              */
+/* Version :  V02                        */
+/* Date    :  10 MAR 2023                */
+/*****************************************/
+
+#ifndef TIM3_INTERFACE_H
+#define TIM3_INTERFACE_H
+
+void MTIM3_voidInit (void);
+void MTIM3_voidOutputPWM (u16 Copy_u16CompareValue);
+void MTIM3_voidSetBusyWait(u32 Copy_u16Ticks);
+
+#endif
+
+
+
+
+/*
+
+PWM freq = Fclk/(PSC*ARR)
+PWM duty cycle = CCR / ARR
+
+ex: if we want freq of 1KHz then Fclk = 8MHZ , ARR = 1000 , PSC = 8
+ pwm freq = 8M/(8*1000) = 1KHZ
+
+*/
diff --git a/MCAL_Drivers/TIM3/include/TIM3_private.h b/MCAL_Drivers/TIM3/include/TIM3_private.h
new file mode 100755
index 0000000..feae4aa
--- /dev/null
+++ b/MCAL_Drivers/TIM3/include/TIM3_private.h
@@ -0,0 +1,41 @@
+/*****************************************/
+/* Author  :  Gehad Elkoumy              */
+/* Version :  V02                        */
+/* Date    :  10 MAR 2023                */
+/*****************************************/
+
+#ifndef TIM3_PRIVATE_H
+#define TIM3_PRIVATE_H
+
+#define 	TIM3_Base_Address		0x40000400
+
+typedef struct
+{
+	volatile u32 CR1   ;
+	volatile u32 CR2   ;
+	volatile u32 SMCR  ;
+	volatile u32 DIER  ;
+	volatile u32 SR    ;
+	volatile u32 EGR   ;
+	volatile u32 CCMR1 ;
+	volatile u32 CCMR2 ;
+	volatile u32 CCER  ;
+	volatile u32 CNT   ;
+	volatile u32 PSC   ; 
+	volatile u32 ARR   ;
+	
+}TIMER_t;
+
+#define     TIM3    ((TIMER_t*) TIM3_Base_Address)
+
+
+#define 	CCR1	*((volatile u32*)(TIM3_Base_Address + 0x34))
+#define 	CCR2	*((volatile u32*)(TIM3_Base_Address + 0x38)) 
+#define 	CCR3	*((volatile u32*)(TIM3_Base_Address + 0x3C)) 
+#define 	CCR4	*((volatile u32*)(TIM3_Base_Address + 0x40)) 
+#define 	DCR		*((volatile u32*)(TIM3_Base_Address + 0x48)) 
+#define 	DMAR	*((volatile u32*)(TIM3_Base_Address + 0x4C)) 
+
+
+
+#endif
diff --git a/MCAL_Drivers/TIM3/src/TIM3_program.c b/MCAL_Drivers/TIM3/src/TIM3_program.c
new file mode 100755
index 0000000..194d1ce
--- /dev/null
+++ b/MCAL_Drivers/TIM3/src/TIM3_program.c
@@ -0,0 +1,72 @@
+/*****************************************/
+/* Author  :  Gehad Elkoumy              */
+/* Version :  V02                        */
+/* Date    :  10 MAR 2023                */
+/*****************************************/
+
+#include "STD_TYPES.h"
+#include "BIT_MATH.h"
+
+#include "TIM3_interface.h"
+#include "TIM3_private.h"
+#include "TIM3_config.h"
+
+void MTIM3_voidInit (void)
+{
+	
+	/*direction of counter when it is edge aligned mode , no need for this bit if centered aligned*/
+	CLR_BIT(TIM3 -> CR1 , 4);
+	TIM3->CR1 |= (CR1_DIR << 4);
+	
+	/*prescaler value*/
+	TIM3->PSC = TIM_PRESCALER;
+	
+	/*if there is interrupt then DIER_UIE must be enabled*/
+	SET_BIT(TIM3 -> DIER , 0);
+	
+	/*enable channel1*/
+	SET_BIT(TIM3->CCER , 0);
+
+	/*enable pwm mode 1 , channel1*/
+	CLR_BIT(TIM3->CCMR1 , 4);
+	SET_BIT(TIM3->CCMR1 , 5);
+	SET_BIT(TIM3->CCMR1 , 6);
+
+	/*enable output compare -- update value after overflow or immediately*/
+	CLR_BIT(TIM3->CCMR1 , 3);   //immediately , channel1
+
+	/*enable auto reload preload for PWM*/
+	SET_BIT(TIM3 -> CR1 , 7);
+
+	/*load desired value in ARR*/
+	TIM3->ARR  = 100;
+
+	/*enable counter*/
+	SET_BIT(TIM3 -> CR1 , 0);
+	/*enable update generation*/
+	SET_BIT(TIM3 -> EGR , 0);
+
+}
+
+void MTIM3_voidSetBusyWait(u32 Copy_u16Ticks)
+{
+	/* Load ticks to ARR register */
+	TIM3 -> ARR = Copy_u16Ticks;
+	/*start counter*/
+	SET_BIT(TIM3 -> CR1 , 0);
+	/* Wait till flag is raised */
+	while( (GET_BIT(TIM3 -> SR , 0)) == 0);
+	/*Stop counter*/
+	CLR_BIT(TIM3 -> CR1 , 0);
+	/*Clear flag*/
+	CLR_BIT(TIM3 -> SR , 0);
+
+}
+
+
+void MTIM3_voidOutputPWM (u16 Copy_u16CompareValue)
+{
+	/* load desired value -- channel 1 */
+	CCR1 = Copy_u16CompareValue;
+}
+
diff --git a/MCAL_Drivers/TIM3/src/main.c b/MCAL_Drivers/TIM3/src/main.c
new file mode 100755
index 0000000..e882008
--- /dev/null
+++ b/MCAL_Drivers/TIM3/src/main.c
@@ -0,0 +1,40 @@
+/*
+ * main.c
+ *
+ *  Created on: Mar 10, 2023
+ *      Author: Gehad
+ */
+
+#include"STD_TYPES.h"
+#include"BIT_MATH.h"
+
+#include"RCC_interface.h"
+#include"DIO_interface.h"
+#include"TIM3_interface.h"
+
+void main (void)
+{
+	/*initialize clocks*/
+	RCC_voidInitSysClock();
+	/*Enable GPIOA clock */
+	RCC_voidEnableClock(RCC_APB2,2);
+	RCC_voidEnableClock(RCC_APB2,3);
+	/*Enable AFIO clock */
+	RCC_voidEnableClock(RCC_APB2,0);
+	/*Enable Timer3 clock*/
+	RCC_voidEnableClock(RCC_APB1,1);
+
+	/*mode must be alternative function push pull (not considered as GPIO)*/
+	MGPIO_VoidSetPinDirection(GPIOA,PIN6,OUTPUT_2MHZ_AFPP);
+	MGPIO_VoidSetPinDirection(GPIOA,PIN5,OUTPUT_2MHZ_PP);
+
+	MTIM3_voidInit();
+
+
+	while(1)
+	{
+		MTIM3_voidOutputPWM(0);
+		MGPIO_VoidSetPinValue(GPIOA,PIN5,HIGH);
+	}
+}
+