fpu_ss with cv32e40x does not work

[davideschiavone]

Either the CPU or the co-processor do not work when running the matfadd example application.

The simulation in Questasim gets stuck, probably due to this error: openhwgroup/cv32e40x#800

while the simulation in Verilator does not even run.

To help debugging, I added in the core-v-mini-mcu.core the --profile-cfuncs option and -DVL_DEBUG=1 flag in the verilator_options as:

      verilator:
        mode: cc
        verilator_options:
          - '--cc'
          - '--trace'
          - '--trace-fst'
          - '--profile-cfuncs'
          - '--trace-structs'
          - '--trace-params'
          - '--trace-max-array 1024'
          - '--x-assign unique'
          - '--x-initial unique'
          - '--exe tb_top.cpp'
          - '-CFLAGS "-std=c++11 -Wall -g -fpermissive -DVL_DEBUG=1"'
          - '-LDFLAGS "-pthread -lutil -lelf"'
          - "-Wall"

and I added in the Verilated::debug(); function in the tb_top.cpp file:

int main (int argc, char * argv[])
{

  unsigned int SRAM_SIZE;
  std::string firmware, arg_max_sim_time, arg_openocd, arg_boot_sel, arg_execute_from_flash;
  unsigned int max_sim_time;
  bool use_openocd;
  bool run_all = false;
  int i,j, exit_val, boot_sel, execute_from_flash;
  Verilated::commandArgs(argc, argv);

  // Instantiate the model
  Vtestharness *dut = new Vtestharness;

  Verilated::debug();

  // Open VCD
  Verilated::traceEverOn (true);
  VerilatedFstC *m_trace = new VerilatedFstC;
  ....

then I did:

make mcu-gen CPU=cv32e40x
make verilator-sim FUSESOC_PARAM="--X_EXT=1"

cd build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-verilator
 ./Vtestharness +firmware=../../../sw/build/main.hex 

and I got as output:

[TESTBENCH]: No OpenOCD is used
[TESTBENCH]: loading firmware  ../../../sw/build/main.hex
[TESTBENCH]: No Max time specified
[TESTBENCH]: No Boot Option specified, using jtag (boot_sel=0)
                   0: the parameter COREV_PULP is 00000000
                   0: the parameter FPU is 00000000
                   0: the parameter ZFINX is 00000000
                   0: the parameter X_EXT is 00000001
                   0: the parameter ZFINX is 00000000
                   0: the parameter JTAG_DPI is 00000000
                   0: the parameter USE_EXTERNAL_DEVICE_EXAMPLE is 00000001
                   0: the parameter CLK_FREQUENCY is     100000 KHz
[X-HEEP]: NUM_BYTES =         64KB

UART: Created /dev/pts/3 for uart0. Connect to it with any terminal program, e.g.
$ screen /dev/pts/3
UART: Additionally writing all UART output to 'uart0.log'.
Reset Released
Set Exit Loop
Memory Loaded
-V{t0,1}- Verilated::debug is on. Message prefix indicates {<thread>,<sequence_number>}.
-V{t0,2}+    Vtestharness___024root___change_request
-V{t0,3}+    Vtestharness___024root___change_request_1
-V{t0,4}        CHANGE: ../../../hw/vendor/pulp_platform_cluster_interconnect/rtl/tcdm_variable_latency_interconnect/addr_dec_resp_mux_varlat.sv:34: testharness.x_heep_system_i.core_v_mini_mcu_i.system_bus_i.system_xbar_i.gen_xbar_1toM.xbar_varlat_one_to_n_i.u_xbar_varlat.__Vcellout__gen_inputs[0].i_addr_dec_resp_mux__req_o
-V{t0,5}        CHANGE: ../../../hw/vendor/pulp_platform_fpu_ss/src/fpu_ss.sv:84: testharness.gen_USE_EXTERNAL_DEVICE_EXAMPLE.gen_fpu_ss_wrapper.fpu_ss_wrapper_i.__Vcellout__fpu_ss_i__x_mem_req_o
-V{t0,6}        CHANGE: ../../../hw/vendor/pulp_platform_fpu_ss/src/fpu_ss.sv:82: testharness.gen_USE_EXTERNAL_DEVICE_EXAMPLE.gen_fpu_ss_wrapper.fpu_ss_wrapper_i.__Vcellout__fpu_ss_i__x_mem_valid_o
-V{t0,7}        CHANGE: ../../../hw/vendor/pulp_platform_common_cells/src/fifo_v3.sv:33: testharness.gen_USE_EXTERNAL_DEVICE_EXAMPLE.gen_fpu_ss_wrapper.fpu_ss_wrapper_i.fpu_ss_i.gen_input_stream_fifo.input_stream_fifo_i.__Vcellout__fifo_i__data_o
-V{t0,8}        CHANGE: ../../../hw/core-v-mini-mcu/xbar_varlat_n_to_one.sv:50: xbar_slave_req_req_outstanding
-V{t0,9}        CHANGE: ../../../hw/vendor/pulp_platform_common_cells/src/rr_arb_tree.sv:132: u_xbar_varlat.gen_outputs[0].gen_rr_arb_tree.i_rr_arb_tree.gen_arbiter.index_nodes
-V{t0,10}        CHANGE: ../../../hw/vendor/pulp_platform_common_cells/src/rr_arb_tree.sv:133: u_xbar_varlat.gen_outputs[0].gen_rr_arb_tree.i_rr_arb_tree.gen_arbiter.data_nodes
-V{t0,11}        CHANGE: ../../../hw/vendor/pulp_platform_common_cells/src/rr_arb_tree.sv:134: u_xbar_varlat.gen_outputs[0].gen_rr_arb_tree.i_rr_arb_tree.gen_arbiter.gnt_nodes
-V{t0,12}        CHANGE: ../../../hw/vendor/pulp_platform_common_cells/src/rr_arb_tree.sv:135: u_xbar_varlat.gen_outputs[0].gen_rr_arb_tree.i_rr_arb_tree.gen_arbiter.req_nodes
-V{t0,13}        CHANGE: ../../../hw/vendor/pulp_platform_common_cells/src/lzc.sv:51: u_xbar_varlat.gen_outputs[0].gen_rr_arb_tree.i_rr_arb_tree.gen_arbiter.gen_int_rr.gen_fair_arb.i_lzc_lower.gen_lzc.sel_nodes
-V{t0,14}        CHANGE: ../../../hw/vendor/pulp_platform_common_cells/src/lzc.sv:52: u_xbar_varlat.gen_outputs[0].gen_rr_arb_tree.i_rr_arb_tree.gen_arbiter.gen_int_rr.gen_fair_arb.i_lzc_lower.gen_lzc.index_nodes
-V{t0,15}        CHANGE: ../../../hw/vendor/pulp_platform_common_cells/src/rr_arb_tree.sv:133: u_xbar_varlat.gen_outputs[0].gen_rr_arb_tree.i_rr_arb_tree.gen_arbiter.data_nodes
%Error: ../../../tb/testharness.sv:9: Verilated model didn't converge
- See https://verilator.org/warn/DIDNOTCONVERGE