-
Notifications
You must be signed in to change notification settings - Fork 11
/
Copy pathmain.c
2151 lines (1852 loc) · 67.1 KB
/
main.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*--------------------------------------------------------------------*/
/*--- Callgrind ---*/
/*--- main.c ---*/
/*--------------------------------------------------------------------*/
/*
This file is part of Callgrind, a Valgrind tool for call graph
profiling programs.
Copyright (C) 2002-2017, Josef Weidendorfer ([email protected])
This tool is derived from and contains code from Cachegrind
Copyright (C) 2002-2017 Nicholas Nethercote ([email protected])
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 2 of the
License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>.
The GNU General Public License is contained in the file COPYING.
*/
#include "config.h"
#include "callgrind.h"
#include "global.h"
#include "pub_tool_threadstate.h"
#include "pub_tool_gdbserver.h"
#include "pub_tool_transtab.h" // VG_(discard_translations_safely)
#include "cg_branchpred.c"
/*------------------------------------------------------------*/
/*--- Global variables ---*/
/*------------------------------------------------------------*/
/* for all threads */
CommandLineOptions CLG_(clo);
Statistics CLG_(stat);
Bool CLG_(instrument_state) = True; /* Instrumentation on ? */
/* thread and signal handler specific */
exec_state CLG_(current_state);
/* min of L1 and LL cache line sizes. This only gets set to a
non-zero value if we are doing cache simulation. */
Int CLG_(min_line_size) = 0;
/*------------------------------------------------------------*/
/*--- Statistics ---*/
/*------------------------------------------------------------*/
static void CLG_(init_statistics)(Statistics* s)
{
s->call_counter = 0;
s->jcnd_counter = 0;
s->jump_counter = 0;
s->rec_call_counter = 0;
s->ret_counter = 0;
s->bb_executions = 0;
s->context_counter = 0;
s->bb_retranslations = 0;
s->distinct_objs = 0;
s->distinct_files = 0;
s->distinct_fns = 0;
s->distinct_contexts = 0;
s->distinct_bbs = 0;
s->distinct_bbccs = 0;
s->distinct_instrs = 0;
s->distinct_skips = 0;
s->bb_hash_resizes = 0;
s->bbcc_hash_resizes = 0;
s->jcc_hash_resizes = 0;
s->cxt_hash_resizes = 0;
s->fn_array_resizes = 0;
s->call_stack_resizes = 0;
s->fn_stack_resizes = 0;
s->full_debug_BBs = 0;
s->file_line_debug_BBs = 0;
s->fn_name_debug_BBs = 0;
s->no_debug_BBs = 0;
s->bbcc_lru_misses = 0;
s->jcc_lru_misses = 0;
s->cxt_lru_misses = 0;
s->bbcc_clones = 0;
}
/*------------------------------------------------------------*/
/*--- Simple callbacks (not cache similator) ---*/
/*------------------------------------------------------------*/
VG_REGPARM(1)
static void log_global_event(InstrInfo* ii)
{
ULong* cost_Bus;
CLG_DEBUG(6, "log_global_event: Ir %#lx/%u\n",
CLG_(bb_base) + ii->instr_offset, ii->instr_size);
if (!CLG_(current_state).collect) return;
CLG_ASSERT( (ii->eventset->mask & (1u<<EG_BUS))>0 );
CLG_(current_state).cost[ fullOffset(EG_BUS) ]++;
if (CLG_(current_state).nonskipped)
cost_Bus = CLG_(current_state).nonskipped->skipped + fullOffset(EG_BUS);
else
cost_Bus = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_BUS];
cost_Bus[0]++;
}
/* For branches, we consult two different predictors, one which
predicts taken/untaken for conditional branches, and the other
which predicts the branch target address for indirect branches
(jump-to-register style ones). */
static VG_REGPARM(2)
void log_cond_branch(InstrInfo* ii, Word taken)
{
Bool miss;
Int fullOffset_Bc;
ULong* cost_Bc;
CLG_DEBUG(6, "log_cond_branch: Ir %#lx, taken %ld\n",
CLG_(bb_base) + ii->instr_offset, taken);
miss = 1 & do_cond_branch_predict(CLG_(bb_base) + ii->instr_offset, taken);
if (!CLG_(current_state).collect) return;
CLG_ASSERT( (ii->eventset->mask & (1u<<EG_BC))>0 );
if (CLG_(current_state).nonskipped)
cost_Bc = CLG_(current_state).nonskipped->skipped + fullOffset(EG_BC);
else
cost_Bc = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_BC];
fullOffset_Bc = fullOffset(EG_BC);
CLG_(current_state).cost[ fullOffset_Bc ]++;
cost_Bc[0]++;
if (miss) {
CLG_(current_state).cost[ fullOffset_Bc+1 ]++;
cost_Bc[1]++;
}
}
static VG_REGPARM(2)
void log_ind_branch(InstrInfo* ii, UWord actual_dst)
{
Bool miss;
Int fullOffset_Bi;
ULong* cost_Bi;
CLG_DEBUG(6, "log_ind_branch: Ir %#lx, dst %#lx\n",
CLG_(bb_base) + ii->instr_offset, actual_dst);
miss = 1 & do_ind_branch_predict(CLG_(bb_base) + ii->instr_offset, actual_dst);
if (!CLG_(current_state).collect) return;
CLG_ASSERT( (ii->eventset->mask & (1u<<EG_BI))>0 );
if (CLG_(current_state).nonskipped)
cost_Bi = CLG_(current_state).nonskipped->skipped + fullOffset(EG_BI);
else
cost_Bi = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_BI];
fullOffset_Bi = fullOffset(EG_BI);
CLG_(current_state).cost[ fullOffset_Bi ]++;
cost_Bi[0]++;
if (miss) {
CLG_(current_state).cost[ fullOffset_Bi+1 ]++;
cost_Bi[1]++;
}
}
/*------------------------------------------------------------*/
/*--- Instrumentation structures and event queue handling ---*/
/*------------------------------------------------------------*/
/* Maintain an ordered list of memory events which are outstanding, in
the sense that no IR has yet been generated to do the relevant
helper calls. The BB is scanned top to bottom and memory events
are added to the end of the list, merging with the most recent
notified event where possible (Dw immediately following Dr and
having the same size and EA can be merged).
This merging is done so that for architectures which have
load-op-store instructions (x86, amd64), the insn is treated as if
it makes just one memory reference (a modify), rather than two (a
read followed by a write at the same address).
At various points the list will need to be flushed, that is, IR
generated from it. That must happen before any possible exit from
the block (the end, or an IRStmt_Exit). Flushing also takes place
when there is no space to add a new event.
If we require the simulation statistics to be up to date with
respect to possible memory exceptions, then the list would have to
be flushed before each memory reference. That would however lose
performance by inhibiting event-merging during flushing.
Flushing the list consists of walking it start to end and emitting
instrumentation IR for each event, in the order in which they
appear. It may be possible to emit a single call for two adjacent
events in order to reduce the number of helper function calls made.
For example, it could well be profitable to handle two adjacent Ir
events with a single helper call. */
typedef
IRExpr
IRAtom;
typedef
enum {
Ev_Ir, // Instruction read
Ev_Dr, // Data read
Ev_Dw, // Data write
Ev_Dm, // Data modify (read then write)
Ev_Bc, // branch conditional
Ev_Bi, // branch indirect (to unknown destination)
Ev_G // Global bus event
}
EventTag;
typedef
struct {
EventTag tag;
InstrInfo* inode;
union {
struct {
} Ir;
struct {
IRAtom* ea;
Int szB;
} Dr;
struct {
IRAtom* ea;
Int szB;
} Dw;
struct {
IRAtom* ea;
Int szB;
} Dm;
struct {
IRAtom* taken; /* :: Ity_I1 */
} Bc;
struct {
IRAtom* dst;
} Bi;
struct {
} G;
} Ev;
}
Event;
static void init_Event ( Event* ev ) {
VG_(memset)(ev, 0, sizeof(Event));
}
static IRAtom* get_Event_dea ( Event* ev ) {
switch (ev->tag) {
case Ev_Dr: return ev->Ev.Dr.ea;
case Ev_Dw: return ev->Ev.Dw.ea;
case Ev_Dm: return ev->Ev.Dm.ea;
default: tl_assert(0);
}
}
static Int get_Event_dszB ( Event* ev ) {
switch (ev->tag) {
case Ev_Dr: return ev->Ev.Dr.szB;
case Ev_Dw: return ev->Ev.Dw.szB;
case Ev_Dm: return ev->Ev.Dm.szB;
default: tl_assert(0);
}
}
/* Up to this many unnotified events are allowed. Number is
arbitrary. Larger numbers allow more event merging to occur, but
potentially induce more spilling due to extending live ranges of
address temporaries. */
#define N_EVENTS 16
/* A struct which holds all the running state during instrumentation.
Mostly to avoid passing loads of parameters everywhere. */
typedef struct {
/* The current outstanding-memory-event list. */
Event events[N_EVENTS];
Int events_used;
/* The array of InstrInfo's is part of BB struct. */
BB* bb;
/* BB seen before (ie. re-instrumentation) */
Bool seen_before;
/* Number InstrInfo bins 'used' so far. */
UInt ii_index;
// current offset of guest instructions from BB start
UInt instr_offset;
/* The output SB being constructed. */
IRSB* sbOut;
} ClgState;
static void showEvent ( Event* ev )
{
switch (ev->tag) {
case Ev_Ir:
VG_(printf)("Ir (InstrInfo %p) at +%u\n",
ev->inode, ev->inode->instr_offset);
break;
case Ev_Dr:
VG_(printf)("Dr (InstrInfo %p) at +%u %d EA=",
ev->inode, ev->inode->instr_offset, ev->Ev.Dr.szB);
ppIRExpr(ev->Ev.Dr.ea);
VG_(printf)("\n");
break;
case Ev_Dw:
VG_(printf)("Dw (InstrInfo %p) at +%u %d EA=",
ev->inode, ev->inode->instr_offset, ev->Ev.Dw.szB);
ppIRExpr(ev->Ev.Dw.ea);
VG_(printf)("\n");
break;
case Ev_Dm:
VG_(printf)("Dm (InstrInfo %p) at +%u %d EA=",
ev->inode, ev->inode->instr_offset, ev->Ev.Dm.szB);
ppIRExpr(ev->Ev.Dm.ea);
VG_(printf)("\n");
break;
case Ev_Bc:
VG_(printf)("Bc %p GA=", ev->inode);
ppIRExpr(ev->Ev.Bc.taken);
VG_(printf)("\n");
break;
case Ev_Bi:
VG_(printf)("Bi %p DST=", ev->inode);
ppIRExpr(ev->Ev.Bi.dst);
VG_(printf)("\n");
break;
case Ev_G:
VG_(printf)("G %p\n", ev->inode);
break;
default:
tl_assert(0);
break;
}
}
/* Generate code for all outstanding memory events, and mark the queue
empty. Code is generated into cgs->sbOut, and this activity
'consumes' slots in cgs->bb. */
static void flushEvents ( ClgState* clgs )
{
Int i, regparms, inew;
const HChar* helperName;
void* helperAddr;
IRExpr** argv;
IRExpr* i_node_expr;
IRDirty* di;
Event* ev;
Event* ev2;
Event* ev3;
if (!clgs->seen_before) {
// extend event sets as needed
// available sets: D0 Dr
for(i=0; i<clgs->events_used; i++) {
ev = &clgs->events[i];
switch(ev->tag) {
case Ev_Ir:
// Ir event always is first for a guest instruction
CLG_ASSERT(ev->inode->eventset == 0);
ev->inode->eventset = CLG_(sets).base;
break;
case Ev_Dr:
// extend event set by Dr counters
ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset,
EG_DR);
break;
case Ev_Dw:
case Ev_Dm:
// extend event set by Dw counters
ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset,
EG_DW);
break;
case Ev_Bc:
// extend event set by Bc counters
ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset,
EG_BC);
break;
case Ev_Bi:
// extend event set by Bi counters
ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset,
EG_BI);
break;
case Ev_G:
// extend event set by Bus counter
ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset,
EG_BUS);
break;
default:
tl_assert(0);
}
}
}
for(i = 0; i < clgs->events_used; i = inew) {
helperName = NULL;
helperAddr = NULL;
argv = NULL;
regparms = 0;
/* generate IR to notify event i and possibly the ones
immediately following it. */
tl_assert(i >= 0 && i < clgs->events_used);
ev = &clgs->events[i];
ev2 = ( i < clgs->events_used-1 ? &clgs->events[i+1] : NULL );
ev3 = ( i < clgs->events_used-2 ? &clgs->events[i+2] : NULL );
CLG_DEBUGIF(5) {
VG_(printf)(" flush ");
showEvent( ev );
}
i_node_expr = mkIRExpr_HWord( (HWord)ev->inode );
/* Decide on helper fn to call and args to pass it, and advance
i appropriately.
Dm events have same effect as Dw events */
switch (ev->tag) {
case Ev_Ir:
/* Merge an Ir with a following Dr. */
if (ev2 && ev2->tag == Ev_Dr) {
/* Why is this true? It's because we're merging an Ir
with a following Dr. The Ir derives from the
instruction's IMark and the Dr from data
references which follow it. In short it holds
because each insn starts with an IMark, hence an
Ev_Ir, and so these Dr must pertain to the
immediately preceding Ir. Same applies to analogous
assertions in the subsequent cases. */
tl_assert(ev2->inode == ev->inode);
helperName = CLG_(cachesim).log_1I1Dr_name;
helperAddr = CLG_(cachesim).log_1I1Dr;
argv = mkIRExprVec_3( i_node_expr,
get_Event_dea(ev2),
mkIRExpr_HWord( get_Event_dszB(ev2) ) );
regparms = 3;
inew = i+2;
}
/* Merge an Ir with a following Dw/Dm. */
else
if (ev2 && (ev2->tag == Ev_Dw || ev2->tag == Ev_Dm)) {
tl_assert(ev2->inode == ev->inode);
helperName = CLG_(cachesim).log_1I1Dw_name;
helperAddr = CLG_(cachesim).log_1I1Dw;
argv = mkIRExprVec_3( i_node_expr,
get_Event_dea(ev2),
mkIRExpr_HWord( get_Event_dszB(ev2) ) );
regparms = 3;
inew = i+2;
}
/* Merge an Ir with two following Irs. */
else
if (ev2 && ev3 && ev2->tag == Ev_Ir && ev3->tag == Ev_Ir) {
helperName = CLG_(cachesim).log_3I0D_name;
helperAddr = CLG_(cachesim).log_3I0D;
argv = mkIRExprVec_3( i_node_expr,
mkIRExpr_HWord( (HWord)ev2->inode ),
mkIRExpr_HWord( (HWord)ev3->inode ) );
regparms = 3;
inew = i+3;
}
/* Merge an Ir with one following Ir. */
else
if (ev2 && ev2->tag == Ev_Ir) {
helperName = CLG_(cachesim).log_2I0D_name;
helperAddr = CLG_(cachesim).log_2I0D;
argv = mkIRExprVec_2( i_node_expr,
mkIRExpr_HWord( (HWord)ev2->inode ) );
regparms = 2;
inew = i+2;
}
/* No merging possible; emit as-is. */
else {
helperName = CLG_(cachesim).log_1I0D_name;
helperAddr = CLG_(cachesim).log_1I0D;
argv = mkIRExprVec_1( i_node_expr );
regparms = 1;
inew = i+1;
}
break;
case Ev_Dr:
/* Data read or modify */
helperName = CLG_(cachesim).log_0I1Dr_name;
helperAddr = CLG_(cachesim).log_0I1Dr;
argv = mkIRExprVec_3( i_node_expr,
get_Event_dea(ev),
mkIRExpr_HWord( get_Event_dszB(ev) ) );
regparms = 3;
inew = i+1;
break;
case Ev_Dw:
case Ev_Dm:
/* Data write */
helperName = CLG_(cachesim).log_0I1Dw_name;
helperAddr = CLG_(cachesim).log_0I1Dw;
argv = mkIRExprVec_3( i_node_expr,
get_Event_dea(ev),
mkIRExpr_HWord( get_Event_dszB(ev) ) );
regparms = 3;
inew = i+1;
break;
case Ev_Bc:
/* Conditional branch */
helperName = "log_cond_branch";
helperAddr = &log_cond_branch;
argv = mkIRExprVec_2( i_node_expr, ev->Ev.Bc.taken );
regparms = 2;
inew = i+1;
break;
case Ev_Bi:
/* Branch to an unknown destination */
helperName = "log_ind_branch";
helperAddr = &log_ind_branch;
argv = mkIRExprVec_2( i_node_expr, ev->Ev.Bi.dst );
regparms = 2;
inew = i+1;
break;
case Ev_G:
/* Global bus event (CAS, LOCK-prefix, LL-SC, etc) */
helperName = "log_global_event";
helperAddr = &log_global_event;
argv = mkIRExprVec_1( i_node_expr );
regparms = 1;
inew = i+1;
break;
default:
tl_assert(0);
}
CLG_DEBUGIF(5) {
if (inew > i+1) {
VG_(printf)(" merge ");
showEvent( ev2 );
}
if (inew > i+2) {
VG_(printf)(" merge ");
showEvent( ev3 );
}
if (helperAddr)
VG_(printf)(" call %s (%p)\n",
helperName, helperAddr);
}
/* helper could be unset depending on the simulator used */
if (helperAddr == 0) continue;
/* Add the helper. */
tl_assert(helperName);
tl_assert(helperAddr);
tl_assert(argv);
di = unsafeIRDirty_0_N( regparms,
helperName, VG_(fnptr_to_fnentry)( helperAddr ),
argv );
addStmtToIRSB( clgs->sbOut, IRStmt_Dirty(di) );
}
clgs->events_used = 0;
}
static void addEvent_Ir ( ClgState* clgs, InstrInfo* inode )
{
Event* evt;
tl_assert(clgs->seen_before || (inode->eventset == 0));
if (!CLG_(clo).simulate_cache) return;
if (clgs->events_used == N_EVENTS)
flushEvents(clgs);
tl_assert(clgs->events_used >= 0 && clgs->events_used < N_EVENTS);
evt = &clgs->events[clgs->events_used];
init_Event(evt);
evt->tag = Ev_Ir;
evt->inode = inode;
clgs->events_used++;
}
static
void addEvent_Dr ( ClgState* clgs, InstrInfo* inode, Int datasize, IRAtom* ea )
{
Event* evt;
tl_assert(isIRAtom(ea));
tl_assert(datasize >= 1);
if (!CLG_(clo).simulate_cache) return;
tl_assert(datasize <= CLG_(min_line_size));
if (clgs->events_used == N_EVENTS)
flushEvents(clgs);
tl_assert(clgs->events_used >= 0 && clgs->events_used < N_EVENTS);
evt = &clgs->events[clgs->events_used];
init_Event(evt);
evt->tag = Ev_Dr;
evt->inode = inode;
evt->Ev.Dr.szB = datasize;
evt->Ev.Dr.ea = ea;
clgs->events_used++;
}
static
void addEvent_Dw ( ClgState* clgs, InstrInfo* inode, Int datasize, IRAtom* ea )
{
Event* evt;
tl_assert(isIRAtom(ea));
tl_assert(datasize >= 1);
if (!CLG_(clo).simulate_cache) return;
tl_assert(datasize <= CLG_(min_line_size));
/* Is it possible to merge this write with the preceding read? */
if (clgs->events_used > 0) {
Event* lastEvt = &clgs->events[clgs->events_used-1];
if ( lastEvt->tag == Ev_Dr
&& lastEvt->Ev.Dr.szB == datasize
&& lastEvt->inode == inode
&& eqIRAtom(lastEvt->Ev.Dr.ea, ea))
{
lastEvt->tag = Ev_Dm;
return;
}
}
/* No. Add as normal. */
if (clgs->events_used == N_EVENTS)
flushEvents(clgs);
tl_assert(clgs->events_used >= 0 && clgs->events_used < N_EVENTS);
evt = &clgs->events[clgs->events_used];
init_Event(evt);
evt->tag = Ev_Dw;
evt->inode = inode;
evt->Ev.Dw.szB = datasize;
evt->Ev.Dw.ea = ea;
clgs->events_used++;
}
static
void addEvent_D_guarded ( ClgState* clgs, InstrInfo* inode,
Int datasize, IRAtom* ea, IRAtom* guard,
Bool isWrite )
{
tl_assert(isIRAtom(ea));
tl_assert(guard);
tl_assert(isIRAtom(guard));
tl_assert(datasize >= 1);
if (!CLG_(clo).simulate_cache) return;
tl_assert(datasize <= CLG_(min_line_size));
/* Adding guarded memory actions and merging them with the existing
queue is too complex. Simply flush the queue and add this
action immediately. Since guarded loads and stores are pretty
rare, this is not thought likely to cause any noticeable
performance loss as a result of the loss of event-merging
opportunities. */
tl_assert(clgs->events_used >= 0);
flushEvents(clgs);
tl_assert(clgs->events_used == 0);
/* Same as case Ev_Dw / case Ev_Dr in flushEvents, except with guard */
IRExpr* i_node_expr;
const HChar* helperName;
void* helperAddr;
IRExpr** argv;
Int regparms;
IRDirty* di;
i_node_expr = mkIRExpr_HWord( (HWord)inode );
helperName = isWrite ? CLG_(cachesim).log_0I1Dw_name
: CLG_(cachesim).log_0I1Dr_name;
helperAddr = isWrite ? CLG_(cachesim).log_0I1Dw
: CLG_(cachesim).log_0I1Dr;
argv = mkIRExprVec_3( i_node_expr,
ea, mkIRExpr_HWord( datasize ) );
regparms = 3;
di = unsafeIRDirty_0_N(
regparms,
helperName, VG_(fnptr_to_fnentry)( helperAddr ),
argv );
di->guard = guard;
addStmtToIRSB( clgs->sbOut, IRStmt_Dirty(di) );
}
static
void addEvent_Bc ( ClgState* clgs, InstrInfo* inode, IRAtom* guard )
{
Event* evt;
tl_assert(isIRAtom(guard));
tl_assert(typeOfIRExpr(clgs->sbOut->tyenv, guard)
== (sizeof(RegWord)==4 ? Ity_I32 : Ity_I64));
if (!CLG_(clo).simulate_branch) return;
if (clgs->events_used == N_EVENTS)
flushEvents(clgs);
tl_assert(clgs->events_used >= 0 && clgs->events_used < N_EVENTS);
evt = &clgs->events[clgs->events_used];
init_Event(evt);
evt->tag = Ev_Bc;
evt->inode = inode;
evt->Ev.Bc.taken = guard;
clgs->events_used++;
}
static
void addEvent_Bi ( ClgState* clgs, InstrInfo* inode, IRAtom* whereTo )
{
Event* evt;
tl_assert(isIRAtom(whereTo));
tl_assert(typeOfIRExpr(clgs->sbOut->tyenv, whereTo)
== (sizeof(RegWord)==4 ? Ity_I32 : Ity_I64));
if (!CLG_(clo).simulate_branch) return;
if (clgs->events_used == N_EVENTS)
flushEvents(clgs);
tl_assert(clgs->events_used >= 0 && clgs->events_used < N_EVENTS);
evt = &clgs->events[clgs->events_used];
init_Event(evt);
evt->tag = Ev_Bi;
evt->inode = inode;
evt->Ev.Bi.dst = whereTo;
clgs->events_used++;
}
static
void addEvent_G ( ClgState* clgs, InstrInfo* inode )
{
Event* evt;
if (!CLG_(clo).collect_bus) return;
if (clgs->events_used == N_EVENTS)
flushEvents(clgs);
tl_assert(clgs->events_used >= 0 && clgs->events_used < N_EVENTS);
evt = &clgs->events[clgs->events_used];
init_Event(evt);
evt->tag = Ev_G;
evt->inode = inode;
clgs->events_used++;
}
/* Initialise or check (if already seen before) an InstrInfo for next insn.
We only can set instr_offset/instr_size here. The required event set and
resulting cost offset depend on events (Ir/Dr/Dw/Dm) in guest
instructions. The event set is extended as required on flush of the event
queue (when Dm events were determined), cost offsets are determined at
end of BB instrumentation. */
static
InstrInfo* next_InstrInfo ( ClgState* clgs, UInt instr_size )
{
InstrInfo* ii;
tl_assert(clgs->ii_index >= 0);
tl_assert(clgs->ii_index < clgs->bb->instr_count);
ii = &clgs->bb->instr[ clgs->ii_index ];
if (clgs->seen_before) {
CLG_ASSERT(ii->instr_offset == clgs->instr_offset);
CLG_ASSERT(ii->instr_size == instr_size);
}
else {
ii->instr_offset = clgs->instr_offset;
ii->instr_size = instr_size;
ii->cost_offset = 0;
ii->eventset = 0;
}
clgs->ii_index++;
clgs->instr_offset += instr_size;
CLG_(stat).distinct_instrs++;
return ii;
}
// return total number of cost values needed for this BB
static
UInt update_cost_offsets( ClgState* clgs )
{
Int i;
InstrInfo* ii;
UInt cost_offset = 0;
CLG_ASSERT(clgs->bb->instr_count == clgs->ii_index);
for(i=0; i<clgs->ii_index; i++) {
ii = &clgs->bb->instr[i];
if (clgs->seen_before) {
CLG_ASSERT(ii->cost_offset == cost_offset);
} else
ii->cost_offset = cost_offset;
cost_offset += ii->eventset ? ii->eventset->size : 0;
}
return cost_offset;
}
/*------------------------------------------------------------*/
/*--- Instrumentation ---*/
/*------------------------------------------------------------*/
#if defined(VG_BIGENDIAN)
# define CLGEndness Iend_BE
#elif defined(VG_LITTLEENDIAN)
# define CLGEndness Iend_LE
#else
# error "Unknown endianness"
#endif
static
Addr IRConst2Addr(IRConst* con)
{
Addr addr;
if (sizeof(RegWord) == 4) {
CLG_ASSERT( con->tag == Ico_U32 );
addr = con->Ico.U32;
}
else if (sizeof(RegWord) == 8) {
CLG_ASSERT( con->tag == Ico_U64 );
addr = con->Ico.U64;
}
else
VG_(tool_panic)("Callgrind: invalid Addr type");
return addr;
}
/* First pass over a BB to instrument, counting instructions and jumps
* This is needed for the size of the BB struct to allocate
*
* Called from CLG_(get_bb)
*/
void CLG_(collectBlockInfo)(IRSB* sbIn,
/*INOUT*/ UInt* instrs,
/*INOUT*/ UInt* cjmps,
/*INOUT*/ Bool* cjmp_inverted)
{
Int i;
IRStmt* st;
Addr instrAddr =0, jumpDst;
UInt instrLen = 0;
Bool toNextInstr = False;
// Ist_Exit has to be ignored in preamble code, before first IMark:
// preamble code is added by VEX for self modifying code, and has
// nothing to do with client code
Bool inPreamble = True;
if (!sbIn) return;
for (i = 0; i < sbIn->stmts_used; i++) {
st = sbIn->stmts[i];
if (Ist_IMark == st->tag) {
inPreamble = False;
instrAddr = st->Ist.IMark.addr;
instrLen = st->Ist.IMark.len;
(*instrs)++;
toNextInstr = False;
}
if (inPreamble) continue;
if (Ist_Exit == st->tag) {
jumpDst = IRConst2Addr(st->Ist.Exit.dst);
toNextInstr = (jumpDst == instrAddr + instrLen);
(*cjmps)++;
}
}
/* if the last instructions of BB conditionally jumps to next instruction
* (= first instruction of next BB in memory), this is a inverted by VEX.
*/
*cjmp_inverted = toNextInstr;
}
static
void addConstMemStoreStmt( IRSB* bbOut, UWord addr, UInt val, IRType hWordTy)
{
addStmtToIRSB( bbOut,
IRStmt_Store(CLGEndness,
IRExpr_Const(hWordTy == Ity_I32 ?
IRConst_U32( addr ) :
IRConst_U64( addr )),
IRExpr_Const(IRConst_U32(val)) ));
}
/* add helper call to setup_bbcc, with pointer to BB struct as argument
*
* precondition for setup_bbcc:
* - jmps_passed has number of cond.jumps passed in last executed BB
* - current_bbcc has a pointer to the BBCC of the last executed BB
* Thus, if bbcc_jmpkind is != -1 (JmpNone),
* current_bbcc->bb->jmp_addr
* gives the address of the jump source.
*
* the setup does 2 things:
* - trace call:
* * Unwind own call stack, i.e sync our ESP with real ESP
* This is for ESP manipulation (longjmps, C++ exec handling) and RET
* * For CALLs or JMPs crossing objects, record call arg +
* push are on own call stack
*
* - prepare for cache log functions:
* set current_bbcc to BBCC that gets the costs for this BB execution
* attached
*/
static
void addBBSetupCall(ClgState* clgs)
{
IRDirty* di;
IRExpr *arg1, **argv;
arg1 = mkIRExpr_HWord( (HWord)clgs->bb );
argv = mkIRExprVec_1(arg1);
di = unsafeIRDirty_0_N( 1, "setup_bbcc",
VG_(fnptr_to_fnentry)( & CLG_(setup_bbcc) ),
argv);
addStmtToIRSB( clgs->sbOut, IRStmt_Dirty(di) );
}
static
IRSB* CLG_(instrument)( VgCallbackClosure* closure,
IRSB* sbIn,
const VexGuestLayout* layout,
const VexGuestExtents* vge,
const VexArchInfo* archinfo_host,
IRType gWordTy, IRType hWordTy )
{
Int i;
IRStmt* st;
Addr origAddr;
InstrInfo* curr_inode = NULL;
ClgState clgs;
UInt cJumps = 0;
IRTypeEnv* tyenv = sbIn->tyenv;
if (gWordTy != hWordTy) {
/* We don't currently support this case. */
VG_(tool_panic)("host/guest word size mismatch");
}
// No instrumentation if it is switched off
if (! CLG_(instrument_state)) {
CLG_DEBUG(5, "instrument(BB %#lx) [Instrumentation OFF]\n",
(Addr)closure->readdr);
return sbIn;
}
CLG_DEBUG(3, "+ instrument(BB %#lx)\n", (Addr)closure->readdr);
/* Set up SB for instrumented IR */
clgs.sbOut = deepCopyIRSBExceptStmts(sbIn);
// Copy verbatim any IR preamble preceding the first IMark
i = 0;
while (i < sbIn->stmts_used && sbIn->stmts[i]->tag != Ist_IMark) {
addStmtToIRSB( clgs.sbOut, sbIn->stmts[i] );
i++;
}
// Get the first statement, and origAddr from it
CLG_ASSERT(sbIn->stmts_used >0);
CLG_ASSERT(i < sbIn->stmts_used);
st = sbIn->stmts[i];
CLG_ASSERT(Ist_IMark == st->tag);
origAddr = st->Ist.IMark.addr + st->Ist.IMark.delta;
CLG_ASSERT(origAddr == st->Ist.IMark.addr
+ st->Ist.IMark.delta); // XXX: check no overflow
/* Get BB struct (creating if necessary).