From 9f769897ae546746e748b16f8022148eb5d3db4d Mon Sep 17 00:00:00 2001 From: Woze Parrot Date: Sun, 6 Feb 2022 12:41:33 -0500 Subject: [PATCH] feat: initial commit --- .envrc | 1 + .gitignore | 3 + LICENSE | 427 ++++++++++++++++++++++++++++++++++++++++++++++++++++ README.md | 18 +++ flake.lock | 43 ++++++ flake.nix | 42 ++++++ spec32.adoc | 92 +++++++++++ 7 files changed, 626 insertions(+) create mode 100644 .envrc create mode 100644 .gitignore create mode 100644 LICENSE create mode 100644 README.md create mode 100644 flake.lock create mode 100644 flake.nix create mode 100644 spec32.adoc diff --git a/.envrc b/.envrc new file mode 100644 index 0000000..3550a30 --- /dev/null +++ b/.envrc @@ -0,0 +1 @@ +use flake diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..bb8ea42 --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +.direnv/ +result +*.pdf diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..3b7b82d --- /dev/null +++ b/LICENSE @@ -0,0 +1,427 @@ +Attribution-ShareAlike 4.0 International + +======================================================================= + +Creative Commons Corporation ("Creative Commons") is not a law firm and +does not provide legal services or legal advice. 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For +the avoidance of doubt, this paragraph does not form part of the +public licenses. + +Creative Commons may be contacted at creativecommons.org. diff --git a/README.md b/README.md new file mode 100644 index 0000000..a058040 --- /dev/null +++ b/README.md @@ -0,0 +1,18 @@ +# skyror ISA + +A minimal RISC inspired ISA. + +## skyror32 + +The 32-bit version of skyror. + +[Spec](./spec32.adoc) + +## Building the PDF Version + +1. Install [Nix](https://nixos.org/download.html) +2. `nix build .#skyror32` for the 32-bit version + +## License + +This work is licensed under a [Creative Commons Attribution-ShareAlike 4.0 International License](http://creativecommons.org/licenses/by-sa/4.0/). diff --git a/flake.lock b/flake.lock new file mode 100644 index 0000000..0c6a54a --- /dev/null +++ b/flake.lock @@ -0,0 +1,43 @@ +{ + "nodes": { + "flake-utils": { + "locked": { + "lastModified": 1667395993, + "narHash": "sha256-nuEHfE/LcWyuSWnS8t12N1wc105Qtau+/OdUAjtQ0rA=", + "owner": "numtide", + "repo": "flake-utils", + "rev": "5aed5285a952e0b949eb3ba02c12fa4fcfef535f", + "type": "github" + }, + "original": { + "owner": "numtide", + "repo": "flake-utils", + "type": "github" + } + }, + "nixpkgs": { + "locked": { + "lastModified": 1669387357, + "narHash": "sha256-z1azVj/5Em5kGhh9OgBOsjTEgMab7hXL/aRilH9tzyI=", + "owner": "nixos", + "repo": "nixpkgs", + "rev": "55b3f68bda6d4f4dc6092eed0508063f154fa4fd", + "type": "github" + }, + "original": { + "owner": "nixos", + "ref": "nixpkgs-unstable", + "repo": "nixpkgs", + "type": "github" + } + }, + "root": { + "inputs": { + "flake-utils": "flake-utils", + "nixpkgs": "nixpkgs" + } + } + }, + "root": "root", + "version": 7 +} diff --git a/flake.nix b/flake.nix new file mode 100644 index 0000000..6cd4ce9 --- /dev/null +++ b/flake.nix @@ -0,0 +1,42 @@ +{ + description = "skyror: instruction set endgame."; + + inputs.nixpkgs.url = "github:nixos/nixpkgs/nixpkgs-unstable"; + inputs.flake-utils.url = "github:numtide/flake-utils"; + + outputs = { + self, + nixpkgs, + flake-utils, + ... + }: + flake-utils.lib.eachDefaultSystem + ( + system: let + pkgs = import nixpkgs { + inherit system; + }; + in { + packages.skyror32 = pkgs.stdenv.mkDerivation { + pname = "skyror32"; + version = "0.1.0"; + src = ./.; + + nativeBuildInputs = with pkgs; [asciidoctor-with-extensions]; + + installPhase = '' + mkdir -p $out + asciidoctor-pdf -n ./spec32.adoc -o $out/skyror32.pdf + ''; + }; + + devShells.default = pkgs.mkShell { + name = "skyror"; + nativeBuildInputs = with pkgs; [ + asciidoctor-with-extensions + entr + ]; + }; + } + ); +} diff --git a/spec32.adoc b/spec32.adoc new file mode 100644 index 0000000..2a7ec05 --- /dev/null +++ b/spec32.adoc @@ -0,0 +1,92 @@ += skyror32 ISA +:revnumber: 0.1.0 + +:doctype: article +:encoding: utf-8 +:lang: en +:toc: + +== Base Architecture + +The base architecture is the minimum requirement of a skyror32 implementation. It provides both control flow as well as integer instructions. + +=== Registers + +The base skyror32 ISA consists of 256 general purpose registers with 8 registers being reserved for special purposes. + +|=== +|Register |Alias |Purpose + +|`r0` |`z` |Always Zero +|`r1` |`pc` |Program Counter +|`r2` |`v` |Vector +|`r3`-`r7` | |Reserved +|`r8`-`r255`| |General Purpose +|=== + +==== `z` Register + +Hard-wired to zero. Writing to the register does nothing. + +==== `pc` Register + +A read-only register that stores the memory address of the current instruction. Writing to the register does nothing. + +==== `v` Register + +When set to a value other than 0x0, instructions will be treated as vector instructions. The first 6 bits of this register determines the length of the vector. The other 2 bits determines how many registers the vector instruction will skip as well as how the vector instruction treats the `REGs1` and `REGs2` registers following the chart below. These vector instructions will run from `REGd` and end at `REGd` + ``. + +|=== +|Bits|Description + +|00 |Both REGs1 and REGs2 are locked +|01 |REGs1 is locked +|10 |REGs2 is locked +|11 |Skips two registers +|=== + +=== Instruction Encoding + +The base skyror32 ISA contains 2 instruction formats: X and Y. Each instruction is always 32 bits wide and always starts with a 7-bit opcode. The register id is 8-bits long. + +[%autowidth] +|=== +|Format|Operands + +|X |Reg, Reg, Reg +|Y |Reg, 16-bit Immediate +|=== + +|=== +|Format 32+^|Bits + +| |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0 +|X |0 8+^|REGs2 8+^|REGs1 8+^|REGd 7+^|OPCODE +|Y |HL 16+^|16-bit Immediate 8+^|REGd 7+^|OPCODE +|=== + +[%autowidth] +|=== +|Field |Description + +|HL |Puts the immediate in high bits or low bits. +|REGd |Destination register id, 8 bits wide. +|REGs1 |Source register 1 id, 8 bits wide. +|REGs2 |Source register 2 id, 8 bits wide. +|OPCODE |Operation, follows encoding specified below. +|=== + +==== Opcode Encoding + +The least significant bit of the opcode is used to determine the instruction format. + +[%autowidth] +|=== +|Bit|Format + +|0 |Format X +|1 |Format Y +|=== + +=== Instructions +