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skyror32 Instruction Set Manual

This document describes the skyror32 instruction set architecture.

This document is a work in progress, implementations that decide to use the instruction set in its current state should watch for breaking changes.

This document is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License.

Introduction

Overview

skyror32 is a free and open source hybrid instruction set architecture mainly inspired by RISC style architectures. It is designed to be small, simple, and highly scalable. It is designed mainly for use in accelerators, but can be used freely anywhere else. The ISA does not have a target towards code density.

skyror32 is a load-store architecture that like RISC-V is split into a tiny base instruction set with optional standardized and non-standardized extensions. The non-standardized extension system allows third-party extensions to be implemented.

Base Architecture

The base architecture is the minimum requirement of a skyror32 implementation. It provides both control flow as well as integer instructions.

Registers

skyror32 has a total of 128 registers split into 112 general purpose registers and 16 reserved system registers.

Each general purpose register is 32 bits wide. All general purpose registers are vectorized registers, meaning that they have a implementation defined depth. These registers can also be used by extensions as long as they are not reserved by the extension. They are shown here being prefixed with g and followed by a number.

The reserved system registers are registers that are used for system purposes. These reserved system registers may not be vectorized as the general purpose registers are. Reserved system registers may not have a width of 32 bits. They are shown here being prefixed with r and followed by a number.

Register Alias Purpose

g0-g111

General Purpose

r0

z

Always Zero

r1

pc

Program Counter

r2

vd

Vector Depth

r3

v

Vector

r4

vm

Vector Mask

r5

vi

Vector Index

r6-r15

Reserved

Reserved Registers

z Register

Hard-wired to zero. Writing to the register is a 1 cycle no-op.

pc Register

A read-only register that stores the memory address of the current instruction. Writing to the register is a 1 cycle no-op.

vd Register

A read-only register that contains the implementation’s maximum vector depth. This is implementation defined, but must be a power of 2. On implementations that do not have a vector depth, this register must be set to 1. Writing to the register is a 1 cycle no-op.

v Register

When set to a value other than 0x0, instructions will be treated as vector instructions. When set, it determines the vector depth of the instruction. Must be set to a value less than or equal to the value of the vd register.

vm Register

Has as many bits as the vector depth. Determines which vector indicies will be skipped. If the bit corresponding to the vector index is set, the vector index will be skipped.

vi Register

A register that contains the current index of the vector instruction. Writing to the register before a vector instruction will set the starting index of the vector instruction. This register should be incremented by the implementation after each vector loop. This register will be reset to 0 after each vector instruction.

Instruction Encoding

The base skyror32 ISA contains four instruction encoding formats: C, S, F, and D each with a different number of destination and source registers.

The C format contains 2 source registers and a single destination register. The S format contains a single source register and 2 destination registers. The F format contains a single source register and a single destination register as well as a function. The D format contains a single 32 bit immediate.

The least significant bit of the C, S, and F instruction encoding formats are used to signal for a data trailer.

The C, S, and F instruction formats use a 8 bit opcode in the most significant bits. Each register is encoded as a 7 bit value in the least significant bits after the trailer bit.

The actual bit encoding of each format is listed below.

C Format

Bits

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

OPCODE

REGs2

REGs1

REGd1

T

S Format

Bits

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

1

OPCODE

REGs1

REGd2

REGd1

T

F Format

Bits

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

OPCODE

FUNC

REGs1

REGd

T

D Format

Bits

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

IMM

Fields

Field Description

OPCODE

Operation code

FUNC

Function

REGs1

Source register 1 id, 7 bits wide.

REGs2

Source register 2 id, 7 bits wide.

REGd1

Destination register 1 id, 7 bits wide.

REGd2

Destination register 2 id, 7 bits wide.

T

Signals if there is immediate data trailing.

IMM

Immediate data, 32 bits wide.

Instructions

Load and Store