From a019fd4ed4f96344b5a9ac704991b53840797b43 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Fin=20Maa=C3=9F?= <f.maass@vogl-electronic.com>
Date: Wed, 22 Jan 2025 11:13:04 +0100
Subject: [PATCH] build: common: make sure Signal lenght is right
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make sure the the lenght of the o2 Signal is
the same lenght of o1, when a DDRImput implementation is used
for a SDRInput. This is needed for multibit io.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
---
 litex/build/altera/common.py  | 4 ++--
 litex/build/lattice/common.py | 2 +-
 litex/build/xilinx/common.py  | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py
index a39de37e9d..7b41b078f1 100644
--- a/litex/build/altera/common.py
+++ b/litex/build/altera/common.py
@@ -135,7 +135,7 @@ def lower(dr):
 class AlteraSDRInput:
     @staticmethod
     def lower(dr):
-        return AlteraDDRInputImpl(dr.i, dr.o, Signal(), dr.clk)
+        return AlteraDDRInputImpl(dr.i, dr.o, Signal(len(dr.o)), dr.clk)
 
 # Special Overrides --------------------------------------------------------------------------------
 
@@ -225,7 +225,7 @@ def lower(dr):
 class Agilex5SDRInput:
     @staticmethod
     def lower(dr):
-        return Agilex5DDRInputImpl(dr.i, dr.o, Signal(), dr.clk)
+        return Agilex5DDRInputImpl(dr.i, dr.o, Signal(len(dr.o)), dr.clk)
 
 # Agilex5 SDRTristate ------------------------------------------------------------------------------
 
diff --git a/litex/build/lattice/common.py b/litex/build/lattice/common.py
index 8ce05598cc..4e98b80e2b 100644
--- a/litex/build/lattice/common.py
+++ b/litex/build/lattice/common.py
@@ -528,7 +528,7 @@ def lower(dr):
 class LatticeiCE40SDRInput:
     @staticmethod
     def lower(dr):
-        return LatticeiCE40DDRInputImpl(dr.i, dr.o, Signal(), dr.clk)
+        return LatticeiCE40DDRInputImpl(dr.i, dr.o, Signal(len(dr.o)), dr.clk)
 
 # iCE40 SDR Tristate -------------------------------------------------------------------------------
 
diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
index 73ccd510dc..15c286f087 100644
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@@ -255,7 +255,7 @@ def lower(dr):
 class XilinxSDRInputS6:
     @staticmethod
     def lower(dr):
-        return XilinxDDRInputImplS6(dr.i, dr.o, Signal(), dr.clk)
+        return XilinxDDRInputImplS6(dr.i, dr.o, Signal(len(dr.o)), dr.clk)
 
 # Spartan6 Special Overrides -----------------------------------------------------------------------
 
@@ -323,7 +323,7 @@ def lower(dr):
 class XilinxSDRInputS7:
     @staticmethod
     def lower(dr):
-        return XilinxDDRInputImplS7(dr.i, dr.o, Signal(), dr.clk)
+        return XilinxDDRInputImplS7(dr.i, dr.o, Signal(len(dr.o)), dr.clk)
 
 # 7-Series Special Overrides -----------------------------------------------------------------------