From 0cfda82d043a039d0bd85549a693c7df3c4129d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Mon, 15 Apr 2024 14:43:53 +0200 Subject: [PATCH 001/138] Split up some paths --- webgui/src/img/riscv_five_stage_pipeline.svg | 556 ++++++++----------- 1 file changed, 237 insertions(+), 319 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 56ead14..729d74d 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,17 +25,17 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.25" - inkscape:cx="2702" - inkscape:cy="2188" + inkscape:zoom="0.1767767" + inkscape:cx="2514.4717" + inkscape:cy="2251.428" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" inkscape:window-y="0" inkscape:window-maximized="1" - inkscape:current-layer="layer6" showguides="true" - inkscape:lockguides="false"> + style="overflow:visible" + id="000000_ArchsimMarker_Triangle_Reversed" + refX="0" + refY="0" + orient="auto-start-reverse" + inkscape:stockid="TriangleStart" + markerWidth="5.3244081" + markerHeight="6.155385" + viewBox="0 0 5.3244081 6.1553851" + inkscape:isstock="true" + inkscape:collect="always" + preserveAspectRatio="xMidYMid"> 0Result Date: Tue, 16 Apr 2024 09:17:00 +0200 Subject: [PATCH 002/138] Merged a path; Made all dots actual circles --- webgui/src/img/riscv_five_stage_pipeline.svg | 126 ++++++++----------- 1 file changed, 53 insertions(+), 73 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 729d74d..5943ece 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.1767767" - inkscape:cx="2514.4717" - inkscape:cy="2251.428" + inkscape:zoom="0.25000001" + inkscape:cx="2137.9999" + inkscape:cy="3303.9999" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -128,13 +128,12 @@ style="display:inline;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:5.0037;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#000000_ArchsimMarker_Triangle)" d="m 942.56233,852.57292 -47.5301,1.5e-4" sodipodi:nodetypes="cc" /> Date: Tue, 16 Apr 2024 09:31:26 +0200 Subject: [PATCH 003/138] updated the stroke with for all signals --- webgui/src/img/riscv_five_stage_pipeline.svg | 106 +++++++++---------- 1 file changed, 53 insertions(+), 53 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 5943ece..548eebb 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -26,8 +26,8 @@ inkscape:document-units="mm" showgrid="false" inkscape:zoom="0.25000001" - inkscape:cx="2137.9999" - inkscape:cy="3303.9999" + inkscape:cx="3801.9999" + inkscape:cy="2699.9999" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -35,7 +35,7 @@ inkscape:window-maximized="1" showguides="true" inkscape:lockguides="false" - inkscape:current-layer="layer6">0 Date: Tue, 16 Apr 2024 09:33:46 +0200 Subject: [PATCH 004/138] updated box stroke widths --- webgui/src/img/riscv_five_stage_pipeline.svg | 40 ++++++++++---------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 548eebb..0578daa 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.25000001" - inkscape:cx="3801.9999" - inkscape:cy="2699.9999" + inkscape:zoom="0.1767767" + inkscape:cx="3340.3723" + inkscape:cy="1810.1933" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -35,7 +35,7 @@ inkscape:window-maximized="1" showguides="true" inkscape:lockguides="false" - inkscape:current-layer="ControlUnitLeftRight2-4">0Instr[31-0]PCRead Addr 1UnitImm GenAddAdd Date: Tue, 16 Apr 2024 10:50:13 +0200 Subject: [PATCH 005/138] Realigned and merged all (?) path segments that form one path --- webgui/src/img/riscv_five_stage_pipeline.svg | 236 ++++++------------- 1 file changed, 71 insertions(+), 165 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 0578daa..7155806 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.1767767" - inkscape:cx="3340.3723" - inkscape:cy="1810.1933" + inkscape:zoom="0.25" + inkscape:cx="5412" + inkscape:cy="2676" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -154,7 +154,7 @@ r="6" />0 Date: Tue, 16 Apr 2024 11:21:39 +0200 Subject: [PATCH 006/138] Changed marker dimensions --- webgui/src/img/riscv_five_stage_pipeline.svg | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 7155806..81fe7a1 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -26,8 +26,8 @@ inkscape:document-units="mm" showgrid="false" inkscape:zoom="0.25" - inkscape:cx="5412" - inkscape:cy="2676" + inkscape:cx="4656" + inkscape:cy="2592" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -51,8 +51,8 @@ refY="0" orient="auto-start-reverse" inkscape:stockid="TriangleStart" - markerWidth="5.3244081" - markerHeight="6.155385" + markerWidth="1.73" + markerHeight="2" viewBox="0 0 5.3244081 6.1553851" inkscape:isstock="true" inkscape:collect="always" @@ -67,8 +67,8 @@ refY="0" orient="auto" inkscape:stockid="TriangleStart" - markerWidth="5.3244081" - markerHeight="6.155385" + markerWidth="1.73" + markerHeight="2" viewBox="0 0 5.3244081 6.1553851" inkscape:isstock="true" inkscape:collect="always" From b5a7d027e4ad0d727a54bcd7a77c8cf8022a2900 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Tue, 16 Apr 2024 11:35:01 +0200 Subject: [PATCH 007/138] Path start and end can now take same marker --- webgui/src/img/riscv_five_stage_pipeline.svg | 74 ++++++++------------ 1 file changed, 28 insertions(+), 46 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 81fe7a1..e187255 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -60,25 +60,7 @@ transform="scale(0.5)" style="fill:#000000;fill-rule:evenodd;stroke:#000000;stroke-width:1pt" d="M 5.77,0 -2.88,5 V -5 Z" - id="000000_ArchsimMarker_Triangle_Reversed_Path" /> + id="000000_ArchsimMarker_Triangle_Reversed_Path" /> Date: Tue, 16 Apr 2024 11:36:50 +0200 Subject: [PATCH 008/138] Fix marker dimensions --- webgui/src/img/riscv_five_stage_pipeline.svg | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index e187255..b6e3306 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.25" - inkscape:cx="4656" - inkscape:cy="2592" + inkscape:zoom="2" + inkscape:cx="6494.5" + inkscape:cy="3299.5" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -51,12 +51,12 @@ refY="0" orient="auto-start-reverse" inkscape:stockid="TriangleStart" - markerWidth="1.73" + markerWidth="2" markerHeight="2" viewBox="0 0 5.3244081 6.1553851" inkscape:isstock="true" inkscape:collect="always" - preserveAspectRatio="xMidYMid"> Date: Tue, 16 Apr 2024 12:15:31 +0200 Subject: [PATCH 009/138] Aligned the markers with their boxes --- webgui/src/img/riscv_five_stage_pipeline.svg | 236 ++++++++----------- 1 file changed, 96 insertions(+), 140 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index b6e3306..c16f0f9 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="2" - inkscape:cx="6494.5" - inkscape:cy="3299.5" + inkscape:zoom="0.25" + inkscape:cx="3058" + inkscape:cy="2348" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -35,7 +35,7 @@ inkscape:window-maximized="1" showguides="true" inkscape:lockguides="false" - inkscape:current-layer="layer6"> Date: Tue, 16 Apr 2024 12:32:06 +0200 Subject: [PATCH 010/138] Merged some more paths --- webgui/src/img/riscv_five_stage_pipeline.svg | 79 ++++++++------------ 1 file changed, 32 insertions(+), 47 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index c16f0f9..a6b5ae9 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.25" - inkscape:cx="3058" - inkscape:cy="2348" + inkscape:zoom="1.4142136" + inkscape:cx="4923.2309" + inkscape:cy="2766.9088" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -35,7 +35,7 @@ inkscape:window-maximized="1" showguides="true" inkscape:lockguides="false" - inkscape:current-layer="DecodeInstructionMemory"> Date: Tue, 16 Apr 2024 16:02:48 +0200 Subject: [PATCH 011/138] Fix read data 1 signal --- webgui/src/img/riscv_five_stage_pipeline.svg | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index a6b5ae9..3641d0b 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="1.4142136" - inkscape:cx="4923.2309" - inkscape:cy="2766.9088" + inkscape:zoom="0.7071068" + inkscape:cx="3789.3851" + inkscape:cy="3027.8312" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -213,7 +213,7 @@ inkscape:label="ExecuteRightMuxOut" /> Date: Tue, 16 Apr 2024 16:50:55 +0200 Subject: [PATCH 012/138] Added the new control signals --- webgui/src/img/riscv_five_stage_pipeline.svg | 95 ++++++++++++++------ 1 file changed, 69 insertions(+), 26 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 3641d0b..f6ac56a 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,15 +25,15 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.7071068" - inkscape:cx="3789.3851" - inkscape:cy="3027.8312" + inkscape:zoom="0.50000001" + inkscape:cx="5326.9999" + inkscape:cy="2501.9999" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" inkscape:window-y="0" inkscape:window-maximized="1" - showguides="true" + showguides="false" inkscape:lockguides="false" inkscape:current-layer="layer6"> Date: Tue, 16 Apr 2024 17:08:59 +0200 Subject: [PATCH 013/138] Added changed markers to svg build script --- build_svg.py | 152 ++++++------------- webgui/src/img/riscv_five_stage_pipeline.svg | 116 +++++++++----- 2 files changed, 125 insertions(+), 143 deletions(-) diff --git a/build_svg.py b/build_svg.py index fa18823..10d7e92 100644 --- a/build_svg.py +++ b/build_svg.py @@ -2,108 +2,56 @@ riscv_five_stage_markers = """ + style="overflow:visible" + id="000000_ArchsimMarker_Triangle" + refX="0" + refY="0" + orient="auto-start-reverse" + inkscape:stockid="TriangleStart" + markerWidth="2" + markerHeight="2" + viewBox="0 0 5.3244081 6.1553851" + inkscape:isstock="true" + inkscape:collect="always" + preserveAspectRatio="none"> + + """ riscv_single_stage_markers = """ diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index f6ac56a..648a43b 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -46,7 +46,7 @@ + id="000000_ArchsimMarker_Triangle_Path" /> + + Date: Tue, 16 Apr 2024 17:32:06 +0200 Subject: [PATCH 014/138] Changed signals in the backend which were removed from the SVG --- .../gui/riscv_fiveStage_svg_directives.py | 4 +--- .../simulation/riscv_simulation.py | 8 +------- webgui/src/img/riscv_five_stage_pipeline.svg | 19 ++++++++++--------- 3 files changed, 12 insertions(+), 19 deletions(-) diff --git a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py index b15999b..86e29a7 100644 --- a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py +++ b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py @@ -147,9 +147,7 @@ def __init__(self): self.FetchRightMuxOutText = SvgWriteCenterDirective() self.FetchLeftMuxOutText = SvgWriteCenterDirective() self.FetchRightMuxOut = SvgFillDirectiveBlue() - self.path2453_0_7_7_9 = SvgFillDirectiveBlue() - self.path2453_2_5_7_0_7_5_1_0_4 = SvgFillDirectiveBlue() - self.path2453_2_5_7_0_7_6_2_29 = SvgFillDirectiveBlue() + self.FetchPCIn = SvgFillDirectiveBlue() class SvgFillDirectiveBlue(SvgFillDirective): diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index 76c7914..cb2cd8b 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -618,13 +618,7 @@ def _get_riscv_five_stage_OTHER_svg_update_values( result.FetchRightMuxOut.do_highlight = bool(result.FetchRightMuxOutText.text) - result.path2453_0_7_7_9.do_highlight = bool(result.FetchLeftMuxOutText.text) - result.path2453_2_5_7_0_7_5_1_0_4.do_highlight = bool( - result.FetchLeftMuxOutText.text - ) - result.path2453_2_5_7_0_7_6_2_29.do_highlight = bool( - result.FetchLeftMuxOutText.text - ) + result.FetchPCIn.do_highlight = bool(result.FetchLeftMuxOutText.text) return result.export() diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 648a43b..94398c4 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.50000001" - inkscape:cx="5326.9999" - inkscape:cy="2501.9999" + inkscape:zoom="0.7071068" + inkscape:cx="3288.7536" + inkscape:cy="3623.2151" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -158,7 +158,7 @@ d="m 1228.3375,996.87328 -210.1437,-3e-5 H 895.03223 v -48.21387" sodipodi:nodetypes="cccc" /> Date: Wed, 17 Apr 2024 07:45:07 +0200 Subject: [PATCH 015/138] Changed to markers for the dots --- build_svg.py | 36 +++ webgui/src/img/riscv_five_stage_pipeline.svg | 223 ++++++------------- 2 files changed, 106 insertions(+), 153 deletions(-) diff --git a/build_svg.py b/build_svg.py index 10d7e92..5f5eb46 100644 --- a/build_svg.py +++ b/build_svg.py @@ -52,6 +52,42 @@ style="fill:#0000FF;fill-rule:evenodd;stroke:#0000FF;stroke-width:1pt" d="M 5.77,0 -2.88,5 V -5 Z" id="0000FF_ArchsimMarker_Triangle_Path" /> + + """ riscv_single_stage_markers = """ diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 94398c4..4ec9a72 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -26,8 +26,8 @@ inkscape:document-units="mm" showgrid="false" inkscape:zoom="0.7071068" - inkscape:cx="3288.7536" - inkscape:cy="3623.2151" + inkscape:cx="1683.6212" + inkscape:cy="992.77789" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -63,38 +63,22 @@ id="000000_ArchsimMarker_Triangle_Path" /> - + style="fill:#000000;fill-rule:evenodd;stroke:none" + d="M 5,0 C 5,2.76 2.76,5 0,5 -2.76,5 -5,2.76 -5,0 c 0,-2.76 2.3,-5 5,-5 2.76,0 5,2.24 5,5 z" + id="Dot1" + sodipodi:nodetypes="sssss" /> Date: Wed, 17 Apr 2024 07:47:34 +0200 Subject: [PATCH 016/138] Fix dot markers --- webgui/src/img/riscv_five_stage_pipeline.svg | 78 ++++++++++++++++---- 1 file changed, 65 insertions(+), 13 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 4ec9a72..f3b33d4 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -61,6 +61,40 @@ style="fill:#000000;fill-rule:evenodd;stroke:#000000;stroke-width:1pt" d="M 5.77,0 -2.88,5 V -5 Z" id="000000_ArchsimMarker_Triangle_Path" /> + + + Date: Wed, 17 Apr 2024 07:51:49 +0200 Subject: [PATCH 017/138] Add missing id to svg --- webgui/src/img/riscv_five_stage_pipeline.svg | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index f3b33d4..0f0599c 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.7071068" - inkscape:cx="1683.6212" - inkscape:cy="992.77789" + inkscape:zoom="0.50000001" + inkscape:cx="2023.9999" + inkscape:cy="2647.9999" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -2492,7 +2492,7 @@ d="M 651.31823,696.53138 H 554.61824" inkscape:label="DecodeInstructionMemory1" sodipodi:nodetypes="cc" - id="path82875" /> Date: Wed, 17 Apr 2024 08:28:50 +0200 Subject: [PATCH 018/138] Added new SvgDirectives; added missing ids to svg --- .../gui/riscv_fiveStage_svg_directives.py | 21 +++++++++++++++++++ webgui/src/img/riscv_five_stage_pipeline.svg | 10 ++++----- 2 files changed, 26 insertions(+), 5 deletions(-) diff --git a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py index 86e29a7..44f0b72 100644 --- a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py +++ b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py @@ -32,6 +32,10 @@ def __init__(self): self.FetchAddOut = SvgFillDirectiveBlue() self.I_LengthText = SvgWriteCenterDirective() self.FetchI_Length = SvgFillDirectiveBlue() + self.PCFetchOutToExAdder = SvgFillDirectiveBlue() + self.PCFetchOutToExMux = SvgFillDirectiveBlue() + self.FetchAddOutToPReg = SvgFillDirectiveBlue() + self.FetchAddOutToMux = SvgFillDirectiveBlue() class RiscvFiveStageIDSvgDirectives(RiscvSvgDirectivesBase): @@ -62,6 +66,10 @@ def __init__(self): self.ControlUnitLeftRight3_1 = SvgFillDirectiveGreen() self.ControlUnitLeftRight4_1 = SvgFillDirectiveGreen() self.ControlUnitLeft_1 = SvgFillDirectiveGreen() + self.DecodeInstructionMemoryIntermediate = SvgFillDirectiveBlue() + self.ControlUnitRegWriteEnable_1 = SvgFillDirectiveGreen() + self.ControlUnitMemWriteEnable_1 = SvgFillDirectiveGreen() + self.ControlUnitMemReadEnable_1 = SvgFillDirectiveGreen() class RiscvFiveStageEXSvgDirectives(RiscvSvgDirectivesBase): @@ -95,6 +103,13 @@ def __init__(self): self.ControlUnitLeftRight4_2 = SvgFillDirectiveGreen() self.ControlUnitLeft_2 = SvgFillDirectiveGreen() self.AluControl = SvgFillDirectiveBlue() + self.ExecuteImmediateToAdder = SvgFillDirectiveBlue() + self.ExecuteImmediateToMux = SvgFillDirectiveBlue() + self.ExecuteImmediateInterediate = SvgFillDirectiveBlue() + self.ExecuteRegisterFileReadData2ToMux = SvgFillDirectiveBlue() + self.ControlUnitRegWriteEnable_2 = SvgFillDirectiveGreen() + self.ControlUnitMemWriteEnable_2 = SvgFillDirectiveGreen() + self.ControlUnitMemReadEnable_2 = SvgFillDirectiveGreen() class RiscvFiveStageMEMSvgDirectives(RiscvSvgDirectivesBase): @@ -121,6 +136,11 @@ def __init__(self): self.ControlUnitLeftRight1_3 = SvgFillDirectiveGreen() self.ControlUnitLeftRight2_3 = SvgFillDirectiveBlue() self.ControlUnitLeft_3 = SvgFillDirectiveGreen() + self.MemoryExecuteAluResultToMemory = SvgFillDirectiveBlue() + self.MemoryExecuteAluResultToFetchMux = SvgFillDirectiveBlue() + self.ControlUnitRegWriteEnable_3 = SvgFillDirectiveGreen() + self.ControlUnitMemWriteEnable_3 = SvgFillDirectiveGreen() + self.ControlUnitMemReadEnable_3 = SvgFillDirectiveGreen() class RiscvFiveStageWBSvgDirectives(RiscvSvgDirectivesBase): @@ -140,6 +160,7 @@ def __init__(self): self.WriteBackImmGen = SvgFillDirectiveBlue() self.wbsrc = SvgWriteCenterDirective() self.ControlUnitLeftRight2_4 = SvgFillDirectiveBlue() + self.ControlUnitRegWriteEnable_4 = SvgFillDirectiveGreen() class RiscvFiveStageOTHERSvgDirectives(RiscvSvgDirectivesBase): diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 0f0599c..ebebfbe 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.50000001" - inkscape:cx="2023.9999" - inkscape:cy="2647.9999" + inkscape:zoom="0.3535534" + inkscape:cx="3396.9409" + inkscape:cy="2525.7854" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -2493,7 +2493,7 @@ inkscape:label="DecodeInstructionMemory1" sodipodi:nodetypes="cc" id="DecodeInstructionMemory1" /> Date: Wed, 17 Apr 2024 09:17:22 +0200 Subject: [PATCH 019/138] Added logic for IF SVG directives --- .../simulation/riscv_simulation.py | 11 ++++++++++ .../uarch/riscv/pipeline_registers.py | 1 + architecture_simulator/uarch/riscv/stages.py | 22 +++++++++++-------- 3 files changed, 25 insertions(+), 9 deletions(-) diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index cb2cd8b..f4c6acd 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -272,10 +272,21 @@ def _get_riscv_five_stage_IF_svg_update_values(self) -> list[tuple[str, str, Any result.FetchAddOutText.text = save_to_str( pipeline_register.pc_plus_instruction_length ) + result.FetchAddOutToMux.do_highlight = bool(result.FetchAddOutText.text) result.FetchAddOut.do_highlight = bool(result.FetchAddOutText.text) result.I_LengthText.text = save_to_str(pipeline_register.instruction.length) result.FetchI_Length.do_highlight = bool(result.I_LengthText.text) + result.PCFetchOutToExAdder.do_highlight = bool( + pipeline_register.control_unit_signals.jump + ) | bool(pipeline_register.control_unit_signals.branch) + result.PCFetchOutToExMux.do_highlight = ( + pipeline_register.control_unit_signals.alu_src_1 is not None + and not bool(pipeline_register.control_unit_signals.alu_src_1) + ) + result.FetchAddOutToPReg.do_highlight = ( + pipeline_register.control_unit_signals.wb_src == 0 + ) return result.export() diff --git a/architecture_simulator/uarch/riscv/pipeline_registers.py b/architecture_simulator/uarch/riscv/pipeline_registers.py index 71dd00e..e8aa62b 100644 --- a/architecture_simulator/uarch/riscv/pipeline_registers.py +++ b/architecture_simulator/uarch/riscv/pipeline_registers.py @@ -28,6 +28,7 @@ class PipelineRegister: @dataclass class InstructionFetchPipelineRegister(PipelineRegister): + control_unit_signals: ControlUnitSignals = field(default_factory=ControlUnitSignals) branch_prediction: Optional[bool] = None pc_plus_instruction_length: Optional[int] = None abbreviation = "IF" diff --git a/architecture_simulator/uarch/riscv/stages.py b/architecture_simulator/uarch/riscv/stages.py index 2d724f6..afca488 100644 --- a/architecture_simulator/uarch/riscv/stages.py +++ b/architecture_simulator/uarch/riscv/stages.py @@ -98,12 +98,14 @@ def behavior( instruction = state.instruction_memory.read_instruction(address_of_instruction) state.program_counter += instruction.length pc_plus_instruction_length = address_of_instruction + instruction.length + control_unit_signals = instruction.control_unit_signals() return InstructionFetchPipelineRegister( instruction=instruction, address_of_instruction=address_of_instruction, branch_prediction=False, pc_plus_instruction_length=pc_plus_instruction_length, + control_unit_signals=control_unit_signals, ) @@ -171,8 +173,6 @@ def behavior( stall_signal = StallSignal(2) break - # gets the control unit signals that are generated in the ID stage - control_unit_signals = pipeline_register.instruction.control_unit_signals() return InstructionDecodePipelineRegister( instruction=pipeline_register.instruction, register_read_addr_1=register_read_addr_1, @@ -181,7 +181,7 @@ def behavior( register_read_data_2=register_read_data_2, imm=imm, write_register=write_register, - control_unit_signals=control_unit_signals, + control_unit_signals=pipeline_register.control_unit_signals, branch_prediction=pipeline_register.branch_prediction, stall_signal=stall_signal, pc_plus_instruction_length=pipeline_register.pc_plus_instruction_length, @@ -504,12 +504,16 @@ def behavior( result_pr.pc_plus_imm = state.program_counter + result_pr.imm a_comparison, a_result = result_pr.instruction.alu_compute( - state.program_counter - if result_pr.control_unit_signals.alu_src_1 - else result_pr.register_read_data_1, - result_pr.imm - if result_pr.control_unit_signals.alu_src_2 - else result_pr.register_read_data_2, + ( + state.program_counter + if result_pr.control_unit_signals.alu_src_1 + else result_pr.register_read_data_1 + ), + ( + result_pr.imm + if result_pr.control_unit_signals.alu_src_2 + else result_pr.register_read_data_2 + ), ) result_pr.alu_comparison = bool(a_comparison) From d6f8c3a2dcc5f8a1961befe191e7a532d4d4d6d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Wed, 17 Apr 2024 09:42:01 +0200 Subject: [PATCH 020/138] Added logic for ID svg directives --- .../simulation/riscv_simulation.py | 52 +++++++++++++------ 1 file changed, 37 insertions(+), 15 deletions(-) diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index f4c6acd..34623dd 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -5,6 +5,7 @@ from architecture_simulator.uarch.riscv.riscv_architectural_state import ( RiscvArchitecturalState, ) +from architecture_simulator.isa.riscv.instruction_types import EmptyInstruction from architecture_simulator.isa.riscv.riscv_parser import RiscvParser from .simulation import Simulation from architecture_simulator.uarch.riscv.pipeline_registers import ( @@ -337,28 +338,35 @@ def _get_riscv_five_stage_ID_svg_update_values(self) -> list[tuple[str, str, Any result.DecodeInstructionMemory4Text.text ) - result.DecodeFetchAddOutText.text = save_to_str( - pipeline_register.pc_plus_instruction_length + result.DecodeFetchAddOut.do_highlight = ( + pipeline_register.control_unit_signals.wb_src == 0 ) - result.DecodeFetchAddOut.do_highlight = bool( - result.DecodeFetchAddOutText.text + result.DecodeFetchAddOutText.text = ( + save_to_str(pipeline_register.pc_plus_instruction_length) + if result.DecodeFetchAddOut.do_highlight + else "" ) - result.DecodeUpperFetchPCOutText.text = save_to_str( - pipeline_register.address_of_instruction - ) - result.DecodeLowerFetchPCOutText.text = save_to_str( - pipeline_register.address_of_instruction + result.DecodeUpperFetchPCOut.do_highlight = bool( + pipeline_register.control_unit_signals.jump + ) | bool(pipeline_register.control_unit_signals.branch) + result.DecodeUpperFetchPCOutText.text = ( + save_to_str(pipeline_register.address_of_instruction) + if result.DecodeUpperFetchPCOut.do_highlight + else "" ) - result.DecodeUpperFetchPCOut.do_highlight = bool( - result.DecodeLowerFetchPCOutText.text + result.DecodeLowerFetchPCOut.do_highlight = ( + pipeline_register.control_unit_signals.alu_src_1 == 0 ) - result.DecodeLowerFetchPCOut.do_highlight = bool( - result.DecodeLowerFetchPCOutText.text + result.DecodeLowerFetchPCOutText.text = ( + save_to_str(pipeline_register.address_of_instruction) + if result.DecodeLowerFetchPCOut.do_highlight + else "" ) - result.DecodeInstructionMemory.do_highlight = bool( - result.DecodeLowerFetchPCOutText.text + + result.DecodeInstructionMemory.do_highlight = not isinstance( + pipeline_register.instruction, EmptyInstruction ) result.ControlUnitLeftRight1_1.do_highlight = bool( pipeline_register.control_unit_signals.jump @@ -375,6 +383,20 @@ def _get_riscv_five_stage_ID_svg_update_values(self) -> list[tuple[str, str, Any result.ControlUnitLeft_1.do_highlight = bool( pipeline_register.control_unit_signals.alu_to_pc ) + result.ControlUnitRegWriteEnable_1.do_highlight = bool( + pipeline_register.control_unit_signals.reg_write + ) + result.ControlUnitMemWriteEnable_1.do_highlight = bool( + pipeline_register.control_unit_signals.mem_write + ) + result.ControlUnitMemReadEnable_1.do_highlight = bool( + pipeline_register.control_unit_signals.mem_read + ) + + result.DecodeInstructionMemoryIntermediate.do_highlight = bool( + pipeline_register.control_unit_signals.reg_write + ) | (pipeline_register.imm is not None) + return result.export() def _get_riscv_five_stage_EX_svg_update_values(self) -> list[tuple[str, str, Any]]: From 43f00a2aeb43112593194e9155bde3835d3c7e88 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Wed, 17 Apr 2024 10:17:16 +0200 Subject: [PATCH 021/138] Added logic for the EX SVG Directives --- .../gui/riscv_fiveStage_svg_directives.py | 2 + .../simulation/riscv_simulation.py | 81 +++++++++++++++---- webgui/src/img/riscv_five_stage_pipeline.svg | 6 +- 3 files changed, 69 insertions(+), 20 deletions(-) diff --git a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py index 44f0b72..f4adb83 100644 --- a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py +++ b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py @@ -107,9 +107,11 @@ def __init__(self): self.ExecuteImmediateToMux = SvgFillDirectiveBlue() self.ExecuteImmediateInterediate = SvgFillDirectiveBlue() self.ExecuteRegisterFileReadData2ToMux = SvgFillDirectiveBlue() + self.ExecuteRegisterFileReadData2ToMemory = SvgFillDirectiveBlue() self.ControlUnitRegWriteEnable_2 = SvgFillDirectiveGreen() self.ControlUnitMemWriteEnable_2 = SvgFillDirectiveGreen() self.ControlUnitMemReadEnable_2 = SvgFillDirectiveGreen() + self.ExecuteImmediateToWbMux = SvgFillDirectiveBlue() class RiscvFiveStageMEMSvgDirectives(RiscvSvgDirectivesBase): diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index 34623dd..29210d8 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -428,9 +428,7 @@ def _get_riscv_five_stage_EX_svg_update_values(self) -> list[tuple[str, str, Any result.ExecuteRegisterFileReadData2Text2.text ) - result.ExecuteImmGenText1.text = save_to_str(pipeline_register.imm) - result.ExecuteImmGenText3.text = save_to_str(pipeline_register.imm) - result.ExecuteImmGen.do_highlight = bool(result.ExecuteImmGenText3.text) + result.ExecuteImmGen.do_highlight = pipeline_register.imm is not None result.ALUResultText.text = save_to_str(pipeline_register.result) result.ExecuteAluResult.do_highlight = bool(result.ALUResultText.text) @@ -445,21 +443,13 @@ def _get_riscv_five_stage_EX_svg_update_values(self) -> list[tuple[str, str, Any result.ExecuteAddText.text = save_to_str(pipeline_register.pc_plus_imm) result.ExecuteAdd.do_highlight = bool(result.ExecuteAddText.text) - result.ExecuteFetchAddOutText.text = save_to_str( - pipeline_register.pc_plus_instruction_length - ) - result.ExecuteFetchAddOut.do_highlight = bool( - result.ExecuteFetchAddOutText.text - ) - - result.ExecuteUpperFetchPCOutText.text = save_to_str( - pipeline_register.address_of_instruction - ) - result.ExecuteUpperFetchPCOut.do_highlight = bool( - result.ExecuteUpperFetchPCOutText.text + result.ExecuteFetchAddOut.do_highlight = ( + pipeline_register.control_unit_signals.wb_src == 0 ) - result.ExecuteLowerFetchPCOut.do_highlight = bool( - result.ExecuteUpperFetchPCOutText.text + result.ExecuteFetchAddOutText.text = ( + save_to_str(pipeline_register.pc_plus_instruction_length) + if result.ExecuteFetchAddOut.do_highlight + else "" ) result.ALUComparison.do_highlight = bool(pipeline_register.comparison) @@ -484,6 +474,63 @@ def _get_riscv_five_stage_EX_svg_update_values(self) -> list[tuple[str, str, Any save_to_str(pipeline_register.control_unit_signals.alu_op) ) + result.ExecuteImmediateToAdder.do_highlight = bool( + pipeline_register.control_unit_signals.jump + ) | bool(pipeline_register.control_unit_signals.branch) + result.ExecuteImmGenText1.text = ( + save_to_str(pipeline_register.imm) + if result.ExecuteImmediateToAdder.do_highlight + else "" + ) + + result.ExecuteUpperFetchPCOut.do_highlight = ( + result.ExecuteImmediateToAdder.do_highlight + ) + result.ExecuteUpperFetchPCOutText.text = ( + save_to_str(pipeline_register.address_of_instruction) + if result.ExecuteUpperFetchPCOut.do_highlight + else "" + ) + + result.ExecuteLowerFetchPCOut.do_highlight = ( + pipeline_register.control_unit_signals.alu_src_1 is False + ) + + result.ExecuteImmediateToMux.do_highlight = ( + pipeline_register.control_unit_signals.alu_src_2 + ) + + result.ExecuteImmediateToWbMux.do_highlight = ( + pipeline_register.control_unit_signals.wb_src == 3 + ) + result.ExecuteImmGenText3.text = ( + save_to_str(pipeline_register.imm) + if result.ExecuteImmediateToWbMux.do_highlight + else "" + ) + + result.ExecuteImmediateInterediate.do_highlight = ( + bool(pipeline_register.control_unit_signals.alu_src_2) + or result.ExecuteImmediateToAdder.do_highlight + ) + + result.ExecuteRegisterFileReadData2ToMux.do_highlight = ( + pipeline_register.control_unit_signals.alu_src_2 is False + ) + result.ExecuteRegisterFileReadData2ToMemory.do_highlight = bool( + pipeline_register.control_unit_signals.mem_write + ) + + result.ControlUnitRegWriteEnable_2.do_highlight = bool( + pipeline_register.control_unit_signals.reg_write + ) + result.ControlUnitMemWriteEnable_2.do_highlight = bool( + pipeline_register.control_unit_signals.mem_write + ) + result.ControlUnitMemReadEnable_2.do_highlight = bool( + pipeline_register.control_unit_signals.mem_read + ) + return result.export() def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, Any]]: diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index ebebfbe..6468cb2 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -26,8 +26,8 @@ inkscape:document-units="mm" showgrid="false" inkscape:zoom="0.3535534" - inkscape:cx="3396.9409" - inkscape:cy="2525.7854" + inkscape:cx="4075.7634" + inkscape:cy="2978.3337" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -183,7 +183,7 @@ style="fill:none;stroke:#000000;stroke-width:4.99999;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#000000_ArchsimMarker_Dot)" d="M 895.03343,948.65936 V 852.57307" id="ExecuteImmediateInterediate" /> Date: Thu, 18 Apr 2024 15:25:02 +0200 Subject: [PATCH 022/138] Added the logic for the MEM SVG Directives --- .../gui/riscv_fiveStage_svg_directives.py | 2 + .../simulation/riscv_simulation.py | 84 +++++++++++++------ 2 files changed, 62 insertions(+), 24 deletions(-) diff --git a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py index f4adb83..138aa91 100644 --- a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py +++ b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py @@ -140,6 +140,8 @@ def __init__(self): self.ControlUnitLeft_3 = SvgFillDirectiveGreen() self.MemoryExecuteAluResultToMemory = SvgFillDirectiveBlue() self.MemoryExecuteAluResultToFetchMux = SvgFillDirectiveBlue() + self.MemoryExecuteAluResultIntermediate = SvgFillDirectiveBlue() + self.MemoryExecuteAluResultToWbMux = SvgFillDirectiveBlue() self.ControlUnitRegWriteEnable_3 = SvgFillDirectiveGreen() self.ControlUnitMemWriteEnable_3 = SvgFillDirectiveGreen() self.ControlUnitMemReadEnable_3 = SvgFillDirectiveGreen() diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index 29210d8..6d54cb1 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -545,22 +545,17 @@ def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, An pipeline_register.memory_address ) - result.MemoryExecuteAluResultText.text = save_to_str( - pipeline_register.result + result.MemoryExecuteAluResult.do_highlight = ( + pipeline_register.result is not None ) - result.MemoryExecuteAluResultText2.text = save_to_str( - pipeline_register.result - ) - - result.MemoryExecuteAluResult.do_highlight = bool( - result.MemoryExecuteAluResultText.text - ) and bool(result.DataMemoryAddressText.text) - result.DataMemoryWriteDataText.text = save_to_str( - pipeline_register.memory_write_data - ) result.MemoryRegisterFileReadData2.do_highlight = bool( - result.DataMemoryWriteDataText.text + pipeline_register.control_unit_signals.mem_write + ) + result.DataMemoryWriteDataText.text = ( + save_to_str(pipeline_register.memory_write_data) + if result.MemoryRegisterFileReadData2.do_highlight + else "" ) result.DataMemoryReadDataText.text = save_to_str( @@ -583,22 +578,30 @@ def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, An pipeline_register.comparison_or_jump ) - result.MemoryExecuteAddOutText.text = save_to_str( - pipeline_register.pc_plus_imm - ) - result.MemoryExecuteAddOut.do_highlight = bool( - result.MemoryExecuteAddOutText.text + result.MemoryExecuteAddOut.do_highlight = result.MemoryJumpOut.do_highlight + result.MemoryExecuteAddOutText.text = ( + save_to_str(pipeline_register.pc_plus_imm) + if result.MemoryExecuteAddOut.do_highlight + else "" ) - result.MemoryFetchAddOutText.text = save_to_str( - pipeline_register.pc_plus_instruction_length + result.MemoryFetchAddOut.do_highlight = ( + pipeline_register.control_unit_signals.wb_src == 0 ) - result.MemoryFetchAddOut.do_highlight = bool( - result.MemoryFetchAddOutText.text + result.MemoryFetchAddOutText.text = ( + save_to_str(pipeline_register.pc_plus_instruction_length) + if result.MemoryFetchAddOut.do_highlight + else "" ) - result.MemoryImmGenText.text = save_to_str(pipeline_register.imm) - result.MemoryImmGen.do_highlight = bool(result.MemoryImmGenText.text) + result.MemoryImmGen.do_highlight = ( + pipeline_register.control_unit_signals.wb_src == 3 + ) + result.MemoryImmGenText.text = ( + save_to_str(pipeline_register.imm) + if result.MemoryImmGen.do_highlight + else "" + ) result.ControlUnitLeftRight1_3.do_highlight = bool( pipeline_register.control_unit_signals.jump @@ -610,6 +613,39 @@ def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, An pipeline_register.control_unit_signals.alu_to_pc ) + result.MemoryExecuteAluResultToMemory.do_highlight = bool( + pipeline_register.control_unit_signals.mem_read + ) or bool(pipeline_register.control_unit_signals.mem_write) + result.MemoryExecuteAluResultToFetchMux.do_highlight = ( + pipeline_register.control_unit_signals.alu_to_pc is True + ) + result.MemoryExecuteAluResultIntermediate.do_highlight = ( + result.MemoryExecuteAluResultToMemory.do_highlight + or result.MemoryExecuteAluResultToFetchMux.do_highlight + ) + result.MemoryExecuteAluResultText.text = ( + save_to_str(pipeline_register.result) + if result.MemoryExecuteAluResultToFetchMux.do_highlight + else "" + ) + result.MemoryExecuteAluResultToWbMux.do_highlight = ( + pipeline_register.control_unit_signals.wb_src == 2 + ) + result.MemoryExecuteAluResultText2.text = ( + save_to_str(pipeline_register.result) + if result.MemoryExecuteAluResultToWbMux.do_highlight + else "" + ) + + result.ControlUnitRegWriteEnable_3 = bool( + pipeline_register.control_unit_signals.reg_write + ) + result.ControlUnitMemReadEnable_3 = bool( + pipeline_register.control_unit_signals.mem_read + ) + result.ControlUnitMemWriteEnable_3 = bool( + pipeline_register.control_unit_signals.mem_write + ) return result.export() def _get_riscv_five_stage_WB_svg_update_values(self) -> list[tuple[str, str, Any]]: From 6342cfba90bd053876d4145ec6f9493d29c90f81 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Thu, 18 Apr 2024 15:33:34 +0200 Subject: [PATCH 023/138] Fix some stuff --- .../simulation/riscv_simulation.py | 20 ++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index 6d54cb1..b338898 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -276,8 +276,14 @@ def _get_riscv_five_stage_IF_svg_update_values(self) -> list[tuple[str, str, Any result.FetchAddOutToMux.do_highlight = bool(result.FetchAddOutText.text) result.FetchAddOut.do_highlight = bool(result.FetchAddOutText.text) - result.I_LengthText.text = save_to_str(pipeline_register.instruction.length) - result.FetchI_Length.do_highlight = bool(result.I_LengthText.text) + result.FetchI_Length.do_highlight = not isinstance( + pipeline_register.instruction, EmptyInstruction + ) + result.I_LengthText.text = ( + save_to_str(pipeline_register.instruction.length) + if result.FetchI_Length.do_highlight + else "" + ) result.PCFetchOutToExAdder.do_highlight = bool( pipeline_register.control_unit_signals.jump ) | bool(pipeline_register.control_unit_signals.branch) @@ -440,9 +446,6 @@ def _get_riscv_five_stage_EX_svg_update_values(self) -> list[tuple[str, str, Any result.ExecuteInstructionMemory4Text.text ) - result.ExecuteAddText.text = save_to_str(pipeline_register.pc_plus_imm) - result.ExecuteAdd.do_highlight = bool(result.ExecuteAddText.text) - result.ExecuteFetchAddOut.do_highlight = ( pipeline_register.control_unit_signals.wb_src == 0 ) @@ -492,6 +495,13 @@ def _get_riscv_five_stage_EX_svg_update_values(self) -> list[tuple[str, str, Any else "" ) + result.ExecuteAdd.do_highlight = result.ExecuteUpperFetchPCOut.do_highlight + result.ExecuteAddText.text = ( + save_to_str(pipeline_register.pc_plus_imm) + if result.ExecuteAdd.do_highlight + else "" + ) + result.ExecuteLowerFetchPCOut.do_highlight = ( pipeline_register.control_unit_signals.alu_src_1 is False ) From 85e87439be11edc26dc2a8192840f55b92c10be3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Thu, 18 Apr 2024 15:45:37 +0200 Subject: [PATCH 024/138] Added logic for the WB SVG Directives --- .../simulation/riscv_simulation.py | 30 ++++++++++++------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index b338898..26f403e 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -682,27 +682,31 @@ def _get_riscv_five_stage_WB_svg_update_values(self) -> list[tuple[str, str, Any result.WriteBackDataMemoryReadDataText.text = save_to_str( pipeline_register.memory_read_data - ) - result.WriteBackDataMemoryReadData.do_highlight = bool( - result.WriteBackDataMemoryReadDataText.text + ) # DELETE + result.WriteBackDataMemoryReadData.do_highlight = ( + pipeline_register.control_unit_signals.wb_src == 1 ) result.WriteBackExecuteAluResultText.text = save_to_str( pipeline_register.alu_result - ) - result.WriteBackExecuteAluResult.do_highlight = bool( - result.WriteBackExecuteAluResultText.text + ) # DELETE + result.WriteBackExecuteAluResult.do_highlight = ( + pipeline_register.control_unit_signals.wb_src == 2 ) result.WriteBackFetchAddOutText.text = save_to_str( pipeline_register.pc_plus_instruction_length - ) - result.WriteBackFetchAddOut.do_highlight = bool( - result.WriteBackFetchAddOutText.text + ) # DELETE + result.WriteBackFetchAddOut.do_highlight = ( + pipeline_register.control_unit_signals.wb_src == 0 ) - result.WriteBackImmGenText.text = save_to_str(pipeline_register.imm) - result.WriteBackImmGen.do_highlight = bool(result.WriteBackImmGenText.text) + result.WriteBackImmGenText.text = save_to_str( + pipeline_register.imm + ) # DELETE + result.WriteBackImmGen.do_highlight = ( + pipeline_register.control_unit_signals.wb_src == 3 + ) result.wbsrc.text = save_to_str( pipeline_register.control_unit_signals.wb_src @@ -710,6 +714,10 @@ def _get_riscv_five_stage_WB_svg_update_values(self) -> list[tuple[str, str, Any result.ControlUnitLeftRight2_4.do_highlight = bool( pipeline_register.control_unit_signals.wb_src ) + + result.ControlUnitRegWriteEnable_4.do_highlight = ( + pipeline_register.control_unit_signals.reg_write is True + ) return result.export() def _get_riscv_five_stage_OTHER_svg_update_values( From f278c353fc31de188a9fe102071ae2b23827739f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Thu, 18 Apr 2024 15:57:07 +0200 Subject: [PATCH 025/138] Removed unnecessary text elements from the svg --- .../gui/riscv_fiveStage_svg_directives.py | 8 - .../simulation/riscv_simulation.py | 34 +-- webgui/src/img/riscv_five_stage_pipeline.svg | 237 +----------------- 3 files changed, 13 insertions(+), 266 deletions(-) diff --git a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py index 138aa91..871a5a0 100644 --- a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py +++ b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py @@ -28,7 +28,6 @@ def __init__(self): self.InstructionReadAddressText = SvgWriteLeftDirective() self.PC = SvgWriteCenterDirective() self.FetchPCOut = SvgFillDirectiveBlue() - self.FetchAddOutText = SvgWriteCenterDirective() self.FetchAddOut = SvgFillDirectiveBlue() self.I_LengthText = SvgWriteCenterDirective() self.FetchI_Length = SvgFillDirectiveBlue() @@ -118,7 +117,6 @@ class RiscvFiveStageMEMSvgDirectives(RiscvSvgDirectivesBase): def __init__(self): self.Memory = SvgWriteCenterDirective() self.DataMemoryAddressText = SvgWriteLeftDirective() - self.MemoryExecuteAluResultText = SvgWriteCenterDirective() self.MemoryExecuteAluResultText2 = SvgWriteCenterDirective() self.MemoryExecuteAluResult = SvgFillDirectiveBlue() self.DataMemoryWriteDataText = SvgWriteLeftDirective() @@ -129,7 +127,6 @@ def __init__(self): self.MemoryInstructionMemory4 = SvgFillDirectiveBlue() self.MemoryALUComparison = SvgFillDirectiveGreen() self.MemoryJumpOut = SvgFillDirectiveGreen() - self.MemoryExecuteAddOutText = SvgWriteCenterDirective() self.MemoryExecuteAddOut = SvgFillDirectiveBlue() self.MemoryFetchAddOutText = SvgWriteCenterDirective() self.MemoryFetchAddOut = SvgFillDirectiveBlue() @@ -154,13 +151,9 @@ def __init__(self): self.WriteBackMuxOut = SvgFillDirectiveBlue() self.RegisterFileWriteRegisterText = SvgWriteLeftDirective() self.WriteBackInstructionMemory4 = SvgFillDirectiveBlue() - self.WriteBackDataMemoryReadDataText = SvgWriteCenterDirective() self.WriteBackDataMemoryReadData = SvgFillDirectiveBlue() - self.WriteBackExecuteAluResultText = SvgWriteCenterDirective() self.WriteBackExecuteAluResult = SvgFillDirectiveBlue() - self.WriteBackFetchAddOutText = SvgWriteCenterDirective() self.WriteBackFetchAddOut = SvgFillDirectiveBlue() - self.WriteBackImmGenText = SvgWriteCenterDirective() self.WriteBackImmGen = SvgFillDirectiveBlue() self.wbsrc = SvgWriteCenterDirective() self.ControlUnitLeftRight2_4 = SvgFillDirectiveBlue() @@ -169,7 +162,6 @@ def __init__(self): class RiscvFiveStageOTHERSvgDirectives(RiscvSvgDirectivesBase): def __init__(self): - self.FetchRightMuxOutText = SvgWriteCenterDirective() self.FetchLeftMuxOutText = SvgWriteCenterDirective() self.FetchRightMuxOut = SvgFillDirectiveBlue() self.FetchPCIn = SvgFillDirectiveBlue() diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index 26f403e..f404c57 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -270,11 +270,12 @@ def _get_riscv_five_stage_IF_svg_update_values(self) -> list[tuple[str, str, Any result.InstructionReadAddressText.text ) - result.FetchAddOutText.text = save_to_str( - pipeline_register.pc_plus_instruction_length + result.FetchAddOutToMux.do_highlight = ( + pipeline_register.pc_plus_instruction_length is not None + ) + result.FetchAddOut.do_highlight = ( + pipeline_register.pc_plus_instruction_length is not None ) - result.FetchAddOutToMux.do_highlight = bool(result.FetchAddOutText.text) - result.FetchAddOut.do_highlight = bool(result.FetchAddOutText.text) result.FetchI_Length.do_highlight = not isinstance( pipeline_register.instruction, EmptyInstruction @@ -589,11 +590,6 @@ def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, An ) result.MemoryExecuteAddOut.do_highlight = result.MemoryJumpOut.do_highlight - result.MemoryExecuteAddOutText.text = ( - save_to_str(pipeline_register.pc_plus_imm) - if result.MemoryExecuteAddOut.do_highlight - else "" - ) result.MemoryFetchAddOut.do_highlight = ( pipeline_register.control_unit_signals.wb_src == 0 @@ -633,11 +629,6 @@ def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, An result.MemoryExecuteAluResultToMemory.do_highlight or result.MemoryExecuteAluResultToFetchMux.do_highlight ) - result.MemoryExecuteAluResultText.text = ( - save_to_str(pipeline_register.result) - if result.MemoryExecuteAluResultToFetchMux.do_highlight - else "" - ) result.MemoryExecuteAluResultToWbMux.do_highlight = ( pipeline_register.control_unit_signals.wb_src == 2 ) @@ -680,30 +671,18 @@ def _get_riscv_five_stage_WB_svg_update_values(self) -> list[tuple[str, str, Any result.RegisterFileWriteRegisterText.text ) - result.WriteBackDataMemoryReadDataText.text = save_to_str( - pipeline_register.memory_read_data - ) # DELETE result.WriteBackDataMemoryReadData.do_highlight = ( pipeline_register.control_unit_signals.wb_src == 1 ) - result.WriteBackExecuteAluResultText.text = save_to_str( - pipeline_register.alu_result - ) # DELETE result.WriteBackExecuteAluResult.do_highlight = ( pipeline_register.control_unit_signals.wb_src == 2 ) - result.WriteBackFetchAddOutText.text = save_to_str( - pipeline_register.pc_plus_instruction_length - ) # DELETE result.WriteBackFetchAddOut.do_highlight = ( pipeline_register.control_unit_signals.wb_src == 0 ) - result.WriteBackImmGenText.text = save_to_str( - pipeline_register.imm - ) # DELETE result.WriteBackImmGen.do_highlight = ( pipeline_register.control_unit_signals.wb_src == 3 ) @@ -747,10 +726,9 @@ def _get_riscv_five_stage_OTHER_svg_update_values( else: pc_pl_imm_or_il_or_alures = pc_pl_imm_or_il - result.FetchRightMuxOutText.text = save_to_str(pc_pl_imm_or_il) result.FetchLeftMuxOutText.text = save_to_str(pc_pl_imm_or_il_or_alures) - result.FetchRightMuxOut.do_highlight = bool(result.FetchRightMuxOutText.text) + result.FetchRightMuxOut.do_highlight = pc_pl_imm_or_il is not None result.FetchPCIn.do_highlight = bool(result.FetchLeftMuxOutText.text) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 6468cb2..2e24691 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,14 +25,14 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.3535534" - inkscape:cx="4075.7634" - inkscape:cy="2978.3337" - inkscape:window-width="1920" + inkscape:zoom="0.1767767" + inkscape:cx="5023.2864" + inkscape:cy="2302.3396" + inkscape:window-width="960" inkscape:window-height="1007" - inkscape:window-x="0" + inkscape:window-x="2880" inkscape:window-y="0" - inkscape:window-maximized="1" + inkscape:window-maximized="0" showguides="false" inkscape:lockguides="false" inkscape:current-layer="layer6">1010101010110101010101wbsrc101010101011010101010110101010101101010101011010101010110101010101 Date: Thu, 18 Apr 2024 16:06:21 +0200 Subject: [PATCH 026/138] Did some refactoring --- .../simulation/riscv_simulation.py | 341 ++++++------------ 1 file changed, 120 insertions(+), 221 deletions(-) diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index f404c57..1e68dfa 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -250,239 +250,193 @@ def get_riscv_five_stage_svg_update_values(self) -> list[tuple[str, str, Any]]: def _get_riscv_five_stage_IF_svg_update_values(self) -> list[tuple[str, str, Any]]: """Returns all information needed to update IF stage part of svg.""" result = RiscvFiveStageIFSvgDirectives() - pipeline_register = self.state.pipeline.pipeline_registers[0] + pr = self.state.pipeline.pipeline_registers[0] - result.Fetch.text = pipeline_register.instruction.mnemonic + result.Fetch.text = pr.instruction.mnemonic result.PC.text = self.state.previous_program_counter - if isinstance(pipeline_register, InstructionFetchPipelineRegister): - result.InstructionMemoryInstrText.text = ( - pipeline_register.instruction.__repr__() - ) + if isinstance(pr, InstructionFetchPipelineRegister): + csignals = pr.control_unit_signals + result.InstructionMemoryInstrText.text = pr.instruction.__repr__() result.InstructionMemory.do_highlight = bool( result.InstructionMemoryInstrText.text ) result.InstructionReadAddressText.text = save_to_str( - pipeline_register.address_of_instruction + pr.address_of_instruction ) result.FetchPCOut.do_highlight = bool( result.InstructionReadAddressText.text ) result.FetchAddOutToMux.do_highlight = ( - pipeline_register.pc_plus_instruction_length is not None - ) - result.FetchAddOut.do_highlight = ( - pipeline_register.pc_plus_instruction_length is not None + pr.pc_plus_instruction_length is not None ) + result.FetchAddOut.do_highlight = pr.pc_plus_instruction_length is not None result.FetchI_Length.do_highlight = not isinstance( - pipeline_register.instruction, EmptyInstruction + pr.instruction, EmptyInstruction ) result.I_LengthText.text = ( - save_to_str(pipeline_register.instruction.length) + save_to_str(pr.instruction.length) if result.FetchI_Length.do_highlight else "" ) - result.PCFetchOutToExAdder.do_highlight = bool( - pipeline_register.control_unit_signals.jump - ) | bool(pipeline_register.control_unit_signals.branch) - result.PCFetchOutToExMux.do_highlight = ( - pipeline_register.control_unit_signals.alu_src_1 is not None - and not bool(pipeline_register.control_unit_signals.alu_src_1) + result.PCFetchOutToExAdder.do_highlight = bool(csignals.jump) | bool( + csignals.branch ) - result.FetchAddOutToPReg.do_highlight = ( - pipeline_register.control_unit_signals.wb_src == 0 + result.PCFetchOutToExMux.do_highlight = ( + csignals.alu_src_1 is not None and not bool(csignals.alu_src_1) ) + result.FetchAddOutToPReg.do_highlight = csignals.wb_src == 0 return result.export() def _get_riscv_five_stage_ID_svg_update_values(self) -> list[tuple[str, str, Any]]: """Returns all information needed to update ID stage part of svg.""" result = RiscvFiveStageIDSvgDirectives() - pipeline_register = self.state.pipeline.pipeline_registers[1] + pr = self.state.pipeline.pipeline_registers[1] - result.Decode.text = pipeline_register.instruction.mnemonic + result.Decode.text = pr.instruction.mnemonic - if isinstance(pipeline_register, InstructionDecodePipelineRegister): + if isinstance(pr, InstructionDecodePipelineRegister): + csignals = pr.control_unit_signals result.RegisterFileReadAddress1Text.text = save_to_str( - pipeline_register.register_read_addr_1 + pr.register_read_addr_1 ) result.DecodeInstructionMemory1.do_highlight = bool( result.RegisterFileReadAddress1Text.text ) result.RegisterFileReadAddress2Text.text = save_to_str( - pipeline_register.register_read_addr_2 + pr.register_read_addr_2 ) result.DecodeInstructionMemory2.do_highlight = bool( result.RegisterFileReadAddress2Text.text ) - result.RegisterFileReadData1Text.text = save_to_str( - pipeline_register.register_read_data_1 - ) + result.RegisterFileReadData1Text.text = save_to_str(pr.register_read_data_1) result.RegisterFileReadData1.do_highlight = bool( result.RegisterFileReadData1Text.text ) - result.RegisterFileReadData2Text.text = save_to_str( - pipeline_register.register_read_data_2 - ) + result.RegisterFileReadData2Text.text = save_to_str(pr.register_read_data_2) result.RegisterFileReadData2.do_highlight = bool( result.RegisterFileReadData2Text.text ) - result.ImmGenText.text = save_to_str(pipeline_register.imm) + result.ImmGenText.text = save_to_str(pr.imm) result.ImmGenOut.do_highlight = bool(result.ImmGenText.text) result.DecodeInstructionMemory3.do_highlight = bool(result.ImmGenText.text) - result.DecodeInstructionMemory4Text.text = save_to_str( - pipeline_register.write_register - ) + result.DecodeInstructionMemory4Text.text = save_to_str(pr.write_register) result.DecodeInstructionMemory4.do_highlight = bool( result.DecodeInstructionMemory4Text.text ) - result.DecodeFetchAddOut.do_highlight = ( - pipeline_register.control_unit_signals.wb_src == 0 - ) + result.DecodeFetchAddOut.do_highlight = csignals.wb_src == 0 result.DecodeFetchAddOutText.text = ( - save_to_str(pipeline_register.pc_plus_instruction_length) + save_to_str(pr.pc_plus_instruction_length) if result.DecodeFetchAddOut.do_highlight else "" ) - result.DecodeUpperFetchPCOut.do_highlight = bool( - pipeline_register.control_unit_signals.jump - ) | bool(pipeline_register.control_unit_signals.branch) + result.DecodeUpperFetchPCOut.do_highlight = bool(csignals.jump) | bool( + csignals.branch + ) result.DecodeUpperFetchPCOutText.text = ( - save_to_str(pipeline_register.address_of_instruction) + save_to_str(pr.address_of_instruction) if result.DecodeUpperFetchPCOut.do_highlight else "" ) - result.DecodeLowerFetchPCOut.do_highlight = ( - pipeline_register.control_unit_signals.alu_src_1 == 0 - ) + result.DecodeLowerFetchPCOut.do_highlight = csignals.alu_src_1 == 0 result.DecodeLowerFetchPCOutText.text = ( - save_to_str(pipeline_register.address_of_instruction) + save_to_str(pr.address_of_instruction) if result.DecodeLowerFetchPCOut.do_highlight else "" ) result.DecodeInstructionMemory.do_highlight = not isinstance( - pipeline_register.instruction, EmptyInstruction - ) - result.ControlUnitLeftRight1_1.do_highlight = bool( - pipeline_register.control_unit_signals.jump - ) - result.ControlUnitLeftRight2_1.do_highlight = bool( - pipeline_register.control_unit_signals.wb_src - ) - result.ControlUnitLeftRight3_1.do_highlight = bool( - pipeline_register.control_unit_signals.alu_src_1 - ) - result.ControlUnitLeftRight4_1.do_highlight = bool( - pipeline_register.control_unit_signals.alu_src_2 - ) - result.ControlUnitLeft_1.do_highlight = bool( - pipeline_register.control_unit_signals.alu_to_pc - ) - result.ControlUnitRegWriteEnable_1.do_highlight = bool( - pipeline_register.control_unit_signals.reg_write - ) - result.ControlUnitMemWriteEnable_1.do_highlight = bool( - pipeline_register.control_unit_signals.mem_write - ) - result.ControlUnitMemReadEnable_1.do_highlight = bool( - pipeline_register.control_unit_signals.mem_read + pr.instruction, EmptyInstruction ) + result.ControlUnitLeftRight1_1.do_highlight = bool(csignals.jump) + result.ControlUnitLeftRight2_1.do_highlight = bool(csignals.wb_src) + result.ControlUnitLeftRight3_1.do_highlight = bool(csignals.alu_src_1) + result.ControlUnitLeftRight4_1.do_highlight = bool(csignals.alu_src_2) + result.ControlUnitLeft_1.do_highlight = bool(csignals.alu_to_pc) + result.ControlUnitRegWriteEnable_1.do_highlight = bool(csignals.reg_write) + result.ControlUnitMemWriteEnable_1.do_highlight = bool(csignals.mem_write) + result.ControlUnitMemReadEnable_1.do_highlight = bool(csignals.mem_read) result.DecodeInstructionMemoryIntermediate.do_highlight = bool( - pipeline_register.control_unit_signals.reg_write - ) | (pipeline_register.imm is not None) + csignals.reg_write + ) | (pr.imm is not None) return result.export() def _get_riscv_five_stage_EX_svg_update_values(self) -> list[tuple[str, str, Any]]: """Returns all information needed to update EX stage part of svg.""" result = RiscvFiveStageEXSvgDirectives() - pipeline_register = self.state.pipeline.pipeline_registers[2] + pr = self.state.pipeline.pipeline_registers[2] - result.Execute.text = pipeline_register.instruction.mnemonic + result.Execute.text = pr.instruction.mnemonic - if isinstance(pipeline_register, ExecutePipelineRegister): - result.ExecuteRightMuxOutText.text = save_to_str(pipeline_register.alu_in_1) + if isinstance(pr, ExecutePipelineRegister): + csignals = pr.control_unit_signals + result.ExecuteRightMuxOutText.text = save_to_str(pr.alu_in_1) result.ExecuteRightMuxOut.do_highlight = bool( result.ExecuteRightMuxOutText.text ) - result.ExecuteLeftMuxOutText.text = save_to_str(pipeline_register.alu_in_2) + result.ExecuteLeftMuxOutText.text = save_to_str(pr.alu_in_2) result.ExecuteLeftMuxOut.do_highlight = bool( result.ExecuteLeftMuxOutText.text ) result.ExecuteRegisterFileReadData1.do_highlight = bool( - save_to_str(pipeline_register.register_read_data_1) + save_to_str(pr.register_read_data_1) ) result.ExecuteRegisterFileReadData2Text2.text = save_to_str( - pipeline_register.register_read_data_2 + pr.register_read_data_2 ) result.ExecuteRegisterFileReadData2.do_highlight = bool( result.ExecuteRegisterFileReadData2Text2.text ) - result.ExecuteImmGen.do_highlight = pipeline_register.imm is not None + result.ExecuteImmGen.do_highlight = pr.imm is not None - result.ALUResultText.text = save_to_str(pipeline_register.result) + result.ALUResultText.text = save_to_str(pr.result) result.ExecuteAluResult.do_highlight = bool(result.ALUResultText.text) - result.ExecuteInstructionMemory4Text.text = save_to_str( - pipeline_register.write_register - ) + result.ExecuteInstructionMemory4Text.text = save_to_str(pr.write_register) result.ExecuteInstructionMemory4.do_highlight = bool( result.ExecuteInstructionMemory4Text.text ) - result.ExecuteFetchAddOut.do_highlight = ( - pipeline_register.control_unit_signals.wb_src == 0 - ) + result.ExecuteFetchAddOut.do_highlight = csignals.wb_src == 0 result.ExecuteFetchAddOutText.text = ( - save_to_str(pipeline_register.pc_plus_instruction_length) + save_to_str(pr.pc_plus_instruction_length) if result.ExecuteFetchAddOut.do_highlight else "" ) - result.ALUComparison.do_highlight = bool(pipeline_register.comparison) + result.ALUComparison.do_highlight = bool(pr.comparison) - result.ControlUnitLeftRight1_2.do_highlight = bool( - pipeline_register.control_unit_signals.jump - ) - result.ControlUnitLeftRight2_2.do_highlight = bool( - pipeline_register.control_unit_signals.wb_src - ) - result.ControlUnitLeftRight3_2.do_highlight = bool( - pipeline_register.control_unit_signals.alu_src_1 - ) - result.ControlUnitLeftRight4_2.do_highlight = bool( - pipeline_register.control_unit_signals.alu_src_2 - ) - result.ControlUnitLeft_2.do_highlight = bool( - pipeline_register.control_unit_signals.alu_to_pc - ) + result.ControlUnitLeftRight1_2.do_highlight = bool(csignals.jump) + result.ControlUnitLeftRight2_2.do_highlight = bool(csignals.wb_src) + result.ControlUnitLeftRight3_2.do_highlight = bool(csignals.alu_src_1) + result.ControlUnitLeftRight4_2.do_highlight = bool(csignals.alu_src_2) + result.ControlUnitLeft_2.do_highlight = bool(csignals.alu_to_pc) - result.AluControl.do_highlight = bool( - save_to_str(pipeline_register.control_unit_signals.alu_op) - ) + result.AluControl.do_highlight = bool(save_to_str(csignals.alu_op)) - result.ExecuteImmediateToAdder.do_highlight = bool( - pipeline_register.control_unit_signals.jump - ) | bool(pipeline_register.control_unit_signals.branch) + result.ExecuteImmediateToAdder.do_highlight = bool(csignals.jump) | bool( + csignals.branch + ) result.ExecuteImmGenText1.text = ( - save_to_str(pipeline_register.imm) + save_to_str(pr.imm) if result.ExecuteImmediateToAdder.do_highlight else "" ) @@ -491,211 +445,156 @@ def _get_riscv_five_stage_EX_svg_update_values(self) -> list[tuple[str, str, Any result.ExecuteImmediateToAdder.do_highlight ) result.ExecuteUpperFetchPCOutText.text = ( - save_to_str(pipeline_register.address_of_instruction) + save_to_str(pr.address_of_instruction) if result.ExecuteUpperFetchPCOut.do_highlight else "" ) result.ExecuteAdd.do_highlight = result.ExecuteUpperFetchPCOut.do_highlight result.ExecuteAddText.text = ( - save_to_str(pipeline_register.pc_plus_imm) - if result.ExecuteAdd.do_highlight - else "" + save_to_str(pr.pc_plus_imm) if result.ExecuteAdd.do_highlight else "" ) - result.ExecuteLowerFetchPCOut.do_highlight = ( - pipeline_register.control_unit_signals.alu_src_1 is False - ) + result.ExecuteLowerFetchPCOut.do_highlight = csignals.alu_src_1 is False - result.ExecuteImmediateToMux.do_highlight = ( - pipeline_register.control_unit_signals.alu_src_2 - ) + result.ExecuteImmediateToMux.do_highlight = csignals.alu_src_2 - result.ExecuteImmediateToWbMux.do_highlight = ( - pipeline_register.control_unit_signals.wb_src == 3 - ) + result.ExecuteImmediateToWbMux.do_highlight = csignals.wb_src == 3 result.ExecuteImmGenText3.text = ( - save_to_str(pipeline_register.imm) + save_to_str(pr.imm) if result.ExecuteImmediateToWbMux.do_highlight else "" ) result.ExecuteImmediateInterediate.do_highlight = ( - bool(pipeline_register.control_unit_signals.alu_src_2) - or result.ExecuteImmediateToAdder.do_highlight + bool(csignals.alu_src_2) or result.ExecuteImmediateToAdder.do_highlight ) result.ExecuteRegisterFileReadData2ToMux.do_highlight = ( - pipeline_register.control_unit_signals.alu_src_2 is False + csignals.alu_src_2 is False ) result.ExecuteRegisterFileReadData2ToMemory.do_highlight = bool( - pipeline_register.control_unit_signals.mem_write + csignals.mem_write ) - result.ControlUnitRegWriteEnable_2.do_highlight = bool( - pipeline_register.control_unit_signals.reg_write - ) - result.ControlUnitMemWriteEnable_2.do_highlight = bool( - pipeline_register.control_unit_signals.mem_write - ) - result.ControlUnitMemReadEnable_2.do_highlight = bool( - pipeline_register.control_unit_signals.mem_read - ) + result.ControlUnitRegWriteEnable_2.do_highlight = bool(csignals.reg_write) + result.ControlUnitMemWriteEnable_2.do_highlight = bool(csignals.mem_write) + result.ControlUnitMemReadEnable_2.do_highlight = bool(csignals.mem_read) return result.export() def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, Any]]: """Returns all information needed to update MEM stage part of svg.""" result = RiscvFiveStageMEMSvgDirectives() - pipeline_register = self.state.pipeline.pipeline_registers[3] + pr = self.state.pipeline.pipeline_registers[3] - result.Memory.text = pipeline_register.instruction.mnemonic + result.Memory.text = pr.instruction.mnemonic - if isinstance(pipeline_register, MemoryAccessPipelineRegister): - result.DataMemoryAddressText.text = save_to_str( - pipeline_register.memory_address - ) + if isinstance(pr, MemoryAccessPipelineRegister): + csignals = pr.control_unit_signals + result.DataMemoryAddressText.text = save_to_str(pr.memory_address) - result.MemoryExecuteAluResult.do_highlight = ( - pipeline_register.result is not None - ) + result.MemoryExecuteAluResult.do_highlight = pr.result is not None - result.MemoryRegisterFileReadData2.do_highlight = bool( - pipeline_register.control_unit_signals.mem_write - ) + result.MemoryRegisterFileReadData2.do_highlight = bool(csignals.mem_write) result.DataMemoryWriteDataText.text = ( - save_to_str(pipeline_register.memory_write_data) + save_to_str(pr.memory_write_data) if result.MemoryRegisterFileReadData2.do_highlight else "" ) - result.DataMemoryReadDataText.text = save_to_str( - pipeline_register.memory_read_data - ) + result.DataMemoryReadDataText.text = save_to_str(pr.memory_read_data) result.DataMemoryReadData.do_highlight = bool( result.DataMemoryReadDataText.text ) - result.MemoryInstructionMemory4Text.text = save_to_str( - pipeline_register.write_register - ) + result.MemoryInstructionMemory4Text.text = save_to_str(pr.write_register) result.MemoryInstructionMemory4.do_highlight = bool( result.MemoryInstructionMemory4Text.text ) - result.MemoryALUComparison.do_highlight = bool(pipeline_register.comparison) + result.MemoryALUComparison.do_highlight = bool(pr.comparison) - result.MemoryJumpOut.do_highlight = bool( - pipeline_register.comparison_or_jump - ) + result.MemoryJumpOut.do_highlight = bool(pr.comparison_or_jump) result.MemoryExecuteAddOut.do_highlight = result.MemoryJumpOut.do_highlight - result.MemoryFetchAddOut.do_highlight = ( - pipeline_register.control_unit_signals.wb_src == 0 - ) + result.MemoryFetchAddOut.do_highlight = csignals.wb_src == 0 result.MemoryFetchAddOutText.text = ( - save_to_str(pipeline_register.pc_plus_instruction_length) + save_to_str(pr.pc_plus_instruction_length) if result.MemoryFetchAddOut.do_highlight else "" ) - result.MemoryImmGen.do_highlight = ( - pipeline_register.control_unit_signals.wb_src == 3 - ) + result.MemoryImmGen.do_highlight = csignals.wb_src == 3 result.MemoryImmGenText.text = ( - save_to_str(pipeline_register.imm) - if result.MemoryImmGen.do_highlight - else "" + save_to_str(pr.imm) if result.MemoryImmGen.do_highlight else "" ) - result.ControlUnitLeftRight1_3.do_highlight = bool( - pipeline_register.control_unit_signals.jump - ) - result.ControlUnitLeftRight2_3.do_highlight = bool( - pipeline_register.control_unit_signals.wb_src - ) - result.ControlUnitLeft_3.do_highlight = bool( - pipeline_register.control_unit_signals.alu_to_pc - ) + result.ControlUnitLeftRight1_3.do_highlight = bool(csignals.jump) + result.ControlUnitLeftRight2_3.do_highlight = bool(csignals.wb_src) + result.ControlUnitLeft_3.do_highlight = bool(csignals.alu_to_pc) result.MemoryExecuteAluResultToMemory.do_highlight = bool( - pipeline_register.control_unit_signals.mem_read - ) or bool(pipeline_register.control_unit_signals.mem_write) + csignals.mem_read + ) or bool(csignals.mem_write) result.MemoryExecuteAluResultToFetchMux.do_highlight = ( - pipeline_register.control_unit_signals.alu_to_pc is True + csignals.alu_to_pc is True ) result.MemoryExecuteAluResultIntermediate.do_highlight = ( result.MemoryExecuteAluResultToMemory.do_highlight or result.MemoryExecuteAluResultToFetchMux.do_highlight ) - result.MemoryExecuteAluResultToWbMux.do_highlight = ( - pipeline_register.control_unit_signals.wb_src == 2 - ) + result.MemoryExecuteAluResultToWbMux.do_highlight = csignals.wb_src == 2 result.MemoryExecuteAluResultText2.text = ( - save_to_str(pipeline_register.result) + save_to_str(pr.result) if result.MemoryExecuteAluResultToWbMux.do_highlight else "" ) - result.ControlUnitRegWriteEnable_3 = bool( - pipeline_register.control_unit_signals.reg_write - ) - result.ControlUnitMemReadEnable_3 = bool( - pipeline_register.control_unit_signals.mem_read - ) - result.ControlUnitMemWriteEnable_3 = bool( - pipeline_register.control_unit_signals.mem_write - ) + result.ControlUnitRegWriteEnable_3 = bool(csignals.reg_write) + result.ControlUnitMemReadEnable_3 = bool(csignals.mem_read) + result.ControlUnitMemWriteEnable_3 = bool(csignals.mem_write) return result.export() def _get_riscv_five_stage_WB_svg_update_values(self) -> list[tuple[str, str, Any]]: """Returns all information needed to update WB stage part of svg.""" result = RiscvFiveStageWBSvgDirectives() - pipeline_register = self.state.pipeline.pipeline_registers[4] + pr = self.state.pipeline.pipeline_registers[4] - result.WriteBack.text = pipeline_register.instruction.mnemonic + result.WriteBack.text = pr.instruction.mnemonic - if isinstance(pipeline_register, RegisterWritebackPipelineRegister): - result.RegisterFileWriteDataText.text = save_to_str( - pipeline_register.register_write_data - ) + if isinstance(pr, RegisterWritebackPipelineRegister): + csignals = pr.control_unit_signals + result.RegisterFileWriteDataText.text = save_to_str(pr.register_write_data) result.WriteBackMuxOut.do_highlight = bool( result.RegisterFileWriteDataText.text ) - result.RegisterFileWriteRegisterText.text = save_to_str( - pipeline_register.write_register - ) + result.RegisterFileWriteRegisterText.text = save_to_str(pr.write_register) result.WriteBackInstructionMemory4.do_highlight = bool( result.RegisterFileWriteRegisterText.text ) - result.WriteBackDataMemoryReadData.do_highlight = ( - pipeline_register.control_unit_signals.wb_src == 1 - ) + result.WriteBackDataMemoryReadData.do_highlight = csignals.wb_src == 1 result.WriteBackExecuteAluResult.do_highlight = ( - pipeline_register.control_unit_signals.wb_src == 2 + pr.control_unit_signals.wb_src == 2 ) result.WriteBackFetchAddOut.do_highlight = ( - pipeline_register.control_unit_signals.wb_src == 0 + pr.control_unit_signals.wb_src == 0 ) - result.WriteBackImmGen.do_highlight = ( - pipeline_register.control_unit_signals.wb_src == 3 - ) + result.WriteBackImmGen.do_highlight = pr.control_unit_signals.wb_src == 3 - result.wbsrc.text = save_to_str( - pipeline_register.control_unit_signals.wb_src - ) + result.wbsrc.text = save_to_str(pr.control_unit_signals.wb_src) result.ControlUnitLeftRight2_4.do_highlight = bool( - pipeline_register.control_unit_signals.wb_src + pr.control_unit_signals.wb_src ) result.ControlUnitRegWriteEnable_4.do_highlight = ( - pipeline_register.control_unit_signals.reg_write is True + pr.control_unit_signals.reg_write is True ) return result.export() From 096ffedafc824d5f796ab606c255bc7eaf14f167 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Thu, 18 Apr 2024 16:18:51 +0200 Subject: [PATCH 027/138] Some more refactoring --- .../simulation/riscv_simulation.py | 87 ++++++++----------- 1 file changed, 37 insertions(+), 50 deletions(-) diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index 1e68dfa..58e5335 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -36,8 +36,17 @@ ) -def save_to_str(input: Any) -> str: - return str(input) if input is not None else "" +def save_to_str(input: Any, input_valid=True) -> str: + """Turns the input into a string. Will result in an empty string if the input is None or if the optional input_valid flag is False. + + Args: + input (Any): Thing to be turned into a string. + input_valid (bool, optional): Flag to indicate if the input is valid. The result will be an empty string if this is False. Defaults to True. + + Returns: + str: The requested string. + """ + return str(input) if input is not None and input_valid else "" class RiscvSimulation(Simulation): @@ -277,10 +286,8 @@ def _get_riscv_five_stage_IF_svg_update_values(self) -> list[tuple[str, str, Any result.FetchI_Length.do_highlight = not isinstance( pr.instruction, EmptyInstruction ) - result.I_LengthText.text = ( - save_to_str(pr.instruction.length) - if result.FetchI_Length.do_highlight - else "" + result.I_LengthText.text = save_to_str( + pr.instruction.length, result.FetchI_Length.do_highlight ) result.PCFetchOutToExAdder.do_highlight = bool(csignals.jump) | bool( csignals.branch @@ -335,26 +342,20 @@ def _get_riscv_five_stage_ID_svg_update_values(self) -> list[tuple[str, str, Any ) result.DecodeFetchAddOut.do_highlight = csignals.wb_src == 0 - result.DecodeFetchAddOutText.text = ( - save_to_str(pr.pc_plus_instruction_length) - if result.DecodeFetchAddOut.do_highlight - else "" + result.DecodeFetchAddOutText.text = save_to_str( + pr.pc_plus_instruction_length, result.DecodeFetchAddOut.do_highlight ) result.DecodeUpperFetchPCOut.do_highlight = bool(csignals.jump) | bool( csignals.branch ) - result.DecodeUpperFetchPCOutText.text = ( - save_to_str(pr.address_of_instruction) - if result.DecodeUpperFetchPCOut.do_highlight - else "" + result.DecodeUpperFetchPCOutText.text = save_to_str( + pr.address_of_instruction, result.DecodeUpperFetchPCOut.do_highlight ) result.DecodeLowerFetchPCOut.do_highlight = csignals.alu_src_1 == 0 - result.DecodeLowerFetchPCOutText.text = ( - save_to_str(pr.address_of_instruction) - if result.DecodeLowerFetchPCOut.do_highlight - else "" + result.DecodeLowerFetchPCOutText.text = save_to_str( + pr.address_of_instruction, result.DecodeLowerFetchPCOut.do_highlight ) result.DecodeInstructionMemory.do_highlight = not isinstance( @@ -416,10 +417,8 @@ def _get_riscv_five_stage_EX_svg_update_values(self) -> list[tuple[str, str, Any ) result.ExecuteFetchAddOut.do_highlight = csignals.wb_src == 0 - result.ExecuteFetchAddOutText.text = ( - save_to_str(pr.pc_plus_instruction_length) - if result.ExecuteFetchAddOut.do_highlight - else "" + result.ExecuteFetchAddOutText.text = save_to_str( + pr.pc_plus_instruction_length, result.ExecuteFetchAddOut.do_highlight ) result.ALUComparison.do_highlight = bool(pr.comparison) @@ -435,24 +434,20 @@ def _get_riscv_five_stage_EX_svg_update_values(self) -> list[tuple[str, str, Any result.ExecuteImmediateToAdder.do_highlight = bool(csignals.jump) | bool( csignals.branch ) - result.ExecuteImmGenText1.text = ( - save_to_str(pr.imm) - if result.ExecuteImmediateToAdder.do_highlight - else "" + result.ExecuteImmGenText1.text = save_to_str( + pr.imm, result.ExecuteImmediateToAdder.do_highlight ) result.ExecuteUpperFetchPCOut.do_highlight = ( result.ExecuteImmediateToAdder.do_highlight ) - result.ExecuteUpperFetchPCOutText.text = ( - save_to_str(pr.address_of_instruction) - if result.ExecuteUpperFetchPCOut.do_highlight - else "" + result.ExecuteUpperFetchPCOutText.text = save_to_str( + pr.address_of_instruction, result.ExecuteUpperFetchPCOut.do_highlight ) result.ExecuteAdd.do_highlight = result.ExecuteUpperFetchPCOut.do_highlight - result.ExecuteAddText.text = ( - save_to_str(pr.pc_plus_imm) if result.ExecuteAdd.do_highlight else "" + result.ExecuteAddText.text = save_to_str( + pr.pc_plus_imm, result.ExecuteAdd.do_highlight ) result.ExecuteLowerFetchPCOut.do_highlight = csignals.alu_src_1 is False @@ -460,10 +455,8 @@ def _get_riscv_five_stage_EX_svg_update_values(self) -> list[tuple[str, str, Any result.ExecuteImmediateToMux.do_highlight = csignals.alu_src_2 result.ExecuteImmediateToWbMux.do_highlight = csignals.wb_src == 3 - result.ExecuteImmGenText3.text = ( - save_to_str(pr.imm) - if result.ExecuteImmediateToWbMux.do_highlight - else "" + result.ExecuteImmGenText3.text = save_to_str( + pr.imm, result.ExecuteImmediateToWbMux.do_highlight ) result.ExecuteImmediateInterediate.do_highlight = ( @@ -497,10 +490,8 @@ def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, An result.MemoryExecuteAluResult.do_highlight = pr.result is not None result.MemoryRegisterFileReadData2.do_highlight = bool(csignals.mem_write) - result.DataMemoryWriteDataText.text = ( - save_to_str(pr.memory_write_data) - if result.MemoryRegisterFileReadData2.do_highlight - else "" + result.DataMemoryWriteDataText.text = save_to_str( + pr.memory_write_data, result.MemoryRegisterFileReadData2.do_highlight ) result.DataMemoryReadDataText.text = save_to_str(pr.memory_read_data) @@ -520,15 +511,13 @@ def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, An result.MemoryExecuteAddOut.do_highlight = result.MemoryJumpOut.do_highlight result.MemoryFetchAddOut.do_highlight = csignals.wb_src == 0 - result.MemoryFetchAddOutText.text = ( - save_to_str(pr.pc_plus_instruction_length) - if result.MemoryFetchAddOut.do_highlight - else "" + result.MemoryFetchAddOutText.text = save_to_str( + pr.pc_plus_instruction_length, result.MemoryFetchAddOut.do_highlight ) result.MemoryImmGen.do_highlight = csignals.wb_src == 3 - result.MemoryImmGenText.text = ( - save_to_str(pr.imm) if result.MemoryImmGen.do_highlight else "" + result.MemoryImmGenText.text = save_to_str( + pr.imm, result.MemoryImmGen.do_highlight ) result.ControlUnitLeftRight1_3.do_highlight = bool(csignals.jump) @@ -546,10 +535,8 @@ def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, An or result.MemoryExecuteAluResultToFetchMux.do_highlight ) result.MemoryExecuteAluResultToWbMux.do_highlight = csignals.wb_src == 2 - result.MemoryExecuteAluResultText2.text = ( - save_to_str(pr.result) - if result.MemoryExecuteAluResultToWbMux.do_highlight - else "" + result.MemoryExecuteAluResultText2.text = save_to_str( + pr.result, result.MemoryExecuteAluResultToWbMux.do_highlight ) result.ControlUnitRegWriteEnable_3 = bool(csignals.reg_write) From 3a275dce87942f859ca8d3efe12853a5126884fd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Thu, 18 Apr 2024 16:43:59 +0200 Subject: [PATCH 028/138] Moved things around to save horizontal space --- webgui/src/img/riscv_five_stage_pipeline.svg | 178 ++++++++++--------- 1 file changed, 93 insertions(+), 85 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 2e24691..2d1e258 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -2,9 +2,9 @@ MuxMux11223300Data MemoryWrite DataRead DataAddress Date: Thu, 18 Apr 2024 16:55:30 +0200 Subject: [PATCH 029/138] Made the svg a bit smaller again --- webgui/src/img/riscv_five_stage_pipeline.svg | 110 +++++++++---------- 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 2d1e258..cfe2bfe 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -2,9 +2,9 @@ MuxMux1100MuxMux1100Instruction MemoryRead AddressInstr[31-0]PC + transform="translate(-111.69115,-14.215385)" /> From 364da758174cf0c32acfddb4ac9c9d281db89a22 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Mon, 22 Apr 2024 08:56:29 +0200 Subject: [PATCH 030/138] Fixed some SVG signals --- .../simulation/riscv_simulation.py | 20 ++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index 58e5335..7984d61 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -362,7 +362,7 @@ def _get_riscv_five_stage_ID_svg_update_values(self) -> list[tuple[str, str, Any pr.instruction, EmptyInstruction ) result.ControlUnitLeftRight1_1.do_highlight = bool(csignals.jump) - result.ControlUnitLeftRight2_1.do_highlight = bool(csignals.wb_src) + result.ControlUnitLeftRight2_1.do_highlight = csignals.wb_src is not None result.ControlUnitLeftRight3_1.do_highlight = bool(csignals.alu_src_1) result.ControlUnitLeftRight4_1.do_highlight = bool(csignals.alu_src_2) result.ControlUnitLeft_1.do_highlight = bool(csignals.alu_to_pc) @@ -424,7 +424,7 @@ def _get_riscv_five_stage_EX_svg_update_values(self) -> list[tuple[str, str, Any result.ALUComparison.do_highlight = bool(pr.comparison) result.ControlUnitLeftRight1_2.do_highlight = bool(csignals.jump) - result.ControlUnitLeftRight2_2.do_highlight = bool(csignals.wb_src) + result.ControlUnitLeftRight2_2.do_highlight = csignals.wb_src is not None result.ControlUnitLeftRight3_2.do_highlight = bool(csignals.alu_src_1) result.ControlUnitLeftRight4_2.do_highlight = bool(csignals.alu_src_2) result.ControlUnitLeft_2.do_highlight = bool(csignals.alu_to_pc) @@ -485,7 +485,6 @@ def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, An if isinstance(pr, MemoryAccessPipelineRegister): csignals = pr.control_unit_signals - result.DataMemoryAddressText.text = save_to_str(pr.memory_address) result.MemoryExecuteAluResult.do_highlight = pr.result is not None @@ -521,12 +520,15 @@ def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, An ) result.ControlUnitLeftRight1_3.do_highlight = bool(csignals.jump) - result.ControlUnitLeftRight2_3.do_highlight = bool(csignals.wb_src) + result.ControlUnitLeftRight2_3.do_highlight = csignals.wb_src is not None result.ControlUnitLeft_3.do_highlight = bool(csignals.alu_to_pc) result.MemoryExecuteAluResultToMemory.do_highlight = bool( csignals.mem_read ) or bool(csignals.mem_write) + result.DataMemoryAddressText.text = save_to_str( + pr.memory_address, result.MemoryExecuteAluResultToMemory.do_highlight + ) result.MemoryExecuteAluResultToFetchMux.do_highlight = ( csignals.alu_to_pc is True ) @@ -539,9 +541,9 @@ def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, An pr.result, result.MemoryExecuteAluResultToWbMux.do_highlight ) - result.ControlUnitRegWriteEnable_3 = bool(csignals.reg_write) - result.ControlUnitMemReadEnable_3 = bool(csignals.mem_read) - result.ControlUnitMemWriteEnable_3 = bool(csignals.mem_write) + result.ControlUnitRegWriteEnable_3.do_highlight = bool(csignals.reg_write) + result.ControlUnitMemReadEnable_3.do_highlight = bool(csignals.mem_read) + result.ControlUnitMemWriteEnable_3.do_highlight = bool(csignals.mem_write) return result.export() def _get_riscv_five_stage_WB_svg_update_values(self) -> list[tuple[str, str, Any]]: @@ -576,8 +578,8 @@ def _get_riscv_five_stage_WB_svg_update_values(self) -> list[tuple[str, str, Any result.WriteBackImmGen.do_highlight = pr.control_unit_signals.wb_src == 3 result.wbsrc.text = save_to_str(pr.control_unit_signals.wb_src) - result.ControlUnitLeftRight2_4.do_highlight = bool( - pr.control_unit_signals.wb_src + result.ControlUnitLeftRight2_4.do_highlight = ( + pr.control_unit_signals.wb_src is not None ) result.ControlUnitRegWriteEnable_4.do_highlight = ( From 155b2cc82cc88043309541940c20dfa3cf7ed691 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Mon, 22 Apr 2024 08:59:06 +0200 Subject: [PATCH 031/138] Refactored a bit --- .../simulation/riscv_simulation.py | 20 ++++++------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index 7984d61..374f57c 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -567,24 +567,16 @@ def _get_riscv_five_stage_WB_svg_update_values(self) -> list[tuple[str, str, Any result.WriteBackDataMemoryReadData.do_highlight = csignals.wb_src == 1 - result.WriteBackExecuteAluResult.do_highlight = ( - pr.control_unit_signals.wb_src == 2 - ) + result.WriteBackExecuteAluResult.do_highlight = csignals.wb_src == 2 - result.WriteBackFetchAddOut.do_highlight = ( - pr.control_unit_signals.wb_src == 0 - ) + result.WriteBackFetchAddOut.do_highlight = csignals.wb_src == 0 - result.WriteBackImmGen.do_highlight = pr.control_unit_signals.wb_src == 3 + result.WriteBackImmGen.do_highlight = csignals.wb_src == 3 - result.wbsrc.text = save_to_str(pr.control_unit_signals.wb_src) - result.ControlUnitLeftRight2_4.do_highlight = ( - pr.control_unit_signals.wb_src is not None - ) + result.wbsrc.text = save_to_str(csignals.wb_src) + result.ControlUnitLeftRight2_4.do_highlight = csignals.wb_src is not None - result.ControlUnitRegWriteEnable_4.do_highlight = ( - pr.control_unit_signals.reg_write is True - ) + result.ControlUnitRegWriteEnable_4.do_highlight = csignals.reg_write is True return result.export() def _get_riscv_five_stage_OTHER_svg_update_values( From 072622fe46aee067b37bbfc027052115293b1bd6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Mon, 22 Apr 2024 10:09:25 +0200 Subject: [PATCH 032/138] Fixed the remaining SVG signals --- architecture_simulator/uarch/riscv/stages.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/architecture_simulator/uarch/riscv/stages.py b/architecture_simulator/uarch/riscv/stages.py index afca488..f22a369 100644 --- a/architecture_simulator/uarch/riscv/stages.py +++ b/architecture_simulator/uarch/riscv/stages.py @@ -216,10 +216,14 @@ def behavior( return ExecutePipelineRegister() alu_in_1 = ( - pipeline_register.register_read_data_1 - if pipeline_register.control_unit_signals.alu_src_1 - else pipeline_register.address_of_instruction - ) + None + if pipeline_register.control_unit_signals.alu_src_1 is None + else ( + pipeline_register.register_read_data_1 + if pipeline_register.control_unit_signals.alu_src_1 + else pipeline_register.address_of_instruction + ) + ) # check if alu_src_1 is None because address_of_instruction always exists and might cause problems in the visualization alu_in_2 = ( pipeline_register.imm if pipeline_register.control_unit_signals.alu_src_2 From 39483cb05e9f03d29f276239bd5c4a11e2bc9ae8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Mon, 22 Apr 2024 10:25:54 +0200 Subject: [PATCH 033/138] Made 5-stage markers a bit bigger --- build_svg.py | 14 +++++++------- webgui/src/img/riscv_five_stage_pipeline.svg | 18 +++++++++--------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/build_svg.py b/build_svg.py index 5f5eb46..332457e 100644 --- a/build_svg.py +++ b/build_svg.py @@ -9,7 +9,7 @@ orient="auto-start-reverse" inkscape:stockid="TriangleStart" markerWidth="2" - markerHeight="2" + markerHeight="2.5" viewBox="0 0 5.3244081 6.1553851" inkscape:isstock="true" inkscape:collect="always" @@ -26,7 +26,7 @@ orient="auto-start-reverse" inkscape:stockid="TriangleStart" markerWidth="2" - markerHeight="2" + markerHeight="2.5" viewBox="0 0 5.3244081 6.1553851" inkscape:isstock="true" inkscape:collect="always" @@ -43,7 +43,7 @@ orient="auto-start-reverse" inkscape:stockid="TriangleStart" markerWidth="2" - markerHeight="2" + markerHeight="2.5" viewBox="0 0 5.3244081 6.1553851" inkscape:isstock="true" inkscape:collect="always" @@ -59,8 +59,8 @@ refY="0" orient="auto" inkscape:stockid="Dot" - markerWidth="2" - markerHeight="2" + markerWidth="2.5" + markerHeight="2.5" viewBox="0 0 5.6666667 5.6666667" inkscape:isstock="true" inkscape:collect="always" @@ -77,8 +77,8 @@ refY="0" orient="auto" inkscape:stockid="Dot" - markerWidth="2" - markerHeight="2" + markerWidth="2.5" + markerHeight="2.5" viewBox="0 0 5.6666667 5.6666667" inkscape:isstock="true" inkscape:collect="always" diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index cfe2bfe..5ee88a4 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -26,8 +26,8 @@ inkscape:document-units="mm" showgrid="false" inkscape:zoom="0.70710678" - inkscape:cx="508.40978" - inkscape:cy="1931.8157" + inkscape:cx="509.82399" + inkscape:cy="1930.4015" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -52,7 +52,7 @@ orient="auto-start-reverse" inkscape:stockid="TriangleStart" markerWidth="2" - markerHeight="2" + markerHeight="2.5" viewBox="0 0 5.3244081 6.1553851" inkscape:isstock="true" inkscape:collect="always" @@ -69,7 +69,7 @@ orient="auto-start-reverse" inkscape:stockid="TriangleStart" markerWidth="2" - markerHeight="2" + markerHeight="2.5" viewBox="0 0 5.3244081 6.1553851" inkscape:isstock="true" inkscape:collect="always" @@ -86,7 +86,7 @@ orient="auto-start-reverse" inkscape:stockid="TriangleStart" markerWidth="2" - markerHeight="2" + markerHeight="2.5" viewBox="0 0 5.3244081 6.1553851" inkscape:isstock="true" inkscape:collect="always" @@ -102,8 +102,8 @@ refY="0" orient="auto" inkscape:stockid="Dot" - markerWidth="2" - markerHeight="2" + markerWidth="2.5" + markerHeight="2.5" viewBox="0 0 5.6666667 5.6666667" inkscape:isstock="true" inkscape:collect="always" @@ -120,8 +120,8 @@ refY="0" orient="auto" inkscape:stockid="Dot" - markerWidth="2" - markerHeight="2" + markerWidth="2.5" + markerHeight="2.5" viewBox="0 0 5.6666667 5.6666667" inkscape:isstock="true" inkscape:collect="always" From a017b60f5fd84e04de9f17b49258f4fda6b97483 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Mon, 22 Apr 2024 10:31:00 +0200 Subject: [PATCH 034/138] Made 5-stage control signals a bit thicker --- webgui/src/img/riscv_five_stage_pipeline.svg | 54 ++++++++++---------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 5ee88a4..02cacad 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -26,8 +26,8 @@ inkscape:document-units="mm" showgrid="false" inkscape:zoom="0.70710678" - inkscape:cx="509.82399" - inkscape:cy="1930.4015" + inkscape:cx="5534.5248" + inkscape:cy="3000.9612" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -214,20 +214,20 @@ style="display:inline;fill:#8fbfe0;fill-opacity:1;stroke-width:0.448263" inkscape:label="Instruction Memory" d="m 1534.4259,14.935 h 14.838 V 1080 h -14.838 z" /> Date: Mon, 22 Apr 2024 11:29:18 +0200 Subject: [PATCH 035/138] Changed some path widths and colors --- .../gui/riscv_fiveStage_svg_directives.py | 10 +++++----- webgui/src/img/riscv_five_stage_pipeline.svg | 20 +++++++++---------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py index 871a5a0..5c4b2fb 100644 --- a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py +++ b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py @@ -61,7 +61,7 @@ def __init__(self): self.DecodeLowerFetchPCOut = SvgFillDirectiveBlue() self.DecodeInstructionMemory = SvgFillDirectiveBlue() self.ControlUnitLeftRight1_1 = SvgFillDirectiveGreen() - self.ControlUnitLeftRight2_1 = SvgFillDirectiveBlue() + self.ControlUnitLeftRight2_1 = SvgFillDirectiveGreen() self.ControlUnitLeftRight3_1 = SvgFillDirectiveGreen() self.ControlUnitLeftRight4_1 = SvgFillDirectiveGreen() self.ControlUnitLeft_1 = SvgFillDirectiveGreen() @@ -97,11 +97,11 @@ def __init__(self): self.ExecuteLowerFetchPCOut = SvgFillDirectiveBlue() self.ALUComparison = SvgFillDirectiveGreen() self.ControlUnitLeftRight1_2 = SvgFillDirectiveGreen() - self.ControlUnitLeftRight2_2 = SvgFillDirectiveBlue() + self.ControlUnitLeftRight2_2 = SvgFillDirectiveGreen() self.ControlUnitLeftRight3_2 = SvgFillDirectiveGreen() self.ControlUnitLeftRight4_2 = SvgFillDirectiveGreen() self.ControlUnitLeft_2 = SvgFillDirectiveGreen() - self.AluControl = SvgFillDirectiveBlue() + self.AluControl = SvgFillDirectiveGreen() self.ExecuteImmediateToAdder = SvgFillDirectiveBlue() self.ExecuteImmediateToMux = SvgFillDirectiveBlue() self.ExecuteImmediateInterediate = SvgFillDirectiveBlue() @@ -133,7 +133,7 @@ def __init__(self): self.MemoryImmGenText = SvgWriteCenterDirective() self.MemoryImmGen = SvgFillDirectiveBlue() self.ControlUnitLeftRight1_3 = SvgFillDirectiveGreen() - self.ControlUnitLeftRight2_3 = SvgFillDirectiveBlue() + self.ControlUnitLeftRight2_3 = SvgFillDirectiveGreen() self.ControlUnitLeft_3 = SvgFillDirectiveGreen() self.MemoryExecuteAluResultToMemory = SvgFillDirectiveBlue() self.MemoryExecuteAluResultToFetchMux = SvgFillDirectiveBlue() @@ -156,7 +156,7 @@ def __init__(self): self.WriteBackFetchAddOut = SvgFillDirectiveBlue() self.WriteBackImmGen = SvgFillDirectiveBlue() self.wbsrc = SvgWriteCenterDirective() - self.ControlUnitLeftRight2_4 = SvgFillDirectiveBlue() + self.ControlUnitLeftRight2_4 = SvgFillDirectiveGreen() self.ControlUnitRegWriteEnable_4 = SvgFillDirectiveGreen() diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 02cacad..120a176 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.70710678" - inkscape:cx="5534.5248" - inkscape:cy="3000.9612" + inkscape:zoom="0.1767767" + inkscape:cx="2621.9519" + inkscape:cy="2076.0655" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -249,8 +249,8 @@ d="m 1603.0182,898.52528 -34.8019,3.6e-4 v -539.9765 l -18.9524,-1e-5" id="WriteBackFetchAddOut" sodipodi:nodetypes="cccc" /> Date: Tue, 23 Apr 2024 13:47:28 +0200 Subject: [PATCH 036/138] Changed the SVG --- webgui/src/img/riscv_five_stage_pipeline.svg | 1201 +++++++++--------- 1 file changed, 575 insertions(+), 626 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 120a176..045f252 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.1767767" - inkscape:cx="2621.9519" - inkscape:cy="2076.0655" + inkscape:zoom="0.25000001" + inkscape:cx="2145.9999" + inkscape:cy="1279.9999" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -61,40 +61,8 @@ style="fill:#000000;fill-rule:evenodd;stroke:#000000;stroke-width:1pt" d="M 5.77,0 -2.88,5 V -5 Z" id="000000_ArchsimMarker_Triangle_Path" /> - - + + - + Mux10Mux1010Mux1230Instruction Instruction MemoryPCRegister FileRegister FileData MemoryData MemoryWrite DataWrite DataAddressAddressControlUnitControlUnitImm GenALUControlMux10Mux10AddAddComparisonALUResultAddwbsrc010101010101101010101010110101010101PC1010101010ALUResult1010101010110101010101Imm Gen101010101010101010123ComparisonMemWriteMemReadRegWriteAdd Date: Tue, 23 Apr 2024 13:58:06 +0200 Subject: [PATCH 037/138] Changed the color of control unit signals --- .../gui/riscv_fiveStage_svg_directives.py | 2 +- build_svg.py | 6 +- webgui/src/img/riscv_five_stage_pipeline.svg | 55 ++++++++++++++++++- 3 files changed, 56 insertions(+), 7 deletions(-) diff --git a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py index 5c4b2fb..d0ef500 100644 --- a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py +++ b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py @@ -178,7 +178,7 @@ class SvgFillDirectiveGreen(SvgFillDirective): """SVG Fill Directive: highlight: green, default: black""" def __init__(self): - super().__init__(color_on="#008000", color_off="#000000") + super().__init__(color_on="#A51E37", color_off="#000000") class SvgWriteLeftDirective(SvgDirective): diff --git a/build_svg.py b/build_svg.py index 332457e..3d031de 100644 --- a/build_svg.py +++ b/build_svg.py @@ -20,7 +20,7 @@ id="000000_ArchsimMarker_Triangle_Path" /> + id="A51E37_ArchsimMarker_Triangle_Path" /> - - + + - + Date: Tue, 23 Apr 2024 14:13:19 +0200 Subject: [PATCH 038/138] Added directives for the new signals --- .../gui/riscv_fiveStage_svg_directives.py | 7 ++++++- .../simulation/riscv_simulation.py | 20 +++++++++++++++++-- 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py index d0ef500..5f954c8 100644 --- a/architecture_simulator/gui/riscv_fiveStage_svg_directives.py +++ b/architecture_simulator/gui/riscv_fiveStage_svg_directives.py @@ -65,10 +65,13 @@ def __init__(self): self.ControlUnitLeftRight3_1 = SvgFillDirectiveGreen() self.ControlUnitLeftRight4_1 = SvgFillDirectiveGreen() self.ControlUnitLeft_1 = SvgFillDirectiveGreen() - self.DecodeInstructionMemoryIntermediate = SvgFillDirectiveBlue() + self.DecodeInstructionMemoryIntermediate1 = SvgFillDirectiveBlue() + self.DecodeInstructionMemoryIntermediate2 = SvgFillDirectiveBlue() self.ControlUnitRegWriteEnable_1 = SvgFillDirectiveGreen() self.ControlUnitMemWriteEnable_1 = SvgFillDirectiveGreen() self.ControlUnitMemReadEnable_1 = SvgFillDirectiveGreen() + self.DecodeInstructionMemoryToAluCtl = SvgFillDirectiveBlue() + self.ControlUnitAluOp_1 = SvgFillDirectiveGreen() class RiscvFiveStageEXSvgDirectives(RiscvSvgDirectivesBase): @@ -111,6 +114,8 @@ def __init__(self): self.ControlUnitMemWriteEnable_2 = SvgFillDirectiveGreen() self.ControlUnitMemReadEnable_2 = SvgFillDirectiveGreen() self.ExecuteImmediateToWbMux = SvgFillDirectiveBlue() + self.ExecuteInstructionMemoryToAluCtl = SvgFillDirectiveBlue() + self.ControlUnitAluOp_2 = SvgFillDirectiveGreen() class RiscvFiveStageMEMSvgDirectives(RiscvSvgDirectivesBase): diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index 374f57c..9666141 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -370,9 +370,20 @@ def _get_riscv_five_stage_ID_svg_update_values(self) -> list[tuple[str, str, Any result.ControlUnitMemWriteEnable_1.do_highlight = bool(csignals.mem_write) result.ControlUnitMemReadEnable_1.do_highlight = bool(csignals.mem_read) - result.DecodeInstructionMemoryIntermediate.do_highlight = bool( + result.DecodeInstructionMemoryToAluCtl.do_highlight = ( + csignals.alu_op is not None + ) + result.ControlUnitAluOp_1.do_highlight = csignals.alu_op is not None + + result.DecodeInstructionMemoryIntermediate1.do_highlight = ( + bool(csignals.reg_write) + or (pr.imm is not None) + or csignals.alu_op is not None + ) + + result.DecodeInstructionMemoryIntermediate2.do_highlight = bool( csignals.reg_write - ) | (pr.imm is not None) + ) or (pr.imm is not None) return result.export() @@ -474,6 +485,11 @@ def _get_riscv_five_stage_EX_svg_update_values(self) -> list[tuple[str, str, Any result.ControlUnitMemWriteEnable_2.do_highlight = bool(csignals.mem_write) result.ControlUnitMemReadEnable_2.do_highlight = bool(csignals.mem_read) + result.ExecuteInstructionMemoryToAluCtl.do_highlight = ( + csignals.alu_op is not None + ) + result.ControlUnitAluOp_2.do_highlight = csignals.alu_op is not None + return result.export() def _get_riscv_five_stage_MEM_svg_update_values(self) -> list[tuple[str, str, Any]]: From 4823123530cd4a5c403cf8dea09edc1c5ad60db5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Tue, 23 Apr 2024 14:17:29 +0200 Subject: [PATCH 039/138] Small svg changes/fixes --- webgui/src/img/riscv_five_stage_pipeline.svg | 26 ++++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 0fa91c8..8276eba 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.25000001" - inkscape:cx="2145.9999" - inkscape:cy="1279.9999" + inkscape:zoom="0.70710681" + inkscape:cx="4507.8056" + inkscape:cy="2360.3223" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -185,12 +185,12 @@ d="m 950.41815,836.92693 -55.38592,-3.1e-4" sodipodi:nodetypes="cc" />3ComparisonMemWriteMemReadRegWrite Date: Mon, 15 Apr 2024 12:36:10 +0200 Subject: [PATCH 040/138] add unedited new single stage svg --- .../src/img/riscv_single_stage_pipeline.svg | 602 ++++--- .../img/riscv_single_stage_pipeline.svg.old | 1415 +++++++++++++++++ 2 files changed, 1715 insertions(+), 302 deletions(-) mode change 100644 => 100755 webgui/src/img/riscv_single_stage_pipeline.svg create mode 100644 webgui/src/img/riscv_single_stage_pipeline.svg.old diff --git a/webgui/src/img/riscv_single_stage_pipeline.svg b/webgui/src/img/riscv_single_stage_pipeline.svg old mode 100644 new mode 100755 index 32d416e..c133047 --- a/webgui/src/img/riscv_single_stage_pipeline.svg +++ b/webgui/src/img/riscv_single_stage_pipeline.svg @@ -8,7 +8,7 @@ version="1.1" id="svg5" xml:space="preserve" - inkscape:version="1.2.2 (b0a8486541, 2022-12-01)" + inkscape:version="1.3.2 (091e20e, 2023-11-25, custom)" sodipodi:docname="riscv_single_stage_pipeline.svg" xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" @@ -24,13 +24,13 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="true" - inkscape:zoom="0.16" - inkscape:cx="2031.25" - inkscape:cy="1668.75" - inkscape:window-width="1920" - inkscape:window-height="1007" - inkscape:window-x="0" - inkscape:window-y="0" + inkscape:zoom="1" + inkscape:cx="3177" + inkscape:cy="2858.5" + inkscape:window-width="2560" + inkscape:window-height="1377" + inkscape:window-x="1912" + inkscape:window-y="-8" inkscape:window-maximized="1" inkscape:current-layer="layer6" showguides="true" @@ -53,110 +53,44 @@ id="defs2"> - - - - + style="overflow:visible" + id="000000_ArchsimMarker_Dot" + refX="0" + refY="0" + orient="auto" + inkscape:stockid="Dot" + markerWidth="0.40000001" + markerHeight="0.40000001" + viewBox="0 0 1 1" + inkscape:isstock="true" + inkscape:collect="always" + preserveAspectRatio="xMidYMid"> + + + style="overflow:visible" + id="000000_ArchsimMarker_Triangle_Reversed" + refX="0" + refY="0" + orient="auto-start-reverse" + inkscape:stockid="Triangle arrow" + markerWidth="0.40000001" + markerHeight="0.40000001" + viewBox="0 0 1 1" + inkscape:isstock="true" + inkscape:collect="always" + preserveAspectRatio="xMidYMid"> + + Instr[31-0]PCRead Addr 1AddressUnitImm GenControlAdd01Mux01MuxAdd01Mux01Mux01Mux2233 + + + + + + + + + + + + Instruction MemoryRead AddressInstr[31-0]PC10101010Register FileWrite DataWrite RegisterReadData 1ReadData 2Read Addr 2Read Addr 1Data MemoryWrite DataRead DataAddressControlUnitImm GenALUControlAddComparisonALUResult1010101010110101010101101010101010101010101010101010101101010101011010101010110101010101010101010110101010101101010101011010101010101Mux01MuxAdd01Mux01Mux01Mux231010101010110101010101010101010 From 09ac2a016a259c9782249f6fe80d415c39b90e81 Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Mon, 15 Apr 2024 13:59:19 +0200 Subject: [PATCH 041/138] update build_svg --- build_svg.py | 224 +-- .../src/img/riscv_single_stage_pipeline.svg | 116 +- .../img/riscv_single_stage_pipeline.svg.old | 1415 ----------------- 3 files changed, 199 insertions(+), 1556 deletions(-) delete mode 100644 webgui/src/img/riscv_single_stage_pipeline.svg.old diff --git a/build_svg.py b/build_svg.py index 3d031de..ca70d49 100644 --- a/build_svg.py +++ b/build_svg.py @@ -91,112 +91,124 @@ """ riscv_single_stage_markers = """ - - - - - - - """ + + + + + + + + + + + + + + + + + + +""" if __name__ == "__main__": for filename, markers in [ diff --git a/webgui/src/img/riscv_single_stage_pipeline.svg b/webgui/src/img/riscv_single_stage_pipeline.svg index c133047..33eb7b3 100755 --- a/webgui/src/img/riscv_single_stage_pipeline.svg +++ b/webgui/src/img/riscv_single_stage_pipeline.svg @@ -52,7 +52,7 @@ visible="true" /> - + id="path78" /> + + + - + + + + - + id="path135" /> + - - + + + + + + - - - - - - - - - - - - Instruction MemoryRead AddressInstr[31-0]PC10101010Register FileWrite DataWrite RegisterReadData 1ReadData 2Read Addr 2Read Addr 1Data MemoryWrite DataRead DataAddressControlUnitImm GenALUControlAddComparisonALUResult1010101010110101010101101010101010101010101010101010101101010101011010101010110101010101010101010110101010101101010101011010101010101Mux01MuxAdd01Mux01Mux01Mux231010101010110101010101010101010 From cb819d1f51f9ebb6af19aec48383bede30e686a4 Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Mon, 15 Apr 2024 14:26:19 +0200 Subject: [PATCH 042/138] update svg directives, ... to include new signals --- .../gui/riscv_single_stage_svg_directives.py | 17 ++++++++++++-- .../simulation/riscv_simulation.py | 22 ++++++++++++++++--- .../uarch/riscv/control_unit_signals.py | 4 ++++ architecture_simulator/uarch/riscv/stages.py | 9 ++++++++ 4 files changed, 47 insertions(+), 5 deletions(-) diff --git a/architecture_simulator/gui/riscv_single_stage_svg_directives.py b/architecture_simulator/gui/riscv_single_stage_svg_directives.py index 934b781..2846de1 100644 --- a/architecture_simulator/gui/riscv_single_stage_svg_directives.py +++ b/architecture_simulator/gui/riscv_single_stage_svg_directives.py @@ -45,6 +45,15 @@ def __init__(self) -> None: self.alu_control_to_read_data_1_mux_path: SvgFillDirectiveGreen = ( SvgFillDirectiveGreen() ) + self.control_unit_write_data_path: SvgFillDirectiveGreen = ( + SvgFillDirectiveGreen() + ) + self.control_unit_read_data_path: SvgFillDirectiveGreen = ( + SvgFillDirectiveGreen() + ) + self.control_unit_to_reg_file_path: SvgFillDirectiveGreen = ( + SvgFillDirectiveGreen() + ) # Non Binary signals self.control_unit_to_4mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() @@ -68,7 +77,8 @@ def __init__(self) -> None: self.imm_gen_out_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.imm_gen_to_add_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.imm_gen_to_4mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() - self.imm_gen_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() + self.imm_gen_joint_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() + self.imm_gen_to_joint_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.read_data2_to_mem_write_data_path: SvgFillDirectiveBlue = ( SvgFillDirectiveBlue() @@ -76,7 +86,10 @@ def __init__(self) -> None: self.read_data_1_mux_to_alu_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.read_data_1_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.read_data_2_2mux_to_alu_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() - self.read_data_2_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() + self.read_data_2_joint_to_2mux_path: SvgFillDirectiveBlue = ( + SvgFillDirectiveBlue() + ) + self.read_data_2_to_joint_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.alu_out_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.alu_out_to_4mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index 9666141..d2e5c04 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -688,6 +688,15 @@ def get_riscv_single_stage_svg_update_values(self) -> list[tuple[str, str, Any]] result.alu_control_to_read_data_1_mux_path.do_highlight = ( p_reg.control_unit_signals.alu_src_1 is not None ) and (not p_reg.control_unit_signals.alu_src_1) + result.control_unit_write_data_path.do_highlight = bool( + p_reg.control_unit_signals.mem_write + ) + result.control_unit_read_data_path.do_highlight = bool( + p_reg.control_unit_signals.mem_read + ) + result.control_unit_to_reg_file_path.do_highlight = bool( + p_reg.control_unit_signals.reg_write + ) # Non Binary signals @@ -729,9 +738,12 @@ def get_riscv_single_stage_svg_update_values(self) -> list[tuple[str, str, Any]] result.imm_gen_to_4mux_path.do_highlight = ( p_reg.control_unit_signals.wb_src_int == 3 ) - result.imm_gen_to_2mux_path.do_highlight = ( + result.imm_gen_joint_to_2mux_path.do_highlight = ( p_reg.control_unit_signals.alu_src_2 - or result.pc_to_add_imm_path.do_highlight + ) + result.imm_gen_to_joint_path.do_highlight = ( + result.imm_gen_joint_to_2mux_path.do_highlight + or result.imm_gen_to_add_path.do_highlight ) result.read_data2_to_mem_write_data_path.do_highlight = bool( @@ -746,7 +758,11 @@ def get_riscv_single_stage_svg_update_values(self) -> list[tuple[str, str, Any]] result.read_data_2_2mux_to_alu_path.do_highlight = not ( p_reg.control_unit_signals.alu_src_2 is None ) - result.read_data_2_to_2mux_path.do_highlight = bool( + result.read_data_2_joint_to_2mux_path.do_highlight = bool( + result.reg_file_read_data_2_text.text + and (not result.alu_control_to_read_data_2mux_path.do_highlight) + ) + result.read_data_2_to_joint_path.do_highlight = bool( result.reg_file_read_data_2_text.text ) diff --git a/architecture_simulator/uarch/riscv/control_unit_signals.py b/architecture_simulator/uarch/riscv/control_unit_signals.py index dafabe9..bbacfbd 100644 --- a/architecture_simulator/uarch/riscv/control_unit_signals.py +++ b/architecture_simulator/uarch/riscv/control_unit_signals.py @@ -37,3 +37,7 @@ class SingleStageControlUnitSignals: jump: bool = False # False if no jump instruction (jal) is selected pc_from_alu_res: bool = False # True if the alu result is used as new pc -> needs inversion for highlighting of control unit path + + reg_write: Optional[bool] = None + mem_read: Optional[bool] = None + mem_write: Optional[bool] = None diff --git a/architecture_simulator/uarch/riscv/stages.py b/architecture_simulator/uarch/riscv/stages.py index f22a369..f6e4dcf 100644 --- a/architecture_simulator/uarch/riscv/stages.py +++ b/architecture_simulator/uarch/riscv/stages.py @@ -485,6 +485,15 @@ def behavior( result_pr.control_unit_signals.pc_from_alu_res = ( result_pr.instruction.mnemonic == "jalr" ) + result_pr.control_unit_signals.reg_write = ( + five_stage_control_unit_signals.reg_write + ) + result_pr.control_unit_signals.mem_read = ( + five_stage_control_unit_signals.mem_read + ) + result_pr.control_unit_signals.mem_write = ( + five_stage_control_unit_signals.mem_write + ) ( result_pr.register_read_addr_1, From eaeedb4ad5550c5dd12255b3bd993f38871dca53 Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Mon, 15 Apr 2024 20:27:16 +0200 Subject: [PATCH 043/138] fix svg ids --- .../simulation/riscv_simulation.py | 2 +- webgui/src/img/riscv_single_stage_pipeline.svg | 14 +++++++------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index d2e5c04..a86b2f9 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -738,7 +738,7 @@ def get_riscv_single_stage_svg_update_values(self) -> list[tuple[str, str, Any]] result.imm_gen_to_4mux_path.do_highlight = ( p_reg.control_unit_signals.wb_src_int == 3 ) - result.imm_gen_joint_to_2mux_path.do_highlight = ( + result.imm_gen_joint_to_2mux_path.do_highlight = bool( p_reg.control_unit_signals.alu_src_2 ) result.imm_gen_to_joint_path.do_highlight = ( diff --git a/webgui/src/img/riscv_single_stage_pipeline.svg b/webgui/src/img/riscv_single_stage_pipeline.svg index 33eb7b3..b60cba6 100755 --- a/webgui/src/img/riscv_single_stage_pipeline.svg +++ b/webgui/src/img/riscv_single_stage_pipeline.svg @@ -208,7 +208,7 @@ inkscape:label="alu-control-to-alu-path" /> Date: Mon, 15 Apr 2024 21:00:56 +0200 Subject: [PATCH 044/138] fix wb text bug --- architecture_simulator/uarch/riscv/stages.py | 23 ++++++++++--------- .../src/img/riscv_single_stage_pipeline.svg | 14 +++++------ 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/architecture_simulator/uarch/riscv/stages.py b/architecture_simulator/uarch/riscv/stages.py index f6e4dcf..8609146 100644 --- a/architecture_simulator/uarch/riscv/stages.py +++ b/architecture_simulator/uarch/riscv/stages.py @@ -544,17 +544,6 @@ def behavior( else None ) - result_pr.register_write_data = defaultdict( - lambda: None, - { - None: None, # to stop mypy complaining - 0: result_pr.pc_plus_instruction_length, - 1: result_pr.memory_read_data, - 2: result_pr.alu_result, - 3: result_pr.imm, - }, - )[five_stage_control_unit_signals.wb_src] - try: result_pr.instruction.behavior(state) result_pr.memory_read_data = ( @@ -564,6 +553,18 @@ def behavior( if type(result_pr.instruction) in SingleStage.TYPE_LOAD_INSTRUCTION else None ) + + result_pr.register_write_data = defaultdict( + lambda: None, + { + None: None, # to stop mypy complaining + 0: result_pr.pc_plus_instruction_length, + 1: result_pr.memory_read_data, + 2: result_pr.alu_result, + 3: result_pr.imm, + }, + )[five_stage_control_unit_signals.wb_src] + state.program_counter += result_pr.instruction.length if ( not type(result_pr.instruction) diff --git a/webgui/src/img/riscv_single_stage_pipeline.svg b/webgui/src/img/riscv_single_stage_pipeline.svg index b60cba6..d6a590a 100755 --- a/webgui/src/img/riscv_single_stage_pipeline.svg +++ b/webgui/src/img/riscv_single_stage_pipeline.svg @@ -25,8 +25,8 @@ inkscape:document-units="mm" showgrid="true" inkscape:zoom="1" - inkscape:cx="3177" - inkscape:cy="2858.5" + inkscape:cx="3497" + inkscape:cy="1498.5" inkscape:window-width="2560" inkscape:window-height="1377" inkscape:window-x="1912" @@ -196,6 +196,11 @@ inkscape:label="canvas" style="display:inline" transform="translate(-67.500005,27.499998)"> Date: Mon, 15 Apr 2024 21:04:16 +0200 Subject: [PATCH 045/138] lower two signals to bottom --- .../src/img/riscv_single_stage_pipeline.svg | 34 +++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/webgui/src/img/riscv_single_stage_pipeline.svg b/webgui/src/img/riscv_single_stage_pipeline.svg index d6a590a..308efba 100755 --- a/webgui/src/img/riscv_single_stage_pipeline.svg +++ b/webgui/src/img/riscv_single_stage_pipeline.svg @@ -24,13 +24,13 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="true" - inkscape:zoom="1" - inkscape:cx="3497" - inkscape:cy="1498.5" - inkscape:window-width="2560" - inkscape:window-height="1377" - inkscape:window-x="1912" - inkscape:window-y="-8" + inkscape:zoom="0.70710678" + inkscape:cx="3175.6166" + inkscape:cy="1788.273" + inkscape:window-width="1920" + inkscape:window-height="1017" + inkscape:window-x="-8" + inkscape:window-y="341" inkscape:window-maximized="1" inkscape:current-layer="layer6" showguides="true" @@ -196,6 +196,16 @@ inkscape:label="canvas" style="display:inline" transform="translate(-67.500005,27.499998)"> Date: Mon, 22 Apr 2024 11:37:44 +0200 Subject: [PATCH 046/138] Changed some path colors and widths --- .../gui/riscv_single_stage_svg_directives.py | 4 ++-- .../src/img/riscv_single_stage_pipeline.svg | 24 +++++++++---------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/architecture_simulator/gui/riscv_single_stage_svg_directives.py b/architecture_simulator/gui/riscv_single_stage_svg_directives.py index 2846de1..0acac87 100644 --- a/architecture_simulator/gui/riscv_single_stage_svg_directives.py +++ b/architecture_simulator/gui/riscv_single_stage_svg_directives.py @@ -56,8 +56,8 @@ def __init__(self) -> None: ) # Non Binary signals - self.control_unit_to_4mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() - self.alu_control_to_alu_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() + self.control_unit_to_4mux_path: SvgFillDirectiveGreen = SvgFillDirectiveGreen() + self.alu_control_to_alu_path: SvgFillDirectiveGreen = SvgFillDirectiveGreen() # Other paths self.pc_to_add_instr_len_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() diff --git a/webgui/src/img/riscv_single_stage_pipeline.svg b/webgui/src/img/riscv_single_stage_pipeline.svg index 308efba..7dfb30d 100755 --- a/webgui/src/img/riscv_single_stage_pipeline.svg +++ b/webgui/src/img/riscv_single_stage_pipeline.svg @@ -8,7 +8,7 @@ version="1.1" id="svg5" xml:space="preserve" - inkscape:version="1.3.2 (091e20e, 2023-11-25, custom)" + inkscape:version="1.2.2 (b0a8486541, 2022-12-01)" sodipodi:docname="riscv_single_stage_pipeline.svg" xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" @@ -24,13 +24,13 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="true" - inkscape:zoom="0.70710678" - inkscape:cx="3175.6166" - inkscape:cy="1788.273" + inkscape:zoom="0.5" + inkscape:cx="5225" + inkscape:cy="1522" inkscape:window-width="1920" - inkscape:window-height="1017" - inkscape:window-x="-8" - inkscape:window-y="341" + inkscape:window-height="1007" + inkscape:window-x="0" + inkscape:window-y="0" inkscape:window-maximized="1" inkscape:current-layer="layer6" showguides="true" @@ -227,7 +227,7 @@ sodipodi:nodetypes="cccc" inkscape:label="control-unit-to-reg-file-path" /> Date: Mon, 22 Apr 2024 11:38:37 +0200 Subject: [PATCH 047/138] Removed some outdated comments --- .../gui/riscv_single_stage_svg_directives.py | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/architecture_simulator/gui/riscv_single_stage_svg_directives.py b/architecture_simulator/gui/riscv_single_stage_svg_directives.py index 0acac87..073e45a 100644 --- a/architecture_simulator/gui/riscv_single_stage_svg_directives.py +++ b/architecture_simulator/gui/riscv_single_stage_svg_directives.py @@ -94,16 +94,12 @@ def __init__(self) -> None: self.alu_out_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.alu_out_to_4mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.alu_out_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() - self.alu_comparison_to_and_path: SvgFillDirectiveGreen = ( - SvgFillDirectiveGreen() - ) # Green since it is a binary value + self.alu_comparison_to_and_path: SvgFillDirectiveGreen = SvgFillDirectiveGreen() self.alu_to_data_memory_address_path: SvgFillDirectiveBlue = ( SvgFillDirectiveBlue() ) - self.and_to_mux_path: SvgFillDirectiveGreen = ( - SvgFillDirectiveGreen() - ) # Green since it is a binary value (should be named or!) + self.and_to_mux_path: SvgFillDirectiveGreen = SvgFillDirectiveGreen() self.add_imm_to_mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.add_instr_len_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() From 3bacd73c64bb5ccc65cd923e609705603f96bfe1 Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Wed, 24 Apr 2024 11:50:10 +0200 Subject: [PATCH 048/138] begin more updates to single stage svg --- .../gui/riscv_single_stage_svg_directives.py | 3 +- .../simulation/riscv_simulation.py | 11 +- .../src/img/riscv_single_stage_pipeline.svg | 1260 +++++++++-------- 3 files changed, 680 insertions(+), 594 deletions(-) diff --git a/architecture_simulator/gui/riscv_single_stage_svg_directives.py b/architecture_simulator/gui/riscv_single_stage_svg_directives.py index 073e45a..482cebe 100644 --- a/architecture_simulator/gui/riscv_single_stage_svg_directives.py +++ b/architecture_simulator/gui/riscv_single_stage_svg_directives.py @@ -60,7 +60,7 @@ def __init__(self) -> None: self.alu_control_to_alu_path: SvgFillDirectiveGreen = SvgFillDirectiveGreen() # Other paths - self.pc_to_add_instr_len_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() + self.instr_to_aluctrl_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.pc_to_add_imm_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.pc_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.pc_to_instr_mem_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() @@ -70,6 +70,7 @@ def __init__(self) -> None: self.instr_mem_to_read_addr2_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.instr_mem_to_write_reg_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.instr_mem_to_imm_gen_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() + self.to_immgen_or_aluctrl_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.instr_mem_to_control_unit_path: SvgFillDirectiveBlue = ( SvgFillDirectiveBlue() ) diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index a86b2f9..ec6e10d 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -706,12 +706,11 @@ def get_riscv_single_stage_svg_update_values(self) -> list[tuple[str, str, Any]] result.alu_control_to_alu_path.do_highlight = ( p_reg.control_unit_signals.alu_control ) + result.instr_to_aluctrl_path.do_highlight = ( + result.alu_control_to_alu_path.do_highlight + ) # Other paths - - result.pc_to_add_instr_len_path.do_highlight = bool( - result.add_instr_len_text.text - ) result.pc_to_add_imm_path.do_highlight = bool(result.add_imm_text.text) result.pc_to_2mux_path.do_highlight = bool(p_reg.control_unit_signals.alu_src_1) result.pc_to_instr_mem_path.do_highlight = bool(result.pc_text.text) @@ -729,6 +728,10 @@ def get_riscv_single_stage_svg_update_values(self) -> list[tuple[str, str, Any]] result.instr_mem_to_imm_gen_path.do_highlight = bool( result.imm_gen_value_text.text ) + result.to_immgen_or_aluctrl_path.do_highlight = ( + result.instr_mem_to_imm_gen_path.do_highlight + or result.instr_to_aluctrl_path.do_highlight + ) result.instr_mem_to_control_unit_path.do_highlight = bool( result.instr_mem_instr_text.text ) diff --git a/webgui/src/img/riscv_single_stage_pipeline.svg b/webgui/src/img/riscv_single_stage_pipeline.svg index 7dfb30d..62bf079 100755 --- a/webgui/src/img/riscv_single_stage_pipeline.svg +++ b/webgui/src/img/riscv_single_stage_pipeline.svg @@ -8,8 +8,8 @@ version="1.1" id="svg5" xml:space="preserve" - inkscape:version="1.2.2 (b0a8486541, 2022-12-01)" - sodipodi:docname="riscv_single_stage_pipeline.svg" + inkscape:version="1.3.2 (091e20e, 2023-11-25, custom)" + sodipodi:docname="riscv_single_stage_pipeline.svg.2024_04_24_10_01_53.0.svg" xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" xmlns="http://www.w3.org/2000/svg" @@ -18,23 +18,26 @@ pagecolor="#505050" bordercolor="#ffffff" borderopacity="1" - inkscape:showpageshadow="0" + inkscape:showpageshadow="false" inkscape:pageopacity="0" inkscape:pagecheckerboard="1" inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="true" - inkscape:zoom="0.5" - inkscape:cx="5225" - inkscape:cy="1522" - inkscape:window-width="1920" - inkscape:window-height="1007" - inkscape:window-x="0" - inkscape:window-y="0" + inkscape:zoom="0.35355339" + inkscape:cx="2931.6647" + inkscape:cy="2464.9742" + inkscape:window-width="2560" + inkscape:window-height="1377" + inkscape:window-x="1912" + inkscape:window-y="-8" inkscape:window-maximized="1" inkscape:current-layer="layer6" showguides="true" - inkscape:lockguides="false"> + + + + +Instruction MemoryInstr[31-0]PCRead Addr 1Data MemoryData MemoryControlUnitImm GenALUControlAddComparisonALUResult10101010101101010101010101010101101010101010110101010101010101010ALUControlMuxAdd0Control1UnitMux0Add10011Mux00110Mux101230Add1ALUMux2Result3Comparison1010101010PC10101010101101010101011010101010RegWriteMemWriteMemReadImm Gen101010101010101010101 + x="731.02557" + y="1025.2313" + id="tspan47074-1-3-1-52-4" /> From 5fb80de888102fc43a8fa324be423618b265fe31 Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Wed, 24 Apr 2024 12:16:40 +0200 Subject: [PATCH 049/138] change ctrl color to red --- .../gui/riscv_single_stage_svg_directives.py | 38 ++-- build_svg.py | 126 +---------- .../src/img/riscv_single_stage_pipeline.svg | 208 ++++++++---------- 3 files changed, 108 insertions(+), 264 deletions(-) diff --git a/architecture_simulator/gui/riscv_single_stage_svg_directives.py b/architecture_simulator/gui/riscv_single_stage_svg_directives.py index 482cebe..ba5963e 100644 --- a/architecture_simulator/gui/riscv_single_stage_svg_directives.py +++ b/architecture_simulator/gui/riscv_single_stage_svg_directives.py @@ -37,27 +37,21 @@ def __init__(self) -> None: # Control Unit paths # Binary signals - self.control_unit_2mux_pc_path: SvgFillDirectiveGreen = SvgFillDirectiveGreen() - self.control_unit_to_and_path: SvgFillDirectiveGreen = SvgFillDirectiveGreen() - self.alu_control_to_read_data_2mux_path: SvgFillDirectiveGreen = ( - SvgFillDirectiveGreen() + self.control_unit_2mux_pc_path: SvgFillDirectiveRed = SvgFillDirectiveRed() + self.control_unit_to_and_path: SvgFillDirectiveRed = SvgFillDirectiveRed() + self.alu_control_to_read_data_2mux_path: SvgFillDirectiveRed = ( + SvgFillDirectiveRed() ) - self.alu_control_to_read_data_1_mux_path: SvgFillDirectiveGreen = ( - SvgFillDirectiveGreen() - ) - self.control_unit_write_data_path: SvgFillDirectiveGreen = ( - SvgFillDirectiveGreen() - ) - self.control_unit_read_data_path: SvgFillDirectiveGreen = ( - SvgFillDirectiveGreen() - ) - self.control_unit_to_reg_file_path: SvgFillDirectiveGreen = ( - SvgFillDirectiveGreen() + self.alu_control_to_read_data_1_mux_path: SvgFillDirectiveRed = ( + SvgFillDirectiveRed() ) + self.control_unit_write_data_path: SvgFillDirectiveRed = SvgFillDirectiveRed() + self.control_unit_read_data_path: SvgFillDirectiveRed = SvgFillDirectiveRed() + self.control_unit_to_reg_file_path: SvgFillDirectiveRed = SvgFillDirectiveRed() # Non Binary signals - self.control_unit_to_4mux_path: SvgFillDirectiveGreen = SvgFillDirectiveGreen() - self.alu_control_to_alu_path: SvgFillDirectiveGreen = SvgFillDirectiveGreen() + self.control_unit_to_4mux_path: SvgFillDirectiveRed = SvgFillDirectiveRed() + self.alu_control_to_alu_path: SvgFillDirectiveRed = SvgFillDirectiveRed() # Other paths self.instr_to_aluctrl_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() @@ -95,12 +89,12 @@ def __init__(self) -> None: self.alu_out_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.alu_out_to_4mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.alu_out_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() - self.alu_comparison_to_and_path: SvgFillDirectiveGreen = SvgFillDirectiveGreen() + self.alu_comparison_to_and_path: SvgFillDirectiveRed = SvgFillDirectiveRed() self.alu_to_data_memory_address_path: SvgFillDirectiveBlue = ( SvgFillDirectiveBlue() ) - self.and_to_mux_path: SvgFillDirectiveGreen = SvgFillDirectiveGreen() + self.and_to_mux_path: SvgFillDirectiveRed = SvgFillDirectiveRed() self.add_imm_to_mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.add_instr_len_to_2mux_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() @@ -166,8 +160,8 @@ def __init__(self): super().__init__(color_on="#0000FF", color_off="#000000") -class SvgFillDirectiveGreen(SvgFillDirective): - """SVG Fill Directive: highlight: green, default: black""" +class SvgFillDirectiveRed(SvgFillDirective): + """SVG Fill Directive: highlight: red, default: black""" def __init__(self): - super().__init__(color_on="#008000", color_off="#000000") + super().__init__(color_on="#A51E37", color_off="#000000") diff --git a/build_svg.py b/build_svg.py index ca70d49..5d4a697 100644 --- a/build_svg.py +++ b/build_svg.py @@ -1,6 +1,6 @@ import re -riscv_five_stage_markers = """ +riscv_markers = """ """ -riscv_single_stage_markers = """ - - - - - - - - - - - - - - - - - - -""" - if __name__ == "__main__": for filename, markers in [ - ("riscv_five_stage_pipeline.svg", riscv_five_stage_markers), - ("riscv_single_stage_pipeline.svg", riscv_single_stage_markers), + ("riscv_five_stage_pipeline.svg", riscv_markers), + ("riscv_single_stage_pipeline.svg", riscv_markers), ]: # open with read permissions file = open("./webgui/src/img/" + filename, "r+") diff --git a/webgui/src/img/riscv_single_stage_pipeline.svg b/webgui/src/img/riscv_single_stage_pipeline.svg index 62bf079..46a5261 100755 --- a/webgui/src/img/riscv_single_stage_pipeline.svg +++ b/webgui/src/img/riscv_single_stage_pipeline.svg @@ -57,121 +57,91 @@ - - - - - + style="fill:#000000;fill-rule:evenodd;stroke:#000000;stroke-width:1pt" + d="M 5.77,0 -2.88,5 V -5 Z" + id="000000_ArchsimMarker_Triangle_Path" /> - - - + style="fill:#A51E37;fill-rule:evenodd;stroke:#A51E37;stroke-width:1pt" + d="M 5.77,0 -2.88,5 V -5 Z" + id="A51E37_ArchsimMarker_Triangle_Path" /> - - + id="0000FF_ArchsimMarker_Triangle_Path" /> - - + style="fill:#000000;fill-rule:evenodd;stroke:none" + d="M 5,0 C 5,2.76 2.76,5 0,5 -2.76,5 -5,2.76 -5,0 c 0,-2.76 2.3,-5 5,-5 2.76,0 5,2.24 5,5 z" + id="Dot1" + sodipodi:nodetypes="sssss" /> - + style="fill:#0000FF;fill-rule:evenodd;stroke:none" + d="M 5,0 C 5,2.76 2.76,5 0,5 -2.76,5 -5,2.76 -5,0 c 0,-2.76 2.3,-5 5,-5 2.76,0 5,2.24 5,5 z" + id="Dot1" + sodipodi:nodetypes="sssss" /> Date: Wed, 24 Apr 2024 12:29:46 +0200 Subject: [PATCH 050/138] update version string --- pyproject.toml | 2 +- webgui/src/main.js | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pyproject.toml b/pyproject.toml index 8457cf6..6b799e5 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -1,6 +1,6 @@ [project] name = "architecture-simulator" -version = "1.3.0" +version = "1.3.1.dev0" readme = "README.md" requires-python = ">=3.10" dependencies = ["pyparsing","fixedint","prompt-toolkit"] diff --git a/webgui/src/main.js b/webgui/src/main.js index b98e481..a9e9ffa 100644 --- a/webgui/src/main.js +++ b/webgui/src/main.js @@ -1,7 +1,7 @@ import "./scss/styles.scss"; import "./css/main.css"; import "./css/splitjs.css"; -import architectureSimulatorPackageUrl from "../../dist/architecture_simulator-1.3.0-py3-none-any.whl"; +import architectureSimulatorPackageUrl from "../../dist/architecture_simulator-1.3.1.dev0-py3-none-any.whl"; import { createApp } from "vue"; From 6fbb3336b43764c8084bfe6095ca4c5d734fc92a Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Wed, 24 Apr 2024 14:49:45 +0200 Subject: [PATCH 051/138] small fixes to single stage svg --- .../gui/riscv_single_stage_svg_directives.py | 4 +- .../simulation/riscv_simulation.py | 3 + .../src/img/riscv_single_stage_pipeline.svg | 643 ++++++++---------- 3 files changed, 284 insertions(+), 366 deletions(-) diff --git a/architecture_simulator/gui/riscv_single_stage_svg_directives.py b/architecture_simulator/gui/riscv_single_stage_svg_directives.py index ba5963e..f05b0e7 100644 --- a/architecture_simulator/gui/riscv_single_stage_svg_directives.py +++ b/architecture_simulator/gui/riscv_single_stage_svg_directives.py @@ -52,7 +52,9 @@ def __init__(self) -> None: # Non Binary signals self.control_unit_to_4mux_path: SvgFillDirectiveRed = SvgFillDirectiveRed() self.alu_control_to_alu_path: SvgFillDirectiveRed = SvgFillDirectiveRed() - + self.control_unit_to_alu_control_path: SvgFillDirectiveRed = ( + SvgFillDirectiveRed() + ) # Other paths self.instr_to_aluctrl_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() self.pc_to_add_imm_path: SvgFillDirectiveBlue = SvgFillDirectiveBlue() diff --git a/architecture_simulator/simulation/riscv_simulation.py b/architecture_simulator/simulation/riscv_simulation.py index ec6e10d..4e80960 100644 --- a/architecture_simulator/simulation/riscv_simulation.py +++ b/architecture_simulator/simulation/riscv_simulation.py @@ -709,6 +709,9 @@ def get_riscv_single_stage_svg_update_values(self) -> list[tuple[str, str, Any]] result.instr_to_aluctrl_path.do_highlight = ( result.alu_control_to_alu_path.do_highlight ) + result.control_unit_to_alu_control_path.do_highlight = ( + result.alu_control_to_alu_path.do_highlight + ) # Other paths result.pc_to_add_imm_path.do_highlight = bool(result.add_imm_text.text) diff --git a/webgui/src/img/riscv_single_stage_pipeline.svg b/webgui/src/img/riscv_single_stage_pipeline.svg index 46a5261..582c388 100755 --- a/webgui/src/img/riscv_single_stage_pipeline.svg +++ b/webgui/src/img/riscv_single_stage_pipeline.svg @@ -4,12 +4,12 @@ - - - - -Instruction MemoryRead AddressInstr[31-0]101010101011010101010101010101010101010110101013AddPC10101010101 + y="1025.2314" + id="tspan47074-1-3-1-52-4" />0101AddPC10101010101Instruction MemoryRead AddressInstr[31-0]10101010101101010101010101010 From c3402ff154a7112416983305afd233ced9865309 Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Wed, 24 Apr 2024 15:18:49 +0200 Subject: [PATCH 052/138] minor svg layering chagnes --- .../src/img/riscv_single_stage_pipeline.svg | 170 +++++++++--------- 1 file changed, 85 insertions(+), 85 deletions(-) diff --git a/webgui/src/img/riscv_single_stage_pipeline.svg b/webgui/src/img/riscv_single_stage_pipeline.svg index 582c388..0c440ae 100755 --- a/webgui/src/img/riscv_single_stage_pipeline.svg +++ b/webgui/src/img/riscv_single_stage_pipeline.svg @@ -24,9 +24,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="true" - inkscape:zoom="0.25" - inkscape:cx="2962" - inkscape:cy="2038" + inkscape:zoom="0.1767767" + inkscape:cx="3020.7602" + inkscape:cy="1326.5323" inkscape:window-width="2560" inkscape:window-height="1377" inkscape:window-x="1912" @@ -169,6 +169,61 @@ inkscape:label="canvas" style="display:inline" transform="translate(-67.500005,27.499998)">Imm Gen10101010101Imm Gen + id="tspan47074-1-3-1-92" />10101010101 From 0e3e72bc73e9884590431d407b0205ce653734c2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Wed, 24 Apr 2024 15:44:49 +0200 Subject: [PATCH 053/138] Center ILength to make it legible again (5Stage) --- webgui/src/img/riscv_five_stage_pipeline.svg | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/webgui/src/img/riscv_five_stage_pipeline.svg b/webgui/src/img/riscv_five_stage_pipeline.svg index 8276eba..485fe15 100644 --- a/webgui/src/img/riscv_five_stage_pipeline.svg +++ b/webgui/src/img/riscv_five_stage_pipeline.svg @@ -25,9 +25,9 @@ inkscape:deskcolor="#505050" inkscape:document-units="mm" showgrid="false" - inkscape:zoom="0.70710681" - inkscape:cx="4507.8056" - inkscape:cy="2360.3223" + inkscape:zoom="4.0000002" + inkscape:cx="859.87497" + inkscape:cy="1672.7499" inkscape:window-width="1920" inkscape:window-height="1007" inkscape:window-x="0" @@ -35,7 +35,7 @@ inkscape:window-maximized="1" showguides="false" inkscape:lockguides="false" - inkscape:current-layer="layer6">10 Date: Thu, 25 Apr 2024 17:05:58 +0200 Subject: [PATCH 054/138] begin implementing accordion for riscv help page --- webgui/src/components/riscv/RiscvHelp.vue | 1561 ++++++++++++--------- 1 file changed, 879 insertions(+), 682 deletions(-) diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue index c1ba06d..d05c360 100644 --- a/webgui/src/components/riscv/RiscvHelp.vue +++ b/webgui/src/components/riscv/RiscvHelp.vue @@ -7,694 +7,891 @@ This simulator supports a subset of the RISC-V32 ISA. The supported instructions are listed below.

-

R-Type

-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
InstructionOperationNotes
- ADD rd, rs1, rs2 - - rd = rs1 + rs2 -
- SUB rd, rs1, rs2 - - rd = rs1 - rs2 -
- SLL rd, rs1, rs2 - - rd = rs1 << rs2 -
- SRL rd, rs1, rs2 - - rd = rs1 >> rs2 - Logical right shift
- SRA rd, rs1, rs2 - - rd = rs1 >>a rs2 - Arithmetic right shift
- SLT rd, rs1, rs2 - - rd = rs1 <s rs2 - - Set rd to 1 if the value in - rs1 is less than the value in - rs2, otherwise 0 (both values are - treated as signed) -
- SLTU rd, rs1, rs2 - - rd = rs1 <u rs2 - - Set rd to 1 if the value in - rs1 is less than the value in - rs2, otherwise 0 (both values are - treated as unsigned) -
- AND rd, rs1, rs2 - - rd = rs1 & rs2 -
- OR rd, rs1, rs2 - - rd = rs1 | rs2 -
- XOR rd, rs1, rs2 - - rd = rs1 ^ rs2 -
- MUL rd, rs1, rs2 - - rd = rs1 * rs2 - - (M), places the lower 32 bits of the result in the - destination register -
- MULH rd, rs1, rs2 - - rd = rs1 s*s rs2 - - (M), places the upper 32 bits of the result in the - destination register, both rs1 and rs2 are treated - as signed -
- MULHU rd, rs1, rs2 - - rd = rs1 u*u rs2 - - (M), places the upper 32 bits of the result in the - destination register, both rs1 and rs2 are treated - as unsigned -
- MULHSU rd, rs1, rs2 - - rd = rs1 s*u rs2 - - (M), places the upper 32 bits of the result in the - destination register, rs1 treated as signed, rs2 - treated as unsigned -
- DIV rd, rs1, rs2 - - rd = rs1 /s rs2 - (M), signed integer division
- DIVU rd, rs1, rs2 - - rd = rs1 /u rs2 - (M), unsigned integer division
- REM rd, rs1, rs2 - - rd = rs1 %s rs2 - (M), remainder of signed integer division
- REMU rd, rs1, rs2 - - rd = rs1 %u rs2 - (M), remainder of unsigned integer division
-
-

- Note: Instructions marked with (M) are part of the "M” Standard - Extension for Integer Multiplication and Division. -

- -

I-Type

-

- Unless otherwise specified, the immediate (imm) has a - length of 12 bits and is sign extended to 32 bits. -
- var is a variable name, index is an - optional array index. -

-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + +
InstructionOperationNotes
- ADDI rd, rs1, imm - - rd = rs1 + imm -
- SLTI rd, rs1, imm - - rd = rs1 <s imm - - Set rd to 1 if the value in - rs1 is less than the value in - imm, otherwise 0 (both values are - treated as signed) -
- SLTIU rd, rs1, imm - - rd = rs1 <u imm - - Set rd to 1 if the value in - rs1 is less than the value in - imm, otherwise 0 (both values are - treated as unsigned) -
- ANDI rd, rs1, imm - - rd = rs1 & imm -
- ORI rd, rs1, imm - - rd = rs1 | imm -
- XORI rd, rs1, imm - - rd = rs1 ^ imm -
- SLLI rd, rs1, imm - - rd = rs1 << imm - - imm is unsigned, with a length of 5 - bits -
- SRLI rd, rs1, imm - - rd = rs1 >> imm - - Logical right shift.
imm - is unsigned, with a length of 5 bits -
- SRAI rd, rs1, imm - - rd = rs1 >>a imm - - Arithmetic right shift.
imm - is unsigned, with a length of 5 bits -
- LB rd, rs1, imm
- LB rd, imm(rs1)
- LB rd, var[index] - 		- rd = M[rs1 + imm]
- rd = var[index] - 		- Load byte.
rd - is sign extended to 32 bits -
- LH rd, rs1, imm
- LH rd, imm(rs1)
- LH rd, var[index] - 		- rd = M[rs1 + imm]
- rd = var[index] - 		- Load two bytes.
rd - is sign extended to 32 bits -
- LW rd, rs1, imm
- LW rd, imm(rs1)
- LW rd, var[index] - 		- rd = M[rs1 + imm]
- rd = var[index] - 		- Load four bytes.
rd - is sign extended to 32 bits -
- LBU rd, rs1, imm
- LBU rd, imm(rs1)
- LBU rd, var[index] - 		- rd = M[rs1 + imm]
- rd = var[index] - 		Load byte
- LHU rd, rs1, imm
- LHU rd, imm(rs1)
- LHU rd, var[index] - 		- rd = M[rs1 + imm]
- rd = var[index] +
+
+

+ +

+
+
+
+ - - - - - - - - - - - - - - -
Load two bytes
- JALR rd, rs1, imm - - rd = PC + 4; PC = rs1 + imm - - Jump and link register. - rd is set to the address of the - instruction following the jump. The jump target is - rs1 + imm - with the least significant bit cleared. -
- ECALL - - environment call - - See section ECALLs. -
-
- -

S-Type

-

- The immediate (imm) has a length of 12 bits and is sign - extended to 32 bits.
- var is a variable name, index is an - optional array index. -

-
- - - - - - - - - - - - - - - - - - - - - - - - - -
InstructionOperationNotes
- SB rs1, rs2, imm
- SB rs1, imm(rs2)
- SB rs1, var[index], rs2 - 		- M[rs2 + imm] = rs1
- var[index] = rs1 - 		- Store byte.
If a variable is modified, - rs2 is used as a temporary register, - that will be overwritten. -
- SH rs1, rs2, imm
- SH rs1, imm(rs2)
- SH rs1, var[index], rs2 - 		- M[rs2 + imm] = rs1
- var[index] = rs1 - 		- Store two bytes.
If a variable is modified, - rs2 is used as a temporary register, - that will be overwritten. -
- SW rs1, rs2, imm
- SW rs1, imm(rs2)
- SW rs1, var[index], rs2 - 		- M[rs2 + imm] = rs1
- var[index] = rs1 - 		- Store four bytes.
If a variable is modified, - rs2 is used as a temporary register, - that will be overwritten. -
-
-

B-Type

-

- The immediate (imm) has a length of 13 bits and is sign - extended to 32 bits.
- Offsets are optional, and in hexadecimal format. -

-
- - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
InstructionOperationNotes
- BEQ rs1, rs2, imm
- BEQ rs1, rs2, label+offset - 		- if (rs1 == rs2) PC = PC + imm - Branch if equal
- BNE rs1, rs2, imm
- BNE rs1, rs2, label+offset - 		- if (rs1 != rs2) PC = PC + imm - Branch if not equal
- BLT rs1, rs2, imm
- BLT rs1, rs2, label+offset +
InstructionOperationNotes
+ ADD rd, rs1, rs2 + + rd = rs1 + rs2 +
+ SUB rd, rs1, rs2 + + rd = rs1 - rs2 +
+ SLL rd, rs1, rs2 + + rd = rs1 << rs2 +
+ SRL rd, rs1, rs2 + + rd = rs1 >> rs2 + Logical right shift
+ SRA rd, rs1, rs2 + + rd = rs1 >>a rs2 + Arithmetic right shift
+ SLT rd, rs1, rs2 + + rd = rs1 <s rs2 + + Set rd to 1 if the + value in rs1 is less + than the value in rs2, + otherwise 0 (both values are treated + as signed) +
+ SLTU rd, rs1, rs2 + + rd = rs1 <u rs2 + + Set rd to 1 if the + value in rs1 is less + than the value in rs2, + otherwise 0 (both values are treated + as unsigned) +
+ AND rd, rs1, rs2 + + rd = rs1 & rs2 +
+ OR rd, rs1, rs2 + + rd = rs1 | rs2 +
+ XOR rd, rs1, rs2 + + rd = rs1 ^ rs2 +
+ MUL rd, rs1, rs2 + + rd = rs1 * rs2 + + (M), places the lower 32 bits of the + result in the destination register +
+ MULH rd, rs1, rs2 + + rd = rs1 s*s rs2 + + (M), places the upper 32 bits of the + result in the destination register, + both rs1 and rs2 are treated as + signed +
+ MULHU rd, rs1, rs2 + + rd = rs1 u*u rs2 + + (M), places the upper 32 bits of the + result in the destination register, + both rs1 and rs2 are treated as + unsigned +
+ MULHSU rd, rs1, rs2 + + rd = rs1 s*u rs2 + + (M), places the upper 32 bits of the + result in the destination register, + rs1 treated as signed, rs2 treated + as unsigned +
+ DIV rd, rs1, rs2 + + rd = rs1 /s rs2 + (M), signed integer division
+ DIVU rd, rs1, rs2 + + rd = rs1 /u rs2 + (M), unsigned integer division
+ REM rd, rs1, rs2 + + rd = rs1 %s rs2 + + (M), remainder of signed integer + division +
+ REMU rd, rs1, rs2 + + rd = rs1 %u rs2 + + (M), remainder of unsigned integer + division +
+
+

+ Note: Instructions marked with (M) are part of the + "M" Standard Extension for Integer Multiplication + and Division. +

+
+
+
+
+

+ +

+
+
+

+ Unless otherwise specified, the immediate + (imm) has a length of 12 bits and is + sign extended to 32 bits. +
+ var is a variable name, + index is an optional array index. +

+
+ - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
- if (rs1 <s rs2) PC = PC + imm - Branch if less than
- BGE rs1, rs2, imm
- BGE rs1, rs2, label+offset +
InstructionOperationNotes
+ ADDI rd, rs1, imm + + rd = rs1 + imm +
+ SLTI rd, rs1, imm + + rd = rs1 <s imm + + Set rd to 1 if the + value in rs1 is less + than the value in imm, + otherwise 0 (both values are treated + as signed) +
+ SLTIU rd, rs1, imm + + rd = rs1 <u imm + + Set rd to 1 if the + value in rs1 is less + than the value in imm, + otherwise 0 (both values are treated + as unsigned) +
+ ANDI rd, rs1, imm + + rd = rs1 & imm +
+ ORI rd, rs1, imm + + rd = rs1 | imm +
+ XORI rd, rs1, imm + + rd = rs1 ^ imm +
+ SLLI rd, rs1, imm + + rd = rs1 << imm + + imm is unsigned, with a + length of 5 bits +
+ SRLI rd, rs1, imm + + rd = rs1 >> imm + + Logical right shift.
imm + is unsigned, with a length of 5 bits +
+ SRAI rd, rs1, imm + + rd = rs1 >>a imm + + Arithmetic right shift.
imm + is unsigned, with a length of 5 bits +
+ LB rd, rs1, imm
+ LB rd, imm(rs1)
+ LB rd, var[index] + 		+ rd = M[rs1 + imm]
+ rd = var[index] + 		+ Load byte.
rd + is sign extended to 32 bits +
+ LH rd, rs1, imm
+ LH rd, imm(rs1)
+ LH rd, var[index] + 		+ rd = M[rs1 + imm]
+ rd = var[index] + 		+ Load two bytes.
rd + is sign extended to 32 bits +
+ LW rd, rs1, imm
+ LW rd, imm(rs1)
+ LW rd, var[index] + 		+ rd = M[rs1 + imm]
+ rd = var[index] + 		+ Load four bytes.
rd + is sign extended to 32 bits +
+ LBU rd, rs1, imm
+ LBU rd, imm(rs1)
+ LBU rd, var[index] + 		+ rd = M[rs1 + imm]
+ rd = var[index] + 		Load byte
+ LHU rd, rs1, imm
+ LHU rd, imm(rs1)
+ LHU rd, var[index] + 		+ rd = M[rs1 + imm]
+ rd = var[index] + 		Load two bytes
+ JALR rd, rs1, imm + + rd = PC + 4; PC = rs1 + + imm + + Jump and link register. + rd is set to the + address of the instruction following + the jump. The jump target is + rs1 + imm + with the least significant bit + cleared. +
+ ECALL + + environment call + + See section + ECALLs. +
+
+
+
+
+
+

+ +

+
+
+

+ The immediate (imm) has a length of 12 + bits and is sign extended to 32 bits.
+ var is a variable name, + index is an optional array index. +

+
+ - - - - - - + + + + + + + + + + + + + + + + + + + + + + +
- if (rs1 >=s rs2) PC = PC + imm - Branch if greater than or equal
- BLTU rs1, rs2, imm
- BLTU rs1, rs2, label+offset +
InstructionOperationNotes
+ SB rs1, rs2, imm
+ SB rs1, imm(rs2)
+ SB rs1, var[index], rs2 + 		+ M[rs2 + imm] = rs1
+ var[index] = rs1 + 		+ Store byte.
If a variable is + modified, rs2 is used + as a temporary register, that will + be overwritten. +
+ SH rs1, rs2, imm
+ SH rs1, imm(rs2)
+ SH rs1, var[index], rs2 + 		+ M[rs2 + imm] = rs1
+ var[index] = rs1 + 		+ Store two bytes.
If a variable + is modified, rs2 is + used as a temporary register, that + will be overwritten. +
+ SW rs1, rs2, imm
+ SW rs1, imm(rs2)
+ SW rs1, var[index], rs2 + 		+ M[rs2 + imm] = rs1
+ var[index] = rs1 + 		+ Store four bytes.
If a variable + is modified, rs2 is + used as a temporary register, that + will be overwritten. +
+
+
+
+
+
+

+ +

+
+
+

+ The immediate (imm) has a length of 13 + bits and is sign extended to 32 bits.
+ Offsets are optional, and in hexadecimal format. +

+
+ - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
- if (rs1 <u rs2) PC = PC + imm - Branch if less than (unsigned)
- BGEU rs1, rs2, imm
- BGEU rs1, rs2, label+offset +
InstructionOperationNotes
+ BEQ rs1, rs2, imm
+ BEQ rs1, rs2, label+offset + 		+ if (rs1 == rs2) PC = PC + + imm + Branch if equal
+ BNE rs1, rs2, imm
+ BNE rs1, rs2, label+offset + 		+ if (rs1 != rs2) PC = PC + + imm + Branch if not equal
+ BLT rs1, rs2, imm
+ BLT rs1, rs2, label+offset + 		+ if (rs1 <s rs2) PC = PC + + imm + Branch if less than
+ BGE rs1, rs2, imm
+ BGE rs1, rs2, label+offset + 		+ if (rs1 >=s rs2) PC = PC + + imm + Branch if greater than or equal
+ BLTU rs1, rs2, imm
+ BLTU rs1, rs2, + label+offset + 		+ if (rs1 <u rs2) PC = PC + + imm + Branch if less than (unsigned)
+ BGEU rs1, rs2, imm
+ BGEU rs1, rs2, + label+offset + 		+ if (rs1 >=u rs2) PC = PC + + imm + + Branch if greater than or equal + (unsigned) +
+
+
+
+
+
+

+ +

+
+
+

+ The immediate (imm) has a length of 20 + bits and is sign extended to 32 bits. +

+
+ - - - - - -
- if (rs1 >=u rs2) PC = PC + imm - Branch if greater than or equal (unsigned)
-
- -

U-Type

-

- The immediate (imm) has a length of 20 bits and is sign - extended to 32 bits. -

-
- - - - - - - - - - - - - - - - - - - - -
InstructionOperationNotes
- LUI rd, imm - - rd = imm << 12 -
- AUIPC rd, imm - - rd = PC + (imm << 12) -
-
- -

J-Type

-

- The address to jump to (addr), is encoded relative to - the current pc in a 21 bit immediate that is sign extended to 32 - bits and added to the current pc.
- Offsets are optional, and in hexadecimal format. -

-
- - - - - - - - - - - + + + + + + + + + + + + + + + + + +
InstructionOperationNotes
- JAL rd, addr
- JAL rd, label+offset +
InstructionOperationNotes
+ LUI rd, imm + + rd = imm << 12 +
+ AUIPC rd, imm + + rd = PC + (imm << + 12) +
+
+
+
+
+
+

+ +

+
+
+

+ The address to jump to (addr), is + encoded relative to the current pc in a 21 bit + immediate that is sign extended to 32 bits and added + to the current pc.
+ Offsets are optional, and in hexadecimal format. +

+
+ - - - - - -
- rd = PC + 4; PC = addr - - Jump and link. - rd is set to the address of the - instruction following the jump. -
- +
InstructionOperationNotes
+ JAL rd, addr
+ JAL rd, label+offset + 		+ rd = PC + 4; PC = addr + + Jump and link. + rd is set to the + address of the instruction following + the jump. +
+
+ + + +

CSR-Type

Currently not implemented in 5-stage pipeline mode. From bb5b6929b9382d827e8c4fc5c955af425b020178 Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Thu, 25 Apr 2024 17:36:22 +0200 Subject: [PATCH 055/138] more collapsibles --- webgui/src/components/riscv/RiscvHelp.vue | 447 +++++++++++++--------- 1 file changed, 267 insertions(+), 180 deletions(-) diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue index d05c360..e35a4bc 100644 --- a/webgui/src/components/riscv/RiscvHelp.vue +++ b/webgui/src/components/riscv/RiscvHelp.vue @@ -891,190 +891,277 @@ - -

CSR-Type

-

- Currently not implemented in 5-stage pipeline mode. -
- The unsigned immediate (uimm) has a length of 5 - bits. -

-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
InstructionOperationNotes
- CSRRW rd, csr, rs1 - - rd = csr; csr = rs1 - Atomic read/write
- CSRRS rd, csr, rs1 - - rd = csr; csr = csr | rs1 - - Atomic read/set. - rs1 - serves as a bit mask -
- CSRRC rd, csr, rs1 - - rd = csr; csr = csr & ~rs1 - - Atomic read/clear. - rs1 - serves as a bit mask -
- CSRRWI rd, csr, uimm - - rd = csr; csr = uimm - Atomic read/write
- CSRRSI rd, csr, uimm - - rd = csr; csr = csr | uimm - - Atomic read/set. - uimm - serves as a bit mask -
- CSRRCI rd, csr, uimm - - rd = csr; csr = csr & ~uimm - - Atomic read/clear. - uimm - serves as a bit mask -
+
+

+ +

+
+
+

+ Currently not implemented in 5-stage pipeline + mode. +
+ The unsigned immediate (uimm) has a + length of 5 bits. +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
InstructionOperationNotes
+ CSRRW rd, csr, rs1 + + rd = csr; csr = rs1 + Atomic read/write
+ CSRRS rd, csr, rs1 + + rd = csr; csr = csr | rs1 + + Atomic read/set. + rs1 + serves as a bit mask +
+ CSRRC rd, csr, rs1 + + rd = csr; csr = csr & + ~rs1 + + Atomic read/clear. + rs1 + serves as a bit mask +
+ CSRRWI rd, csr, uimm + + rd = csr; csr = uimm + Atomic read/write
+ CSRRSI rd, csr, uimm + + rd = csr; csr = csr | + uimm + + Atomic read/set. + uimm + serves as a bit mask +
+ CSRRCI rd, csr, uimm + + rd = csr; csr = csr & + ~uimm + + Atomic read/clear. + uimm + serves as a bit mask +
+
+
+
- -

Pseudoinstructions

-

- var is a variable name, index is an - optional array index. -

-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
InstructionOperationNotes
- NOP - - - No operation. Translated to - ADDI x0, x0, 0 -
- LA rd, var[index] - - rd = &var[index] - - Load variable address into - rd -
- LI rd, imm - - rd = imm - - Load 32 bit immediate into - rd -
- MV rd, rs - rd = rs - Translated to - ADDI rd, rs, 0 -
+
+

+ +

+
+
+

+ var is a variable name, + index is an optional array index. +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
InstructionOperationNotes
+ NOP + - + No operation. Translated to + ADDI x0, x0, 0 +
+ LA rd, var[index] + + rd = &var[index] + + Load variable address into + rd +
+ LI rd, imm + + rd = imm + + Load 32 bit immediate into + rd +
+ MV rd, rs + rd = rs + Translated to + ADDI rd, rs, 0 +
+
+
+
- -

Miscellaneous

-
- - - - - - - - - - - - - - - - - - - - -
InstructionOperationNotes
- EBREAK - -Recognized but currently not implemented
- FENCE rd, rs1 - -Recognized but currently not implemented
+
+

+ +

+
+
+
+ + + + + + + + + + + + + + + + + + + + +
InstructionOperationNotes
+ EBREAK + - + Recognized but currently not + implemented +
+ FENCE rd, rs1 + - + Recognized but currently not + implemented +
+
+
+
+

Comments and labels

From 5dc96422f20222c50357e5f6c863719a13309c0f Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Thu, 25 Apr 2024 18:54:20 +0200 Subject: [PATCH 056/138] move all sections into accordion --- webgui/src/components/riscv/RiscvHelp.vue | 460 ++++++++++++++-------- 1 file changed, 293 insertions(+), 167 deletions(-) diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue index e35a4bc..f8e53b0 100644 --- a/webgui/src/components/riscv/RiscvHelp.vue +++ b/webgui/src/components/riscv/RiscvHelp.vue @@ -1162,40 +1162,84 @@

- -

Comments and labels

-

- Comments can be added to the code using - #.
- Labels are added by appending a colon - : to a label name. They can be used as jump targets. -

- 
+        
Other

+        
+        

+            

+                

+                    
+                

+                

+                    

+                        

+                            Comments can be added to the code using
+                            #.

+                            Labels are added by appending a colon
+                            : to a label name. They can be used as
+                            jump targets.
+                        

+                        
 # This is a comment
 my_label:
 addi x1, x1, 1
 jal x2, my_label
 addi x3, x3, 1 # This line is never reached

-
-        
Segments and variables

-        

-            In addition to the program code, the simulator supports a data
-            segment. It can be used to store variables and arrays in the
-            simulator's memory.
-        

-        

-            In order to define a data segment, the
-            .data directive is used, while the
-            .text directive designates the code segment.
-        

-        

-            The following example demonstrates how to declare and use variables
-            and arrays, employing all currently supported data types. Note that
-            all variables/arrays are word-aligned (addresses are multiples of
-            4), which is achieved by zero-padding preceding variables.
-        

-        
+                        >
+                    

+                

+            

+            

+                

+                    
+                

+                

+                    

+                        

+                            In addition to the program code, the simulator
+                            supports a data segment. It can be used to store
+                            variables and arrays in the simulator's memory.
+                        

+                        

+                            In order to define a data segment, the
+                            .data directive is used, while the
+                            .text directive designates the code
+                            segment.
+                        

+                        

+                            The following example demonstrates how to declare
+                            and use variables and arrays, employing all
+                            currently supported data types. Note that all
+                            variables/arrays are word-aligned (addresses are
+                            multiples of 4), which is achieved by zero-padding
+                            preceding variables.
+                        

+                        
 .data
     empty_array: .zero 64 # reserves space for 64 words (256 bytes)
     # The following two declarations of 'my_var1' are equivalent,
@@ -1212,146 +1256,228 @@ addi x3, x3, 1 # This line is never reached

-        

-            If no directives are given, the entire input is interpreted as
-            code.

-            Similarly, if a .data but no
-            .text directive is given, every line before the data
-            segment is interpreted as code.
-            

-            There is no fixed segmentation order. However, declaring multiple
-            segments of the same type will throw an error.
-        

-
-        
Cache Simulation

-        

-            You can activate separate caches for data and instructions in the
-            settings. These caches can be configured as Write-through with Write
-            no-allocate or Write-back with Write allocate. The number of sets,
-            block size and associativity are also configurable. You can also
-            choose between LRU and PLRU for the replacement strategy.
-        

-        

-            As the name implies, LRU (Least Recently Used) will always replace
-            the block that was used least recently. The LRU value in the cache
-            table shows the age of each block. Higher values indicate more
-            recently used blocks.
-        

-        

-            PLRU (Pseudo LRU) is an approximation of LRU which is easier to
-            implement in hardware. It uses a binary tree with the blocks at its
-            leaf nodes. On each non-leaf node is a single bit - a 0 indicates
-            that older blocks are in the upper child tree while a 1 indicates
-            that older blocks are in the lower child tree. 

-            When replacing a block, PLRU will choose the one which is oldest
-            according to those bits. Then all bits along the path are flipped to
-            mark it as the most recent. 

-            When accessing any block that is stored in the cache, PLRU will
-            update all bits along the path to the new block so they correctly
-            identify it as the newest block. 

-            Note that when using PLRU, associativity must be a power of 2 since
-            PLRU uses a binary tree in its state.
-        

-        

-            You can also get a visualization of the cache by selecting it in the
-            drop down menu in the control bar. Note that for performance
-            reasons, this option becomes unavailabe if the cache gets too big.
-            Even with the visualization disabled, you should not make the cache
-            too big since the site may become unresponsive.
-        

-        

-            When using a data cache, misaligned access to the memory is not
-            allowed because it would be unclear what exactly should happen in
-            the cache. For example, the following piece of code would not work
-            since the accessed value crosses a word boundary:
-        

-        
lw x1, -5(x0)

-
-        
ECALLs

-        

-            Environment calls (ECALLs) can be used for interacting with the
-            environment - currently, ECALLs can be used for printing to the
-            console or stopping the simulation. Each ECALL has a different code
-            which must be loaded into register a7. Some ECALLs also
-            require an argument which must be loaded into register
-            a0. The supported ECALLs are identical to those of
-            Ripes.
-        

+                        >
+                        

+                            If no directives are given, the entire input is
+                            interpreted as code.

+                            Similarly, if a .data but no
+                            .text directive is given, every line
+                            before the data segment is interpreted as code.
+                            

+                            There is no fixed segmentation order. However,
+                            declaring multiple segments of the same type will
+                            throw an error.
+                        

+                    

+                

+            

+            

+                

+                    
+                

+                

+                    

+                        

+                            You can activate separate caches for data and
+                            instructions in the settings. These caches can be
+                            configured as Write-through with Write no-allocate
+                            or Write-back with Write allocate. The number of
+                            sets, block size and associativity are also
+                            configurable. You can also choose between LRU and
+                            PLRU for the replacement strategy.
+                        

+                        

+                            As the name implies, LRU (Least Recently Used) will
+                            always replace the block that was used least
+                            recently. The LRU value in the cache table shows the
+                            age of each block. Higher values indicate more
+                            recently used blocks.
+                        

+                        

+                            PLRU (Pseudo LRU) is an approximation of LRU which
+                            is easier to implement in hardware. It uses a binary
+                            tree with the blocks at its leaf nodes. On each
+                            non-leaf node is a single bit - a 0 indicates that
+                            older blocks are in the upper child tree while a 1
+                            indicates that older blocks are in the lower child
+                            tree. 

+                            When replacing a block, PLRU will choose the one
+                            which is oldest according to those bits. Then all
+                            bits along the path are flipped to mark it as the
+                            most recent. 

+                            When accessing any block that is stored in the
+                            cache, PLRU will update all bits along the path to
+                            the new block so they correctly identify it as the
+                            newest block. 

+                            Note that when using PLRU, associativity must be a
+                            power of 2 since PLRU uses a binary tree in its
+                            state.
+                        

+                        

+                            You can also get a visualization of the cache by
+                            selecting it in the drop down menu in the control
+                            bar. Note that for performance reasons, this option
+                            becomes unavailabe if the cache gets too big. Even
+                            with the visualization disabled, you should not make
+                            the cache too big since the site may become
+                            unresponsive.
+                        

+                        

+                            When using a data cache, misaligned access to the
+                            memory is not allowed because it would be unclear
+                            what exactly should happen in the cache. For
+                            example, the following piece of code would not work
+                            since the accessed value crosses a word boundary:
+                        

+                        
lw x1, -5(x0)

+                    

+                

+            

+            

+                

+                    
+                

+                

+                    

+                        

+                            Environment calls (ECALLs) can be used for
+                            interacting with the environment - currently, ECALLs
+                            can be used for printing to the console or stopping
+                            the simulation. Each ECALL has a different code
+                            which must be loaded into register a7.
+                            Some ECALLs also require an argument which must be
+                            loaded into register a0. The supported
+                            ECALLs are identical to those of Ripes.
+                        

 
-        

-            Note that our visualization of the pipeline during an ECALL is not
-            fully correct. The pipeline might get flushed unnecessarily and we
-            also dont halt the pipeline until the ECALL has finished - instead,
-            the entire ecall is being executed in a single cycle (in the execute
-            stage).
-        

+                        

+                            Note that our visualization of the pipeline during
+                            an ECALL is not fully correct. The pipeline might
+                            get flushed unnecessarily and we also dont halt the
+                            pipeline until the ECALL has finished - instead, the
+                            entire ecall is being executed in a single cycle (in
+                            the execute stage).
+                        

 
-        

-            
-                
-                    
-                        
-                        
-                        
-                    
-                
-                
-                    
-                        
-                        
-                        
-                    
-                    
-                        
-                        
-                        
-                    
-                    
-                        
-                        
-                        
-                    
-                    
-                        
-                        
-                        
-                    
-                    
-                        
-                        
-                        
-                    
-                    
-                        
-                        
-                        
-                    
-                    
-                        
-                        
-                        
-                    
-                    
-                        
-                        
-                        
-                    
-                    
-                        
-                        
-                        
-                    
-                
-            
a7a0Description
1integer to printPrints a0 as signed integer.
2float to print
-                            Prints a0 as a floating point number.
-                        
4string to print
-                            Prints the null terminated string whose first
-                            character is stored at the address in
-                            a0.
-                        
10-Stops the simulation with code 0.
11char to printPrints a0 as ASCII character
34hex to printPrints a0 as hexadecimal nuber
35binary to printPrints a0 as binary number.
36integer to printPrints a0 as unsigned integer.
93exit code
-                            Stops the simulation with code in a0.
-                        

+                        

+                            
+                                
+                                    
+                                        
+                                        
+                                        
+                                    
+                                
+                                
+                                    
+                                        
+                                        
+                                        
+                                    
+                                    
+                                        
+                                        
+                                        
+                                    
+                                    
+                                        
+                                        
+                                        
+                                    
+                                    
+                                        
+                                        
+                                        
+                                    
+                                    
+                                        
+                                        
+                                        
+                                    
+                                    
+                                        
+                                        
+                                        
+                                    
+                                    
+                                        
+                                        
+                                        
+                                    
+                                    
+                                        
+                                        
+                                        
+                                    
+                                    
+                                        
+                                        
+                                        
+                                    
+                                
+                            
a7a0Description
1integer to print
+                                            Prints a0 as signed
+                                            integer.
+                                        
2float to print
+                                            Prints a0 as a floating
+                                            point number.
+                                        
4string to print
+                                            Prints the null terminated string
+                                            whose first character is stored at
+                                            the address in
+                                            a0.
+                                        
10-
+                                            Stops the simulation with code 0.
+                                        
11char to print
+                                            Prints a0 as ASCII
+                                            character
+                                        
34hex to print
+                                            Prints a0 as
+                                            hexadecimal nuber
+                                        
35binary to print
+                                            Prints a0 as binary
+                                            number.
+                                        
36integer to print
+                                            Prints a0 as unsigned
+                                            integer.
+                                        
93exit code
+                                            Stops the simulation with code in
+                                            a0.
+                                        

+                        

+                    

+                

+            

         

     

+    
 

From f101b2f24bd042427c5d34ea900a4653a11b197f Mon Sep 17 00:00:00 2001
From: MartinRoehm 
Date: Thu, 25 Apr 2024 19:15:04 +0200
Subject: [PATCH 057/138] finish accordion riscv help page

---
 webgui/src/components/riscv/RiscvHelp.vue | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue
index f8e53b0..c2b16dc 100644
--- a/webgui/src/components/riscv/RiscvHelp.vue
+++ b/webgui/src/components/riscv/RiscvHelp.vue
@@ -7,8 +7,8 @@
             This simulator supports a subset of the RISC-V32 ISA. The supported
             instructions are listed below.
         

-        
-        

+
+        

             

                 

                     

         

-        
-        
Other

-        
-        

+
+        
Other

+
+        

             

                 

                     
@@ -1479,5 +1480,4 @@ addi x3, x3, 1 # This line is never reached
- From 96ca224985829305125cd4353216119e6771ed05 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Fri, 26 Apr 2024 09:32:39 +0200 Subject: [PATCH 058/138] Added a test for the bug --- tests/test_riscv_pipeline.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/tests/test_riscv_pipeline.py b/tests/test_riscv_pipeline.py index 881a5b1..39215b5 100644 --- a/tests/test_riscv_pipeline.py +++ b/tests/test_riscv_pipeline.py @@ -1418,3 +1418,19 @@ def test_stall_2(self): self.assertEqual(sim.state.performance_metrics.cycles, 14) self.assertEqual(sim.state.performance_metrics.stalls, 2) self.assertEqual(sim.state.performance_metrics.flushes, 0) + + def test_exit(self): + program = """li a7, 10 + ecall + nop + nop + nop + nop + nop""" + + sim = RiscvSimulation(mode="five_stage_pipeline") + + sim.load_program(program) + sim.run() + self.assertEqual(sim.state.performance_metrics.cycles, 8) + self.assertEqual(sim.state.performance_metrics.instruction_count, 2) From 5798b24672f0dc3609fac9ccdea23f201235d697 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Fri, 26 Apr 2024 10:15:57 +0200 Subject: [PATCH 059/138] Ecall now continues until the wb stage But it doesn't flush yet, which is not good --- .../isa/riscv/rv32i_instructions.py | 42 +++++++++++++------ .../uarch/riscv/pipeline_registers.py | 2 + architecture_simulator/uarch/riscv/stages.py | 28 +++++++++---- 3 files changed, 53 insertions(+), 19 deletions(-) diff --git a/architecture_simulator/isa/riscv/rv32i_instructions.py b/architecture_simulator/isa/riscv/rv32i_instructions.py index fdb224f..2c925a8 100644 --- a/architecture_simulator/isa/riscv/rv32i_instructions.py +++ b/architecture_simulator/isa/riscv/rv32i_instructions.py @@ -825,38 +825,56 @@ def behavior( self, architectural_state: RiscvArchitecturalState ) -> RiscvArchitecturalState: """RaiseException(EnvironmentCall)""" + result = self.process_ecall(architectural_state) + if type(result) is int: + architectural_state.exit_code = result + elif type(result) is str: + architectural_state.output += result + return architectural_state + + def process_ecall(self, architectural_state: RiscvArchitecturalState) -> str | int: + """Processes this ecall. Returns the action to be applied to the architectural state. + + Args: + architectural_state (RiscvArchitecturalState): The state on which the ecall shall be applied. + + Raises: + ValueError: Raises an error if the ECALL code is invalid. + + Returns: + str|int: Returns either a string to be printed to the output or an exit code. + """ code = int(architectural_state.register_file.registers[17]) arg = int(architectural_state.register_file.registers[10]) match code: case 1: # print arg as sint - architectural_state.output += str(fixedint.Int32(arg)) + return str(fixedint.Int32(arg)) case 2: # print arg as 32-bit float - architectural_state.output += str( - unpack(">f", arg.to_bytes(4, "big"))[0] - ) + return str(unpack(">f", arg.to_bytes(4, "big"))[0]) case 4: # print null-terminated string stored at address in arg address = arg + result = "" while ( byte := architectural_state.memory.read_byte(address, False) ) != 0: - architectural_state.output += chr(byte % 128) + result += chr(byte % 128) address += 1 + return result case 11: # print arg as ascii char - architectural_state.output += chr(arg % 128) + return chr(arg % 128) case 34: # print arg as hex - architectural_state.output += "0x" + "{:X}".format(arg) + return "0x" + "{:X}".format(arg) case 35: # print arg as bin - architectural_state.output += bin(arg) + return bin(arg) case 36: # print arg as uint - architectural_state.output += str(arg) + return str(arg) case 10: # exit with status 0 - architectural_state.exit_code = 0 + return 0 case 93: # exit with arg as status - architectural_state.exit_code = arg + return arg case _: raise ValueError(f"{code} (register a7) is not a valid code for ECALL") - return architectural_state def alu_compute( self, alu_in_1: int | None, alu_in_2: int | None diff --git a/architecture_simulator/uarch/riscv/pipeline_registers.py b/architecture_simulator/uarch/riscv/pipeline_registers.py index 71dd00e..1f49d7d 100644 --- a/architecture_simulator/uarch/riscv/pipeline_registers.py +++ b/architecture_simulator/uarch/riscv/pipeline_registers.py @@ -63,6 +63,7 @@ class ExecutePipelineRegister(PipelineRegister): pc_plus_imm: Optional[int] = None branch_prediction: Optional[bool] = None pc_plus_instruction_length: Optional[int] = None + exit_code: Optional[int] = None abbreviation = "EX" @@ -80,6 +81,7 @@ class MemoryAccessPipelineRegister(PipelineRegister): pc_plus_imm: Optional[int] = None pc_plus_instruction_length: Optional[int] = None imm: Optional[int] = None + exit_code: Optional[int] = None abbreviation = "MEM" diff --git a/architecture_simulator/uarch/riscv/stages.py b/architecture_simulator/uarch/riscv/stages.py index 2d724f6..f1944ad 100644 --- a/architecture_simulator/uarch/riscv/stages.py +++ b/architecture_simulator/uarch/riscv/stages.py @@ -237,6 +237,7 @@ def behavior( # ECALL needs some special behavior (flush and print to output) stall_signal = None + exit_code = None if isinstance(pipeline_register.instruction, ECALL): # assume that all further stages need to be empty, unless this stage is already stalled and the value of the next register is only for display purposes for other_pr in pipeline_registers[ @@ -249,7 +250,11 @@ def behavior( stall_signal = StallSignal(2) break if stall_signal is None: - pipeline_register.instruction.behavior(state) + ecall_result = pipeline_register.instruction.process_ecall(state) + if type(ecall_result) is str: + state.output += ecall_result + elif type(ecall_result) is int: + exit_code = ecall_result return ExecutePipelineRegister( stall_signal=stall_signal, @@ -267,6 +272,7 @@ def behavior( branch_prediction=pipeline_register.branch_prediction, pc_plus_instruction_length=pipeline_register.pc_plus_instruction_length, address_of_instruction=pipeline_register.address_of_instruction, + exit_code=exit_code, ) @@ -349,6 +355,7 @@ def behavior( pc_plus_instruction_length=pipeline_register.pc_plus_instruction_length, imm=pipeline_register.imm, address_of_instruction=pipeline_register.address_of_instruction, + exit_code=pipeline_register.exit_code, ) @@ -402,6 +409,9 @@ def behavior( architectural_state=state, ) + if pipeline_register.exit_code is not None: + state.exit_code = pipeline_register.exit_code + return RegisterWritebackPipelineRegister( instruction=pipeline_register.instruction, register_write_data=register_write_data, @@ -504,12 +514,16 @@ def behavior( result_pr.pc_plus_imm = state.program_counter + result_pr.imm a_comparison, a_result = result_pr.instruction.alu_compute( - state.program_counter - if result_pr.control_unit_signals.alu_src_1 - else result_pr.register_read_data_1, - result_pr.imm - if result_pr.control_unit_signals.alu_src_2 - else result_pr.register_read_data_2, + ( + state.program_counter + if result_pr.control_unit_signals.alu_src_1 + else result_pr.register_read_data_1 + ), + ( + result_pr.imm + if result_pr.control_unit_signals.alu_src_2 + else result_pr.register_read_data_2 + ), ) result_pr.alu_comparison = bool(a_comparison) From 9882dd8d39ef7cd93b79776611eedc8d787f8d68 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Fri, 26 Apr 2024 10:19:09 +0200 Subject: [PATCH 060/138] Added a test for flushing --- tests/test_riscv_pipeline.py | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/tests/test_riscv_pipeline.py b/tests/test_riscv_pipeline.py index 39215b5..d3412b2 100644 --- a/tests/test_riscv_pipeline.py +++ b/tests/test_riscv_pipeline.py @@ -1419,7 +1419,7 @@ def test_stall_2(self): self.assertEqual(sim.state.performance_metrics.stalls, 2) self.assertEqual(sim.state.performance_metrics.flushes, 0) - def test_exit(self): + def test_exit_1(self): program = """li a7, 10 ecall nop @@ -1434,3 +1434,19 @@ def test_exit(self): sim.run() self.assertEqual(sim.state.performance_metrics.cycles, 8) self.assertEqual(sim.state.performance_metrics.instruction_count, 2) + + def test_exit_2(self): + # make sure instructions are flushed to prevent unwanted "side effects" + program = """li x3, 555 +li a7, 10 +ecall +sw x3, -4(x0) +nop +nop""" + sim = RiscvSimulation(mode="five_stage_pipeline") + + sim.load_program(program) + sim.run() + self.assertEqual(sim.state.performance_metrics.cycles, 9) + self.assertEqual(sim.state.performance_metrics.instruction_count, 3) + self.assertEqual(sim.state.memory.read_word(-4, False), 0) From 00fe3e6afa5d7f3b8e0fe81dbaa0b72be4752f46 Mon Sep 17 00:00:00 2001 From: Michael Kuhn Date: Fri, 26 Apr 2024 10:45:49 +0200 Subject: [PATCH 061/138] generate riscv instruction table from json data --- webgui/src/components/riscv/RiscvHelp.vue | 39 +++ webgui/src/data/riscv_instructions.json | 338 ++++++++++++++++++++++ 2 files changed, 377 insertions(+) create mode 100644 webgui/src/data/riscv_instructions.json diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue index c2b16dc..e472e3f 100644 --- a/webgui/src/components/riscv/RiscvHelp.vue +++ b/webgui/src/components/riscv/RiscvHelp.vue @@ -8,6 +8,25 @@ instructions are listed below.

+ + + + + + + + + + + + + +
+ {{ field }} +
+ {{ item[field] }} +
+

@@ -1481,3 +1500,23 @@ addi x3, x3, 1 # This line is never reached

+ diff --git a/webgui/src/data/riscv_instructions.json b/webgui/src/data/riscv_instructions.json new file mode 100644 index 0000000..1bb548c --- /dev/null +++ b/webgui/src/data/riscv_instructions.json @@ -0,0 +1,338 @@ +[ + { + "Instruction":"ADD rd, rs1, rs2", + "Operation":"rd = rs1 + rs2", + "Notes":null, + "Format":"R-type" + }, + { + "Instruction":"SUB rd, rs1, rs2", + "Operation":"rd = rs1 - rs2", + "Notes":null, + "Format":"R-type" + }, + { + "Instruction":"SLL rd, rs1, rs2", + "Operation":"rd = rs1 << rs2", + "Notes":null, + "Format":"R-type" + }, + { + "Instruction":"SRL rd, rs1, rs2", + "Operation":"rd = rs1 >> rs2", + "Notes":"Logical right shift", + "Format":"R-type" + }, + { + "Instruction":"SRA rd, rs1, rs2", + "Operation":"rd = rs1 >>a rs2", + "Notes":"Arithmetic right shift", + "Format":"R-type" + }, + { + "Instruction":"SLT rd, rs1, rs2", + "Operation":"rd = rs1 > imm", + "Notes":"Logical right shift. imm is unsigned, with a length of 5 bits", + "Format":"I-type" + }, + { + "Instruction":"SRAI rd, rs1, imm", + "Operation":"rd = rs1 >>a imm", + "Notes":"Arithmetic right shift. imm is unsigned, with a length of 5 bits", + "Format":"I-type" + }, + { + "Instruction":"LB rd, rs1, imm LB rd, imm(rs1) LB rd, var[index]", + "Operation":"rd = M[rs1 + imm] rd = var[index]", + "Notes":"Load byte. rd is sign extended to 32 bits", + "Format":"I-type" + }, + { + "Instruction":"LH rd, rs1, imm LH rd, imm(rs1) LH rd, var[index]", + "Operation":"rd = M[rs1 + imm] rd = var[index]", + "Notes":"Load two bytes. rd is sign extended to 32 bits", + "Format":"I-type" + }, + { + "Instruction":"LW rd, rs1, imm LW rd, imm(rs1) LW rd, var[index]", + "Operation":"rd = M[rs1 + imm] rd = var[index]", + "Notes":"Load four bytes. rd is sign extended to 32 bits", + "Format":"I-type" + }, + { + "Instruction":"LBU rd, rs1, imm LBU rd, imm(rs1) LBU rd, var[index]", + "Operation":"rd = M[rs1 + imm] rd = var[index]", + "Notes":"Load byte", + "Format":"I-type" + }, + { + "Instruction":"LHU rd, rs1, imm LHU rd, imm(rs1) LHU rd, var[index]", + "Operation":"rd = M[rs1 + imm] rd = var[index]", + "Notes":"Load two bytes", + "Format":"I-type" + }, + { + "Instruction":"JALR rd, rs1, imm", + "Operation":"rd = PC + 4; PC = rs1 + imm", + "Notes":"Jump and link register. rd is set to the address of the instruction following the jump. The jump target is rs1 + imm with the least significant bit cleared.", + "Format":"I-type" + }, + { + "Instruction":"ECALL", + "Operation":"environment call", + "Notes":"See section ECALLs.", + "Format":"I-type" + }, + { + "Instruction":"SB rs1, rs2, imm SB rs1, imm(rs2) SB rs1, var[index], rs2", + "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", + "Notes":"Store byte. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", + "Format":"S-type" + }, + { + "Instruction":"SH rs1, rs2, imm SH rs1, imm(rs2) SH rs1, var[index], rs2", + "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", + "Notes":"Store two bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", + "Format":"S-type" + }, + { + "Instruction":"SW rs1, rs2, imm SW rs1, imm(rs2) SW rs1, var[index], rs2", + "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", + "Notes":"Store four bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", + "Format":"S-type" + }, + { + "Instruction":"BEQ rs1, rs2, imm BEQ rs1, rs2, label+offset", + "Operation":"if (rs1 == rs2) PC = PC + imm", + "Notes":"Branch if equal", + "Format":"B-type" + }, + { + "Instruction":"BNE rs1, rs2, imm BNE rs1, rs2, label+offset", + "Operation":"if (rs1 != rs2) PC = PC + imm", + "Notes":"Branch if not equal", + "Format":"B-type" + }, + { + "Instruction":"BLT rs1, rs2, imm BLT rs1, rs2, label+offset", + "Operation":"if (rs1 =s rs2) PC = PC + imm", + "Notes":"Branch if greater than or equal", + "Format":"B-type" + }, + { + "Instruction":"BLTU rs1, rs2, imm BLTU rs1, rs2, label+offset", + "Operation":"if (rs1 =u rs2) PC = PC + imm", + "Notes":"Branch if greater than or equal (unsigned)", + "Format":"B-type" + }, + { + "Instruction":"LUI rd, imm", + "Operation":"rd = imm << 12", + "Notes":null, + "Format":"U" + }, + { + "Instruction":"AUIPC rd, imm", + "Operation":"rd = PC + (imm << 12)", + "Notes":null, + "Format":"U" + }, + { + "Instruction":"JAL rd, addr JAL rd, label+offset", + "Operation":"rd = PC + 4; PC = addr", + "Notes":"Jump and link. rd is set to the address of the instruction following the jump.", + "Format":"J-type" + }, + { + "Instruction":"CSRRW rd, csr, rs1", + "Operation":"rd = csr; csr = rs1", + "Notes":"Atomic read\/write", + "Format":"CSR" + }, + { + "Instruction":"CSRRS rd, csr, rs1", + "Operation":"rd = csr; csr = csr | rs1", + "Notes":"Atomic read\/set. rs1 serves as a bit mask", + "Format":"CSR" + }, + { + "Instruction":"CSRRC rd, csr, rs1", + "Operation":"rd = csr; csr = csr & ~rs1", + "Notes":"Atomic read\/clear. rs1 serves as a bit mask", + "Format":"CSR" + }, + { + "Instruction":"CSRRWI rd, csr, uimm", + "Operation":"rd = csr; csr = uimm", + "Notes":"Atomic read\/write", + "Format":"CSR" + }, + { + "Instruction":"CSRRSI rd, csr, uimm", + "Operation":"rd = csr; csr = csr | uimm", + "Notes":"Atomic read\/set. uimm serves as a bit mask", + "Format":"CSR" + }, + { + "Instruction":"CSRRCI rd, csr, uimm", + "Operation":"rd = csr; csr = csr & ~uimm", + "Notes":"Atomic read\/clear. uimm serves as a bit mask", + "Format":"CSR" + }, + { + "Instruction":"NOP", + "Operation":"-", + "Notes":"No operation. Translated to ADDI x0, x0, 0", + "Format":"Pseudo" + }, + { + "Instruction":"LA rd, var[index]", + "Operation":"rd = &var[index]", + "Notes":"Load variable address into rd", + "Format":"Pseudo" + }, + { + "Instruction":"LI rd, imm", + "Operation":"rd = imm", + "Notes":"Load 32 bit immediate into rd", + "Format":"Pseudo" + }, + { + "Instruction":"MV rd, rs", + "Operation":"rd = rs", + "Notes":"Translated to ADDI rd, rs, 0", + "Format":"Pseudo" + } +] From 7b4132d81f3c843f93a0f89f7c317c03c35552f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Richard=20M=C3=BCller?= Date: Fri, 26 Apr 2024 10:53:44 +0200 Subject: [PATCH 062/138] Added flushes for ecall exit --- architecture_simulator/uarch/riscv/stages.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/architecture_simulator/uarch/riscv/stages.py b/architecture_simulator/uarch/riscv/stages.py index f1944ad..023de5a 100644 --- a/architecture_simulator/uarch/riscv/stages.py +++ b/architecture_simulator/uarch/riscv/stages.py @@ -238,6 +238,7 @@ def behavior( # ECALL needs some special behavior (flush and print to output) stall_signal = None exit_code = None + flush_signal = None # Needed for exiting the simulation (ecall 10/93) if isinstance(pipeline_register.instruction, ECALL): # assume that all further stages need to be empty, unless this stage is already stalled and the value of the next register is only for display purposes for other_pr in pipeline_registers[ @@ -255,6 +256,10 @@ def behavior( state.output += ecall_result elif type(ecall_result) is int: exit_code = ecall_result + assert pipeline_register.pc_plus_instruction_length is not None + flush_signal = FlushSignal( + False, pipeline_register.pc_plus_instruction_length + ) return ExecutePipelineRegister( stall_signal=stall_signal, @@ -273,6 +278,7 @@ def behavior( pc_plus_instruction_length=pipeline_register.pc_plus_instruction_length, address_of_instruction=pipeline_register.address_of_instruction, exit_code=exit_code, + flush_signal=flush_signal, ) @@ -331,6 +337,12 @@ def behavior( flush_signal = FlushSignal( inclusive=False, address=pipeline_register.result ) + elif pipeline_register.exit_code is not None: + # Exit codes stem from ecalls which cannot cause branches and thus cannot generate other flush signals + assert pipeline_register.pc_plus_instruction_length is not None + flush_signal = FlushSignal( + False, pipeline_register.pc_plus_instruction_length + ) else: flush_signal = None @@ -409,7 +421,12 @@ def behavior( architectural_state=state, ) + flush_signal = None if pipeline_register.exit_code is not None: + assert pipeline_register.pc_plus_instruction_length is not None + flush_signal = FlushSignal( + False, pipeline_register.pc_plus_instruction_length + ) state.exit_code = pipeline_register.exit_code return RegisterWritebackPipelineRegister( @@ -422,6 +439,7 @@ def behavior( pc_plus_instruction_length=pipeline_register.pc_plus_instruction_length, imm=pipeline_register.imm, address_of_instruction=pipeline_register.address_of_instruction, + flush_signal=flush_signal, ) From 5d8b19e700958c34cb7d5c5450d5cfa512db60ce Mon Sep 17 00:00:00 2001 From: Michael Kuhn Date: Fri, 26 Apr 2024 11:18:55 +0200 Subject: [PATCH 063/138] format riscv help table --- webgui/src/components/riscv/RiscvHelp.vue | 10 +++++++- webgui/src/data/riscv_instructions.json | 30 +++++++++++------------ 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue index e472e3f..92266c9 100644 --- a/webgui/src/components/riscv/RiscvHelp.vue +++ b/webgui/src/components/riscv/RiscvHelp.vue @@ -21,7 +21,15 @@ - {{ item[field] }} + + {{ item[field] }} + +
{{ item[field] }}
diff --git a/webgui/src/data/riscv_instructions.json b/webgui/src/data/riscv_instructions.json index 1bb548c..9c8d4a3 100644 --- a/webgui/src/data/riscv_instructions.json +++ b/webgui/src/data/riscv_instructions.json @@ -162,31 +162,31 @@ "Format":"I-type" }, { - "Instruction":"LB rd, rs1, imm LB rd, imm(rs1) LB rd, var[index]", + "Instruction":"LB rd, rs1, imm\nLB rd, imm(rs1)\nLB rd, var[index]", "Operation":"rd = M[rs1 + imm] rd = var[index]", "Notes":"Load byte. rd is sign extended to 32 bits", "Format":"I-type" }, { - "Instruction":"LH rd, rs1, imm LH rd, imm(rs1) LH rd, var[index]", + "Instruction":"LH rd, rs1, imm\nLH rd, imm(rs1)\nLH rd, var[index]", "Operation":"rd = M[rs1 + imm] rd = var[index]", "Notes":"Load two bytes. rd is sign extended to 32 bits", "Format":"I-type" }, { - "Instruction":"LW rd, rs1, imm LW rd, imm(rs1) LW rd, var[index]", + "Instruction":"LW rd, rs1, imm\nLW rd, imm(rs1)\nLW rd, var[index]", "Operation":"rd = M[rs1 + imm] rd = var[index]", "Notes":"Load four bytes. rd is sign extended to 32 bits", "Format":"I-type" }, { - "Instruction":"LBU rd, rs1, imm LBU rd, imm(rs1) LBU rd, var[index]", + "Instruction":"LBU rd, rs1, imm\nLBU rd, imm(rs1)\nLBU rd, var[index]", "Operation":"rd = M[rs1 + imm] rd = var[index]", "Notes":"Load byte", "Format":"I-type" }, { - "Instruction":"LHU rd, rs1, imm LHU rd, imm(rs1) LHU rd, var[index]", + "Instruction":"LHU rd, rs1, imm\nLHU rd, imm(rs1)\nLHU rd, var[index]", "Operation":"rd = M[rs1 + imm] rd = var[index]", "Notes":"Load two bytes", "Format":"I-type" @@ -204,55 +204,55 @@ "Format":"I-type" }, { - "Instruction":"SB rs1, rs2, imm SB rs1, imm(rs2) SB rs1, var[index], rs2", + "Instruction":"SB rs1, rs2, imm\nSB rs1, imm(rs2)\nSB rs1, var[index], rs2", "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", "Notes":"Store byte. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", "Format":"S-type" }, { - "Instruction":"SH rs1, rs2, imm SH rs1, imm(rs2) SH rs1, var[index], rs2", + "Instruction":"SH rs1, rs2, imm\nSH rs1, imm(rs2)\nSH rs1, var[index], rs2", "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", "Notes":"Store two bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", "Format":"S-type" }, { - "Instruction":"SW rs1, rs2, imm SW rs1, imm(rs2) SW rs1, var[index], rs2", + "Instruction":"SW rs1, rs2, imm\nSW rs1, imm(rs2)\nSW rs1, var[index], rs2", "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", "Notes":"Store four bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", "Format":"S-type" }, { - "Instruction":"BEQ rs1, rs2, imm BEQ rs1, rs2, label+offset", + "Instruction":"BEQ rs1, rs2, imm\nBEQ rs1, rs2, label+offset", "Operation":"if (rs1 == rs2) PC = PC + imm", "Notes":"Branch if equal", "Format":"B-type" }, { - "Instruction":"BNE rs1, rs2, imm BNE rs1, rs2, label+offset", + "Instruction":"BNE rs1, rs2, imm\nBNE rs1, rs2, label+offset", "Operation":"if (rs1 != rs2) PC = PC + imm", "Notes":"Branch if not equal", "Format":"B-type" }, { - "Instruction":"BLT rs1, rs2, imm BLT rs1, rs2, label+offset", + "Instruction":"BLT rs1, rs2, imm\nBLT rs1, rs2, label+offset", "Operation":"if (rs1 =s rs2) PC = PC + imm", "Notes":"Branch if greater than or equal", "Format":"B-type" }, { - "Instruction":"BLTU rs1, rs2, imm BLTU rs1, rs2, label+offset", + "Instruction":"BLTU rs1, rs2, imm\nBLTU rs1, rs2, label+offset", "Operation":"if (rs1 =u rs2) PC = PC + imm", "Notes":"Branch if greater than or equal (unsigned)", "Format":"B-type" @@ -270,7 +270,7 @@ "Format":"U" }, { - "Instruction":"JAL rd, addr JAL rd, label+offset", + "Instruction":"JAL rd, addr\nJAL rd, label+offset", "Operation":"rd = PC + 4; PC = addr", "Notes":"Jump and link. rd is set to the address of the instruction following the jump.", "Format":"J-type" From b777a5c4839e5ca25541b1ce8b46b97826605b34 Mon Sep 17 00:00:00 2001 From: Michael Kuhn Date: Fri, 26 Apr 2024 11:31:24 +0200 Subject: [PATCH 064/138] complete instruction formats --- webgui/src/data/riscv_instructions.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/webgui/src/data/riscv_instructions.json b/webgui/src/data/riscv_instructions.json index 9c8d4a3..5af1f0e 100644 --- a/webgui/src/data/riscv_instructions.json +++ b/webgui/src/data/riscv_instructions.json @@ -261,13 +261,13 @@ "Instruction":"LUI rd, imm", "Operation":"rd = imm << 12", "Notes":null, - "Format":"U" + "Format":"U-type" }, { "Instruction":"AUIPC rd, imm", "Operation":"rd = PC + (imm << 12)", "Notes":null, - "Format":"U" + "Format":"U-type" }, { "Instruction":"JAL rd, addr\nJAL rd, label+offset", From 763c453b77cdc5f6ab52d5a651fd202f75bb146a Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Fri, 26 Apr 2024 12:08:27 +0200 Subject: [PATCH 065/138] put tables into component --- webgui/src/components/riscv/RiscvHelp.vue | 52 +- .../src/components/riscv/RiscvHelpTable.vue | 28 + webgui/src/data/riscv_instructions.json | 679 +++++++++--------- 3 files changed, 375 insertions(+), 384 deletions(-) create mode 100644 webgui/src/components/riscv/RiscvHelpTable.vue diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue index 92266c9..d694144 100644 --- a/webgui/src/components/riscv/RiscvHelp.vue +++ b/webgui/src/components/riscv/RiscvHelp.vue @@ -1,4 +1,9 @@ + - diff --git a/webgui/src/components/riscv/RiscvHelpTable.vue b/webgui/src/components/riscv/RiscvHelpTable.vue new file mode 100644 index 0000000..39d3a2a --- /dev/null +++ b/webgui/src/components/riscv/RiscvHelpTable.vue @@ -0,0 +1,28 @@ + + diff --git a/webgui/src/data/riscv_instructions.json b/webgui/src/data/riscv_instructions.json index 9c8d4a3..ec98eaa 100644 --- a/webgui/src/data/riscv_instructions.json +++ b/webgui/src/data/riscv_instructions.json @@ -1,338 +1,341 @@ -[ - { - "Instruction":"ADD rd, rs1, rs2", - "Operation":"rd = rs1 + rs2", - "Notes":null, - "Format":"R-type" - }, - { - "Instruction":"SUB rd, rs1, rs2", - "Operation":"rd = rs1 - rs2", - "Notes":null, - "Format":"R-type" - }, - { - "Instruction":"SLL rd, rs1, rs2", - "Operation":"rd = rs1 << rs2", - "Notes":null, - "Format":"R-type" - }, - { - "Instruction":"SRL rd, rs1, rs2", - "Operation":"rd = rs1 >> rs2", - "Notes":"Logical right shift", - "Format":"R-type" - }, - { - "Instruction":"SRA rd, rs1, rs2", - "Operation":"rd = rs1 >>a rs2", - "Notes":"Arithmetic right shift", - "Format":"R-type" - }, - { - "Instruction":"SLT rd, rs1, rs2", - "Operation":"rd = rs1 > imm", - "Notes":"Logical right shift. imm is unsigned, with a length of 5 bits", - "Format":"I-type" - }, - { - "Instruction":"SRAI rd, rs1, imm", - "Operation":"rd = rs1 >>a imm", - "Notes":"Arithmetic right shift. imm is unsigned, with a length of 5 bits", - "Format":"I-type" - }, - { - "Instruction":"LB rd, rs1, imm\nLB rd, imm(rs1)\nLB rd, var[index]", - "Operation":"rd = M[rs1 + imm] rd = var[index]", - "Notes":"Load byte. rd is sign extended to 32 bits", - "Format":"I-type" - }, - { - "Instruction":"LH rd, rs1, imm\nLH rd, imm(rs1)\nLH rd, var[index]", - "Operation":"rd = M[rs1 + imm] rd = var[index]", - "Notes":"Load two bytes. rd is sign extended to 32 bits", - "Format":"I-type" - }, - { - "Instruction":"LW rd, rs1, imm\nLW rd, imm(rs1)\nLW rd, var[index]", - "Operation":"rd = M[rs1 + imm] rd = var[index]", - "Notes":"Load four bytes. rd is sign extended to 32 bits", - "Format":"I-type" - }, - { - "Instruction":"LBU rd, rs1, imm\nLBU rd, imm(rs1)\nLBU rd, var[index]", - "Operation":"rd = M[rs1 + imm] rd = var[index]", - "Notes":"Load byte", - "Format":"I-type" - }, - { - "Instruction":"LHU rd, rs1, imm\nLHU rd, imm(rs1)\nLHU rd, var[index]", - "Operation":"rd = M[rs1 + imm] rd = var[index]", - "Notes":"Load two bytes", - "Format":"I-type" - }, - { - "Instruction":"JALR rd, rs1, imm", - "Operation":"rd = PC + 4; PC = rs1 + imm", - "Notes":"Jump and link register. rd is set to the address of the instruction following the jump. The jump target is rs1 + imm with the least significant bit cleared.", - "Format":"I-type" - }, - { - "Instruction":"ECALL", - "Operation":"environment call", - "Notes":"See section ECALLs.", - "Format":"I-type" - }, - { - "Instruction":"SB rs1, rs2, imm\nSB rs1, imm(rs2)\nSB rs1, var[index], rs2", - "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", - "Notes":"Store byte. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", - "Format":"S-type" - }, - { - "Instruction":"SH rs1, rs2, imm\nSH rs1, imm(rs2)\nSH rs1, var[index], rs2", - "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", - "Notes":"Store two bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", - "Format":"S-type" - }, - { - "Instruction":"SW rs1, rs2, imm\nSW rs1, imm(rs2)\nSW rs1, var[index], rs2", - "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", - "Notes":"Store four bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", - "Format":"S-type" - }, - { - "Instruction":"BEQ rs1, rs2, imm\nBEQ rs1, rs2, label+offset", - "Operation":"if (rs1 == rs2) PC = PC + imm", - "Notes":"Branch if equal", - "Format":"B-type" - }, - { - "Instruction":"BNE rs1, rs2, imm\nBNE rs1, rs2, label+offset", - "Operation":"if (rs1 != rs2) PC = PC + imm", - "Notes":"Branch if not equal", - "Format":"B-type" - }, - { - "Instruction":"BLT rs1, rs2, imm\nBLT rs1, rs2, label+offset", - "Operation":"if (rs1 =s rs2) PC = PC + imm", - "Notes":"Branch if greater than or equal", - "Format":"B-type" - }, - { - "Instruction":"BLTU rs1, rs2, imm\nBLTU rs1, rs2, label+offset", - "Operation":"if (rs1 =u rs2) PC = PC + imm", - "Notes":"Branch if greater than or equal (unsigned)", - "Format":"B-type" - }, - { - "Instruction":"LUI rd, imm", - "Operation":"rd = imm << 12", - "Notes":null, - "Format":"U" - }, - { - "Instruction":"AUIPC rd, imm", - "Operation":"rd = PC + (imm << 12)", - "Notes":null, - "Format":"U" - }, - { - "Instruction":"JAL rd, addr\nJAL rd, label+offset", - "Operation":"rd = PC + 4; PC = addr", - "Notes":"Jump and link. rd is set to the address of the instruction following the jump.", - "Format":"J-type" - }, - { - "Instruction":"CSRRW rd, csr, rs1", - "Operation":"rd = csr; csr = rs1", - "Notes":"Atomic read\/write", - "Format":"CSR" - }, - { - "Instruction":"CSRRS rd, csr, rs1", - "Operation":"rd = csr; csr = csr | rs1", - "Notes":"Atomic read\/set. rs1 serves as a bit mask", - "Format":"CSR" - }, - { - "Instruction":"CSRRC rd, csr, rs1", - "Operation":"rd = csr; csr = csr & ~rs1", - "Notes":"Atomic read\/clear. rs1 serves as a bit mask", - "Format":"CSR" - }, - { - "Instruction":"CSRRWI rd, csr, uimm", - "Operation":"rd = csr; csr = uimm", - "Notes":"Atomic read\/write", - "Format":"CSR" - }, - { - "Instruction":"CSRRSI rd, csr, uimm", - "Operation":"rd = csr; csr = csr | uimm", - "Notes":"Atomic read\/set. uimm serves as a bit mask", - "Format":"CSR" - }, - { - "Instruction":"CSRRCI rd, csr, uimm", - "Operation":"rd = csr; csr = csr & ~uimm", - "Notes":"Atomic read\/clear. uimm serves as a bit mask", - "Format":"CSR" - }, - { - "Instruction":"NOP", - "Operation":"-", - "Notes":"No operation. Translated to ADDI x0, x0, 0", - "Format":"Pseudo" - }, - { - "Instruction":"LA rd, var[index]", - "Operation":"rd = &var[index]", - "Notes":"Load variable address into rd", - "Format":"Pseudo" - }, - { - "Instruction":"LI rd, imm", - "Operation":"rd = imm", - "Notes":"Load 32 bit immediate into rd", - "Format":"Pseudo" - }, - { - "Instruction":"MV rd, rs", - "Operation":"rd = rs", - "Notes":"Translated to ADDI rd, rs, 0", - "Format":"Pseudo" - } -] +{ + "all": [ + { + "Instruction": "ADD rd, rs1, rs2", + "Operation": "rd = rs1 + rs2", + "Notes": null, + "Format": "R-type" + }, + { + "Instruction": "SUB rd, rs1, rs2", + "Operation": "rd = rs1 - rs2", + "Notes": null, + "Format": "R-type" + }, + { + "Instruction": "SLL rd, rs1, rs2", + "Operation": "rd = rs1 << rs2", + "Notes": null, + "Format": "R-type" + }, + { + "Instruction": "SRL rd, rs1, rs2", + "Operation": "rd = rs1 >> rs2", + "Notes": "Logical right shift", + "Format": "R-type" + }, + { + "Instruction": "SRA rd, rs1, rs2", + "Operation": "rd = rs1 >>a rs2", + "Notes": "Arithmetic right shift", + "Format": "R-type" + }, + { + "Instruction": "SLT rd, rs1, rs2", + "Operation": "rd = rs1 > imm", + "Notes": "Logical right shift. imm is unsigned, with a length of 5 bits", + "Format": "I-type" + }, + { + "Instruction": "SRAI rd, rs1, imm", + "Operation": "rd = rs1 >>a imm", + "Notes": "Arithmetic right shift. imm is unsigned, with a length of 5 bits", + "Format": "I-type" + }, + { + "Instruction": "LB rd, rs1, imm\nLB rd, imm(rs1)\nLB rd, var[index]", + "Operation": "rd = M[rs1 + imm] rd = var[index]", + "Notes": "Load byte. rd is sign extended to 32 bits", + "Format": "I-type" + }, + { + "Instruction": "LH rd, rs1, imm\nLH rd, imm(rs1)\nLH rd, var[index]", + "Operation": "rd = M[rs1 + imm] rd = var[index]", + "Notes": "Load two bytes. rd is sign extended to 32 bits", + "Format": "I-type" + }, + { + "Instruction": "LW rd, rs1, imm\nLW rd, imm(rs1)\nLW rd, var[index]", + "Operation": "rd = M[rs1 + imm] rd = var[index]", + "Notes": "Load four bytes. rd is sign extended to 32 bits", + "Format": "I-type" + }, + { + "Instruction": "LBU rd, rs1, imm\nLBU rd, imm(rs1)\nLBU rd, var[index]", + "Operation": "rd = M[rs1 + imm] rd = var[index]", + "Notes": "Load byte", + "Format": "I-type" + }, + { + "Instruction": "LHU rd, rs1, imm\nLHU rd, imm(rs1)\nLHU rd, var[index]", + "Operation": "rd = M[rs1 + imm] rd = var[index]", + "Notes": "Load two bytes", + "Format": "I-type" + }, + { + "Instruction": "JALR rd, rs1, imm", + "Operation": "rd = PC + 4; PC = rs1 + imm", + "Notes": "Jump and link register. rd is set to the address of the instruction following the jump. The jump target is rs1 + imm with the least significant bit cleared.", + "Format": "I-type" + }, + { + "Instruction": "ECALL", + "Operation": "environment call", + "Notes": "See section ECALLs.", + "Format": "I-type" + }, + { + "Instruction": "SB rs1, rs2, imm\nSB rs1, imm(rs2)\nSB rs1, var[index], rs2", + "Operation": "M[rs2 + imm] = rs1 var[index] = rs1", + "Notes": "Store byte. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", + "Format": "S-type" + }, + { + "Instruction": "SH rs1, rs2, imm\nSH rs1, imm(rs2)\nSH rs1, var[index], rs2", + "Operation": "M[rs2 + imm] = rs1 var[index] = rs1", + "Notes": "Store two bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", + "Format": "S-type" + }, + { + "Instruction": "SW rs1, rs2, imm\nSW rs1, imm(rs2)\nSW rs1, var[index], rs2", + "Operation": "M[rs2 + imm] = rs1 var[index] = rs1", + "Notes": "Store four bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", + "Format": "S-type" + }, + { + "Instruction": "BEQ rs1, rs2, imm\nBEQ rs1, rs2, label+offset", + "Operation": "if (rs1 == rs2) PC = PC + imm", + "Notes": "Branch if equal", + "Format": "B-type" + }, + { + "Instruction": "BNE rs1, rs2, imm\nBNE rs1, rs2, label+offset", + "Operation": "if (rs1 != rs2) PC = PC + imm", + "Notes": "Branch if not equal", + "Format": "B-type" + }, + { + "Instruction": "BLT rs1, rs2, imm\nBLT rs1, rs2, label+offset", + "Operation": "if (rs1 =s rs2) PC = PC + imm", + "Notes": "Branch if greater than or equal", + "Format": "B-type" + }, + { + "Instruction": "BLTU rs1, rs2, imm\nBLTU rs1, rs2, label+offset", + "Operation": "if (rs1 =u rs2) PC = PC + imm", + "Notes": "Branch if greater than or equal (unsigned)", + "Format": "B-type" + }, + { + "Instruction": "LUI rd, imm", + "Operation": "rd = imm << 12", + "Notes": null, + "Format": "U" + }, + { + "Instruction": "AUIPC rd, imm", + "Operation": "rd = PC + (imm << 12)", + "Notes": null, + "Format": "U" + }, + { + "Instruction": "JAL rd, addr\nJAL rd, label+offset", + "Operation": "rd = PC + 4; PC = addr", + "Notes": "Jump and link. rd is set to the address of the instruction following the jump.", + "Format": "J-type" + }, + { + "Instruction": "CSRRW rd, csr, rs1", + "Operation": "rd = csr; csr = rs1", + "Notes": "Atomic read/write", + "Format": "CSR" + }, + { + "Instruction": "CSRRS rd, csr, rs1", + "Operation": "rd = csr; csr = csr | rs1", + "Notes": "Atomic read/set. rs1 serves as a bit mask", + "Format": "CSR" + }, + { + "Instruction": "CSRRC rd, csr, rs1", + "Operation": "rd = csr; csr = csr & ~rs1", + "Notes": "Atomic read/clear. rs1 serves as a bit mask", + "Format": "CSR" + }, + { + "Instruction": "CSRRWI rd, csr, uimm", + "Operation": "rd = csr; csr = uimm", + "Notes": "Atomic read/write", + "Format": "CSR" + }, + { + "Instruction": "CSRRSI rd, csr, uimm", + "Operation": "rd = csr; csr = csr | uimm", + "Notes": "Atomic read/set. uimm serves as a bit mask", + "Format": "CSR" + }, + { + "Instruction": "CSRRCI rd, csr, uimm", + "Operation": "rd = csr; csr = csr & ~uimm", + "Notes": "Atomic read/clear. uimm serves as a bit mask", + "Format": "CSR" + }, + { + "Instruction": "NOP", + "Operation": "-", + "Notes": "No operation. Translated to ADDI x0, x0, 0", + "Format": "Pseudo" + }, + { + "Instruction": "LA rd, var[index]", + "Operation": "rd = &var[index]", + "Notes": "Load variable address into rd", + "Format": "Pseudo" + }, + { + "Instruction": "LI rd, imm", + "Operation": "rd = imm", + "Notes": "Load 32 bit immediate into rd", + "Format": "Pseudo" + }, + { + "Instruction": "MV rd, rs", + "Operation": "rd = rs", + "Notes": "Translated to ADDI rd, rs, 0", + "Format": "Pseudo" + } + ], + "other": [] +} From fcfd9a61df41539faa49a3041d0f34aba64298f3 Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Fri, 26 Apr 2024 12:32:16 +0200 Subject: [PATCH 066/138] split instructions into sections --- webgui/src/components/riscv/RiscvHelp.vue | 1135 +-------------------- webgui/src/data/riscv_instructions.json | 107 +- 2 files changed, 99 insertions(+), 1143 deletions(-) diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue index d694144..c7069d8 100644 --- a/webgui/src/components/riscv/RiscvHelp.vue +++ b/webgui/src/components/riscv/RiscvHelp.vue @@ -2,7 +2,6 @@ From 8a01b7c97eab17d8bd48992ded4d89296bd4bd7a Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Thu, 25 Apr 2024 19:15:04 +0200 Subject: [PATCH 078/138] finish accordion riscv help page --- webgui/src/components/riscv/RiscvHelp.vue | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue index f8e53b0..c2b16dc 100644 --- a/webgui/src/components/riscv/RiscvHelp.vue +++ b/webgui/src/components/riscv/RiscvHelp.vue @@ -7,8 +7,8 @@ This simulator supports a subset of the RISC-V32 ISA. The supported instructions are listed below.

- -
+ +

- -

Other

- -
+ +

Other

+ +

@@ -1479,5 +1480,4 @@ addi x3, x3, 1 # This line is never reached

- From 5784fef7eaf0b65c41d96c4f9e3568e0d4e4d274 Mon Sep 17 00:00:00 2001 From: Michael Kuhn Date: Fri, 26 Apr 2024 10:45:49 +0200 Subject: [PATCH 079/138] generate riscv instruction table from json data --- webgui/src/components/riscv/RiscvHelp.vue | 39 +++ webgui/src/data/riscv_instructions.json | 338 ++++++++++++++++++++++ 2 files changed, 377 insertions(+) create mode 100644 webgui/src/data/riscv_instructions.json diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue index c2b16dc..e472e3f 100644 --- a/webgui/src/components/riscv/RiscvHelp.vue +++ b/webgui/src/components/riscv/RiscvHelp.vue @@ -8,6 +8,25 @@ instructions are listed below.

+ + + + + + + + + + + + + +
+ {{ field }} +
+ {{ item[field] }} +
+

@@ -1481,3 +1500,23 @@ addi x3, x3, 1 # This line is never reached

+ diff --git a/webgui/src/data/riscv_instructions.json b/webgui/src/data/riscv_instructions.json new file mode 100644 index 0000000..1bb548c --- /dev/null +++ b/webgui/src/data/riscv_instructions.json @@ -0,0 +1,338 @@ +[ + { + "Instruction":"ADD rd, rs1, rs2", + "Operation":"rd = rs1 + rs2", + "Notes":null, + "Format":"R-type" + }, + { + "Instruction":"SUB rd, rs1, rs2", + "Operation":"rd = rs1 - rs2", + "Notes":null, + "Format":"R-type" + }, + { + "Instruction":"SLL rd, rs1, rs2", + "Operation":"rd = rs1 << rs2", + "Notes":null, + "Format":"R-type" + }, + { + "Instruction":"SRL rd, rs1, rs2", + "Operation":"rd = rs1 >> rs2", + "Notes":"Logical right shift", + "Format":"R-type" + }, + { + "Instruction":"SRA rd, rs1, rs2", + "Operation":"rd = rs1 >>a rs2", + "Notes":"Arithmetic right shift", + "Format":"R-type" + }, + { + "Instruction":"SLT rd, rs1, rs2", + "Operation":"rd = rs1 > imm", + "Notes":"Logical right shift. imm is unsigned, with a length of 5 bits", + "Format":"I-type" + }, + { + "Instruction":"SRAI rd, rs1, imm", + "Operation":"rd = rs1 >>a imm", + "Notes":"Arithmetic right shift. imm is unsigned, with a length of 5 bits", + "Format":"I-type" + }, + { + "Instruction":"LB rd, rs1, imm LB rd, imm(rs1) LB rd, var[index]", + "Operation":"rd = M[rs1 + imm] rd = var[index]", + "Notes":"Load byte. rd is sign extended to 32 bits", + "Format":"I-type" + }, + { + "Instruction":"LH rd, rs1, imm LH rd, imm(rs1) LH rd, var[index]", + "Operation":"rd = M[rs1 + imm] rd = var[index]", + "Notes":"Load two bytes. rd is sign extended to 32 bits", + "Format":"I-type" + }, + { + "Instruction":"LW rd, rs1, imm LW rd, imm(rs1) LW rd, var[index]", + "Operation":"rd = M[rs1 + imm] rd = var[index]", + "Notes":"Load four bytes. rd is sign extended to 32 bits", + "Format":"I-type" + }, + { + "Instruction":"LBU rd, rs1, imm LBU rd, imm(rs1) LBU rd, var[index]", + "Operation":"rd = M[rs1 + imm] rd = var[index]", + "Notes":"Load byte", + "Format":"I-type" + }, + { + "Instruction":"LHU rd, rs1, imm LHU rd, imm(rs1) LHU rd, var[index]", + "Operation":"rd = M[rs1 + imm] rd = var[index]", + "Notes":"Load two bytes", + "Format":"I-type" + }, + { + "Instruction":"JALR rd, rs1, imm", + "Operation":"rd = PC + 4; PC = rs1 + imm", + "Notes":"Jump and link register. rd is set to the address of the instruction following the jump. The jump target is rs1 + imm with the least significant bit cleared.", + "Format":"I-type" + }, + { + "Instruction":"ECALL", + "Operation":"environment call", + "Notes":"See section ECALLs.", + "Format":"I-type" + }, + { + "Instruction":"SB rs1, rs2, imm SB rs1, imm(rs2) SB rs1, var[index], rs2", + "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", + "Notes":"Store byte. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", + "Format":"S-type" + }, + { + "Instruction":"SH rs1, rs2, imm SH rs1, imm(rs2) SH rs1, var[index], rs2", + "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", + "Notes":"Store two bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", + "Format":"S-type" + }, + { + "Instruction":"SW rs1, rs2, imm SW rs1, imm(rs2) SW rs1, var[index], rs2", + "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", + "Notes":"Store four bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", + "Format":"S-type" + }, + { + "Instruction":"BEQ rs1, rs2, imm BEQ rs1, rs2, label+offset", + "Operation":"if (rs1 == rs2) PC = PC + imm", + "Notes":"Branch if equal", + "Format":"B-type" + }, + { + "Instruction":"BNE rs1, rs2, imm BNE rs1, rs2, label+offset", + "Operation":"if (rs1 != rs2) PC = PC + imm", + "Notes":"Branch if not equal", + "Format":"B-type" + }, + { + "Instruction":"BLT rs1, rs2, imm BLT rs1, rs2, label+offset", + "Operation":"if (rs1 =s rs2) PC = PC + imm", + "Notes":"Branch if greater than or equal", + "Format":"B-type" + }, + { + "Instruction":"BLTU rs1, rs2, imm BLTU rs1, rs2, label+offset", + "Operation":"if (rs1 =u rs2) PC = PC + imm", + "Notes":"Branch if greater than or equal (unsigned)", + "Format":"B-type" + }, + { + "Instruction":"LUI rd, imm", + "Operation":"rd = imm << 12", + "Notes":null, + "Format":"U" + }, + { + "Instruction":"AUIPC rd, imm", + "Operation":"rd = PC + (imm << 12)", + "Notes":null, + "Format":"U" + }, + { + "Instruction":"JAL rd, addr JAL rd, label+offset", + "Operation":"rd = PC + 4; PC = addr", + "Notes":"Jump and link. rd is set to the address of the instruction following the jump.", + "Format":"J-type" + }, + { + "Instruction":"CSRRW rd, csr, rs1", + "Operation":"rd = csr; csr = rs1", + "Notes":"Atomic read\/write", + "Format":"CSR" + }, + { + "Instruction":"CSRRS rd, csr, rs1", + "Operation":"rd = csr; csr = csr | rs1", + "Notes":"Atomic read\/set. rs1 serves as a bit mask", + "Format":"CSR" + }, + { + "Instruction":"CSRRC rd, csr, rs1", + "Operation":"rd = csr; csr = csr & ~rs1", + "Notes":"Atomic read\/clear. rs1 serves as a bit mask", + "Format":"CSR" + }, + { + "Instruction":"CSRRWI rd, csr, uimm", + "Operation":"rd = csr; csr = uimm", + "Notes":"Atomic read\/write", + "Format":"CSR" + }, + { + "Instruction":"CSRRSI rd, csr, uimm", + "Operation":"rd = csr; csr = csr | uimm", + "Notes":"Atomic read\/set. uimm serves as a bit mask", + "Format":"CSR" + }, + { + "Instruction":"CSRRCI rd, csr, uimm", + "Operation":"rd = csr; csr = csr & ~uimm", + "Notes":"Atomic read\/clear. uimm serves as a bit mask", + "Format":"CSR" + }, + { + "Instruction":"NOP", + "Operation":"-", + "Notes":"No operation. Translated to ADDI x0, x0, 0", + "Format":"Pseudo" + }, + { + "Instruction":"LA rd, var[index]", + "Operation":"rd = &var[index]", + "Notes":"Load variable address into rd", + "Format":"Pseudo" + }, + { + "Instruction":"LI rd, imm", + "Operation":"rd = imm", + "Notes":"Load 32 bit immediate into rd", + "Format":"Pseudo" + }, + { + "Instruction":"MV rd, rs", + "Operation":"rd = rs", + "Notes":"Translated to ADDI rd, rs, 0", + "Format":"Pseudo" + } +] From c15d7ae27c726110547c98a13c3a9b2d9a312419 Mon Sep 17 00:00:00 2001 From: Michael Kuhn Date: Fri, 26 Apr 2024 11:18:55 +0200 Subject: [PATCH 080/138] format riscv help table --- webgui/src/components/riscv/RiscvHelp.vue | 10 +++++++- webgui/src/data/riscv_instructions.json | 30 +++++++++++------------ 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue index e472e3f..92266c9 100644 --- a/webgui/src/components/riscv/RiscvHelp.vue +++ b/webgui/src/components/riscv/RiscvHelp.vue @@ -21,7 +21,15 @@ - {{ item[field] }} + + {{ item[field] }} + +
{{ item[field] }}
diff --git a/webgui/src/data/riscv_instructions.json b/webgui/src/data/riscv_instructions.json index 1bb548c..9c8d4a3 100644 --- a/webgui/src/data/riscv_instructions.json +++ b/webgui/src/data/riscv_instructions.json @@ -162,31 +162,31 @@ "Format":"I-type" }, { - "Instruction":"LB rd, rs1, imm LB rd, imm(rs1) LB rd, var[index]", + "Instruction":"LB rd, rs1, imm\nLB rd, imm(rs1)\nLB rd, var[index]", "Operation":"rd = M[rs1 + imm] rd = var[index]", "Notes":"Load byte. rd is sign extended to 32 bits", "Format":"I-type" }, { - "Instruction":"LH rd, rs1, imm LH rd, imm(rs1) LH rd, var[index]", + "Instruction":"LH rd, rs1, imm\nLH rd, imm(rs1)\nLH rd, var[index]", "Operation":"rd = M[rs1 + imm] rd = var[index]", "Notes":"Load two bytes. rd is sign extended to 32 bits", "Format":"I-type" }, { - "Instruction":"LW rd, rs1, imm LW rd, imm(rs1) LW rd, var[index]", + "Instruction":"LW rd, rs1, imm\nLW rd, imm(rs1)\nLW rd, var[index]", "Operation":"rd = M[rs1 + imm] rd = var[index]", "Notes":"Load four bytes. rd is sign extended to 32 bits", "Format":"I-type" }, { - "Instruction":"LBU rd, rs1, imm LBU rd, imm(rs1) LBU rd, var[index]", + "Instruction":"LBU rd, rs1, imm\nLBU rd, imm(rs1)\nLBU rd, var[index]", "Operation":"rd = M[rs1 + imm] rd = var[index]", "Notes":"Load byte", "Format":"I-type" }, { - "Instruction":"LHU rd, rs1, imm LHU rd, imm(rs1) LHU rd, var[index]", + "Instruction":"LHU rd, rs1, imm\nLHU rd, imm(rs1)\nLHU rd, var[index]", "Operation":"rd = M[rs1 + imm] rd = var[index]", "Notes":"Load two bytes", "Format":"I-type" @@ -204,55 +204,55 @@ "Format":"I-type" }, { - "Instruction":"SB rs1, rs2, imm SB rs1, imm(rs2) SB rs1, var[index], rs2", + "Instruction":"SB rs1, rs2, imm\nSB rs1, imm(rs2)\nSB rs1, var[index], rs2", "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", "Notes":"Store byte. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", "Format":"S-type" }, { - "Instruction":"SH rs1, rs2, imm SH rs1, imm(rs2) SH rs1, var[index], rs2", + "Instruction":"SH rs1, rs2, imm\nSH rs1, imm(rs2)\nSH rs1, var[index], rs2", "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", "Notes":"Store two bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", "Format":"S-type" }, { - "Instruction":"SW rs1, rs2, imm SW rs1, imm(rs2) SW rs1, var[index], rs2", + "Instruction":"SW rs1, rs2, imm\nSW rs1, imm(rs2)\nSW rs1, var[index], rs2", "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", "Notes":"Store four bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", "Format":"S-type" }, { - "Instruction":"BEQ rs1, rs2, imm BEQ rs1, rs2, label+offset", + "Instruction":"BEQ rs1, rs2, imm\nBEQ rs1, rs2, label+offset", "Operation":"if (rs1 == rs2) PC = PC + imm", "Notes":"Branch if equal", "Format":"B-type" }, { - "Instruction":"BNE rs1, rs2, imm BNE rs1, rs2, label+offset", + "Instruction":"BNE rs1, rs2, imm\nBNE rs1, rs2, label+offset", "Operation":"if (rs1 != rs2) PC = PC + imm", "Notes":"Branch if not equal", "Format":"B-type" }, { - "Instruction":"BLT rs1, rs2, imm BLT rs1, rs2, label+offset", + "Instruction":"BLT rs1, rs2, imm\nBLT rs1, rs2, label+offset", "Operation":"if (rs1 =s rs2) PC = PC + imm", "Notes":"Branch if greater than or equal", "Format":"B-type" }, { - "Instruction":"BLTU rs1, rs2, imm BLTU rs1, rs2, label+offset", + "Instruction":"BLTU rs1, rs2, imm\nBLTU rs1, rs2, label+offset", "Operation":"if (rs1 =u rs2) PC = PC + imm", "Notes":"Branch if greater than or equal (unsigned)", "Format":"B-type" @@ -270,7 +270,7 @@ "Format":"U" }, { - "Instruction":"JAL rd, addr JAL rd, label+offset", + "Instruction":"JAL rd, addr\nJAL rd, label+offset", "Operation":"rd = PC + 4; PC = addr", "Notes":"Jump and link. rd is set to the address of the instruction following the jump.", "Format":"J-type" From fd6ae1907b16b9c3fe76dfdefc15d0ce108fc165 Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Fri, 26 Apr 2024 12:08:27 +0200 Subject: [PATCH 081/138] put tables into component --- webgui/src/components/riscv/RiscvHelp.vue | 52 +- .../src/components/riscv/RiscvHelpTable.vue | 28 + webgui/src/data/riscv_instructions.json | 679 +++++++++--------- 3 files changed, 375 insertions(+), 384 deletions(-) create mode 100644 webgui/src/components/riscv/RiscvHelpTable.vue diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue index 92266c9..d694144 100644 --- a/webgui/src/components/riscv/RiscvHelp.vue +++ b/webgui/src/components/riscv/RiscvHelp.vue @@ -1,4 +1,9 @@ + - diff --git a/webgui/src/components/riscv/RiscvHelpTable.vue b/webgui/src/components/riscv/RiscvHelpTable.vue new file mode 100644 index 0000000..39d3a2a --- /dev/null +++ b/webgui/src/components/riscv/RiscvHelpTable.vue @@ -0,0 +1,28 @@ + + diff --git a/webgui/src/data/riscv_instructions.json b/webgui/src/data/riscv_instructions.json index 9c8d4a3..ec98eaa 100644 --- a/webgui/src/data/riscv_instructions.json +++ b/webgui/src/data/riscv_instructions.json @@ -1,338 +1,341 @@ -[ - { - "Instruction":"ADD rd, rs1, rs2", - "Operation":"rd = rs1 + rs2", - "Notes":null, - "Format":"R-type" - }, - { - "Instruction":"SUB rd, rs1, rs2", - "Operation":"rd = rs1 - rs2", - "Notes":null, - "Format":"R-type" - }, - { - "Instruction":"SLL rd, rs1, rs2", - "Operation":"rd = rs1 << rs2", - "Notes":null, - "Format":"R-type" - }, - { - "Instruction":"SRL rd, rs1, rs2", - "Operation":"rd = rs1 >> rs2", - "Notes":"Logical right shift", - "Format":"R-type" - }, - { - "Instruction":"SRA rd, rs1, rs2", - "Operation":"rd = rs1 >>a rs2", - "Notes":"Arithmetic right shift", - "Format":"R-type" - }, - { - "Instruction":"SLT rd, rs1, rs2", - "Operation":"rd = rs1 > imm", - "Notes":"Logical right shift. imm is unsigned, with a length of 5 bits", - "Format":"I-type" - }, - { - "Instruction":"SRAI rd, rs1, imm", - "Operation":"rd = rs1 >>a imm", - "Notes":"Arithmetic right shift. imm is unsigned, with a length of 5 bits", - "Format":"I-type" - }, - { - "Instruction":"LB rd, rs1, imm\nLB rd, imm(rs1)\nLB rd, var[index]", - "Operation":"rd = M[rs1 + imm] rd = var[index]", - "Notes":"Load byte. rd is sign extended to 32 bits", - "Format":"I-type" - }, - { - "Instruction":"LH rd, rs1, imm\nLH rd, imm(rs1)\nLH rd, var[index]", - "Operation":"rd = M[rs1 + imm] rd = var[index]", - "Notes":"Load two bytes. rd is sign extended to 32 bits", - "Format":"I-type" - }, - { - "Instruction":"LW rd, rs1, imm\nLW rd, imm(rs1)\nLW rd, var[index]", - "Operation":"rd = M[rs1 + imm] rd = var[index]", - "Notes":"Load four bytes. rd is sign extended to 32 bits", - "Format":"I-type" - }, - { - "Instruction":"LBU rd, rs1, imm\nLBU rd, imm(rs1)\nLBU rd, var[index]", - "Operation":"rd = M[rs1 + imm] rd = var[index]", - "Notes":"Load byte", - "Format":"I-type" - }, - { - "Instruction":"LHU rd, rs1, imm\nLHU rd, imm(rs1)\nLHU rd, var[index]", - "Operation":"rd = M[rs1 + imm] rd = var[index]", - "Notes":"Load two bytes", - "Format":"I-type" - }, - { - "Instruction":"JALR rd, rs1, imm", - "Operation":"rd = PC + 4; PC = rs1 + imm", - "Notes":"Jump and link register. rd is set to the address of the instruction following the jump. The jump target is rs1 + imm with the least significant bit cleared.", - "Format":"I-type" - }, - { - "Instruction":"ECALL", - "Operation":"environment call", - "Notes":"See section ECALLs.", - "Format":"I-type" - }, - { - "Instruction":"SB rs1, rs2, imm\nSB rs1, imm(rs2)\nSB rs1, var[index], rs2", - "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", - "Notes":"Store byte. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", - "Format":"S-type" - }, - { - "Instruction":"SH rs1, rs2, imm\nSH rs1, imm(rs2)\nSH rs1, var[index], rs2", - "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", - "Notes":"Store two bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", - "Format":"S-type" - }, - { - "Instruction":"SW rs1, rs2, imm\nSW rs1, imm(rs2)\nSW rs1, var[index], rs2", - "Operation":"M[rs2 + imm] = rs1 var[index] = rs1", - "Notes":"Store four bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", - "Format":"S-type" - }, - { - "Instruction":"BEQ rs1, rs2, imm\nBEQ rs1, rs2, label+offset", - "Operation":"if (rs1 == rs2) PC = PC + imm", - "Notes":"Branch if equal", - "Format":"B-type" - }, - { - "Instruction":"BNE rs1, rs2, imm\nBNE rs1, rs2, label+offset", - "Operation":"if (rs1 != rs2) PC = PC + imm", - "Notes":"Branch if not equal", - "Format":"B-type" - }, - { - "Instruction":"BLT rs1, rs2, imm\nBLT rs1, rs2, label+offset", - "Operation":"if (rs1 =s rs2) PC = PC + imm", - "Notes":"Branch if greater than or equal", - "Format":"B-type" - }, - { - "Instruction":"BLTU rs1, rs2, imm\nBLTU rs1, rs2, label+offset", - "Operation":"if (rs1 =u rs2) PC = PC + imm", - "Notes":"Branch if greater than or equal (unsigned)", - "Format":"B-type" - }, - { - "Instruction":"LUI rd, imm", - "Operation":"rd = imm << 12", - "Notes":null, - "Format":"U" - }, - { - "Instruction":"AUIPC rd, imm", - "Operation":"rd = PC + (imm << 12)", - "Notes":null, - "Format":"U" - }, - { - "Instruction":"JAL rd, addr\nJAL rd, label+offset", - "Operation":"rd = PC + 4; PC = addr", - "Notes":"Jump and link. rd is set to the address of the instruction following the jump.", - "Format":"J-type" - }, - { - "Instruction":"CSRRW rd, csr, rs1", - "Operation":"rd = csr; csr = rs1", - "Notes":"Atomic read\/write", - "Format":"CSR" - }, - { - "Instruction":"CSRRS rd, csr, rs1", - "Operation":"rd = csr; csr = csr | rs1", - "Notes":"Atomic read\/set. rs1 serves as a bit mask", - "Format":"CSR" - }, - { - "Instruction":"CSRRC rd, csr, rs1", - "Operation":"rd = csr; csr = csr & ~rs1", - "Notes":"Atomic read\/clear. rs1 serves as a bit mask", - "Format":"CSR" - }, - { - "Instruction":"CSRRWI rd, csr, uimm", - "Operation":"rd = csr; csr = uimm", - "Notes":"Atomic read\/write", - "Format":"CSR" - }, - { - "Instruction":"CSRRSI rd, csr, uimm", - "Operation":"rd = csr; csr = csr | uimm", - "Notes":"Atomic read\/set. uimm serves as a bit mask", - "Format":"CSR" - }, - { - "Instruction":"CSRRCI rd, csr, uimm", - "Operation":"rd = csr; csr = csr & ~uimm", - "Notes":"Atomic read\/clear. uimm serves as a bit mask", - "Format":"CSR" - }, - { - "Instruction":"NOP", - "Operation":"-", - "Notes":"No operation. Translated to ADDI x0, x0, 0", - "Format":"Pseudo" - }, - { - "Instruction":"LA rd, var[index]", - "Operation":"rd = &var[index]", - "Notes":"Load variable address into rd", - "Format":"Pseudo" - }, - { - "Instruction":"LI rd, imm", - "Operation":"rd = imm", - "Notes":"Load 32 bit immediate into rd", - "Format":"Pseudo" - }, - { - "Instruction":"MV rd, rs", - "Operation":"rd = rs", - "Notes":"Translated to ADDI rd, rs, 0", - "Format":"Pseudo" - } -] +{ + "all": [ + { + "Instruction": "ADD rd, rs1, rs2", + "Operation": "rd = rs1 + rs2", + "Notes": null, + "Format": "R-type" + }, + { + "Instruction": "SUB rd, rs1, rs2", + "Operation": "rd = rs1 - rs2", + "Notes": null, + "Format": "R-type" + }, + { + "Instruction": "SLL rd, rs1, rs2", + "Operation": "rd = rs1 << rs2", + "Notes": null, + "Format": "R-type" + }, + { + "Instruction": "SRL rd, rs1, rs2", + "Operation": "rd = rs1 >> rs2", + "Notes": "Logical right shift", + "Format": "R-type" + }, + { + "Instruction": "SRA rd, rs1, rs2", + "Operation": "rd = rs1 >>a rs2", + "Notes": "Arithmetic right shift", + "Format": "R-type" + }, + { + "Instruction": "SLT rd, rs1, rs2", + "Operation": "rd = rs1 > imm", + "Notes": "Logical right shift. imm is unsigned, with a length of 5 bits", + "Format": "I-type" + }, + { + "Instruction": "SRAI rd, rs1, imm", + "Operation": "rd = rs1 >>a imm", + "Notes": "Arithmetic right shift. imm is unsigned, with a length of 5 bits", + "Format": "I-type" + }, + { + "Instruction": "LB rd, rs1, imm\nLB rd, imm(rs1)\nLB rd, var[index]", + "Operation": "rd = M[rs1 + imm] rd = var[index]", + "Notes": "Load byte. rd is sign extended to 32 bits", + "Format": "I-type" + }, + { + "Instruction": "LH rd, rs1, imm\nLH rd, imm(rs1)\nLH rd, var[index]", + "Operation": "rd = M[rs1 + imm] rd = var[index]", + "Notes": "Load two bytes. rd is sign extended to 32 bits", + "Format": "I-type" + }, + { + "Instruction": "LW rd, rs1, imm\nLW rd, imm(rs1)\nLW rd, var[index]", + "Operation": "rd = M[rs1 + imm] rd = var[index]", + "Notes": "Load four bytes. rd is sign extended to 32 bits", + "Format": "I-type" + }, + { + "Instruction": "LBU rd, rs1, imm\nLBU rd, imm(rs1)\nLBU rd, var[index]", + "Operation": "rd = M[rs1 + imm] rd = var[index]", + "Notes": "Load byte", + "Format": "I-type" + }, + { + "Instruction": "LHU rd, rs1, imm\nLHU rd, imm(rs1)\nLHU rd, var[index]", + "Operation": "rd = M[rs1 + imm] rd = var[index]", + "Notes": "Load two bytes", + "Format": "I-type" + }, + { + "Instruction": "JALR rd, rs1, imm", + "Operation": "rd = PC + 4; PC = rs1 + imm", + "Notes": "Jump and link register. rd is set to the address of the instruction following the jump. The jump target is rs1 + imm with the least significant bit cleared.", + "Format": "I-type" + }, + { + "Instruction": "ECALL", + "Operation": "environment call", + "Notes": "See section ECALLs.", + "Format": "I-type" + }, + { + "Instruction": "SB rs1, rs2, imm\nSB rs1, imm(rs2)\nSB rs1, var[index], rs2", + "Operation": "M[rs2 + imm] = rs1 var[index] = rs1", + "Notes": "Store byte. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", + "Format": "S-type" + }, + { + "Instruction": "SH rs1, rs2, imm\nSH rs1, imm(rs2)\nSH rs1, var[index], rs2", + "Operation": "M[rs2 + imm] = rs1 var[index] = rs1", + "Notes": "Store two bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", + "Format": "S-type" + }, + { + "Instruction": "SW rs1, rs2, imm\nSW rs1, imm(rs2)\nSW rs1, var[index], rs2", + "Operation": "M[rs2 + imm] = rs1 var[index] = rs1", + "Notes": "Store four bytes. If a variable is modified, rs2 is used as a temporary register, that will be overwritten.", + "Format": "S-type" + }, + { + "Instruction": "BEQ rs1, rs2, imm\nBEQ rs1, rs2, label+offset", + "Operation": "if (rs1 == rs2) PC = PC + imm", + "Notes": "Branch if equal", + "Format": "B-type" + }, + { + "Instruction": "BNE rs1, rs2, imm\nBNE rs1, rs2, label+offset", + "Operation": "if (rs1 != rs2) PC = PC + imm", + "Notes": "Branch if not equal", + "Format": "B-type" + }, + { + "Instruction": "BLT rs1, rs2, imm\nBLT rs1, rs2, label+offset", + "Operation": "if (rs1 =s rs2) PC = PC + imm", + "Notes": "Branch if greater than or equal", + "Format": "B-type" + }, + { + "Instruction": "BLTU rs1, rs2, imm\nBLTU rs1, rs2, label+offset", + "Operation": "if (rs1 =u rs2) PC = PC + imm", + "Notes": "Branch if greater than or equal (unsigned)", + "Format": "B-type" + }, + { + "Instruction": "LUI rd, imm", + "Operation": "rd = imm << 12", + "Notes": null, + "Format": "U" + }, + { + "Instruction": "AUIPC rd, imm", + "Operation": "rd = PC + (imm << 12)", + "Notes": null, + "Format": "U" + }, + { + "Instruction": "JAL rd, addr\nJAL rd, label+offset", + "Operation": "rd = PC + 4; PC = addr", + "Notes": "Jump and link. rd is set to the address of the instruction following the jump.", + "Format": "J-type" + }, + { + "Instruction": "CSRRW rd, csr, rs1", + "Operation": "rd = csr; csr = rs1", + "Notes": "Atomic read/write", + "Format": "CSR" + }, + { + "Instruction": "CSRRS rd, csr, rs1", + "Operation": "rd = csr; csr = csr | rs1", + "Notes": "Atomic read/set. rs1 serves as a bit mask", + "Format": "CSR" + }, + { + "Instruction": "CSRRC rd, csr, rs1", + "Operation": "rd = csr; csr = csr & ~rs1", + "Notes": "Atomic read/clear. rs1 serves as a bit mask", + "Format": "CSR" + }, + { + "Instruction": "CSRRWI rd, csr, uimm", + "Operation": "rd = csr; csr = uimm", + "Notes": "Atomic read/write", + "Format": "CSR" + }, + { + "Instruction": "CSRRSI rd, csr, uimm", + "Operation": "rd = csr; csr = csr | uimm", + "Notes": "Atomic read/set. uimm serves as a bit mask", + "Format": "CSR" + }, + { + "Instruction": "CSRRCI rd, csr, uimm", + "Operation": "rd = csr; csr = csr & ~uimm", + "Notes": "Atomic read/clear. uimm serves as a bit mask", + "Format": "CSR" + }, + { + "Instruction": "NOP", + "Operation": "-", + "Notes": "No operation. Translated to ADDI x0, x0, 0", + "Format": "Pseudo" + }, + { + "Instruction": "LA rd, var[index]", + "Operation": "rd = &var[index]", + "Notes": "Load variable address into rd", + "Format": "Pseudo" + }, + { + "Instruction": "LI rd, imm", + "Operation": "rd = imm", + "Notes": "Load 32 bit immediate into rd", + "Format": "Pseudo" + }, + { + "Instruction": "MV rd, rs", + "Operation": "rd = rs", + "Notes": "Translated to ADDI rd, rs, 0", + "Format": "Pseudo" + } + ], + "other": [] +} From 4443e50d193c8164dfefd3ac4d5a4c812b592892 Mon Sep 17 00:00:00 2001 From: MartinRoehm Date: Fri, 26 Apr 2024 12:32:16 +0200 Subject: [PATCH 082/138] split instructions into sections --- webgui/src/components/riscv/RiscvHelp.vue | 1135 +-------------------- webgui/src/data/riscv_instructions.json | 107 +- 2 files changed, 99 insertions(+), 1143 deletions(-) diff --git a/webgui/src/components/riscv/RiscvHelp.vue b/webgui/src/components/riscv/RiscvHelp.vue index d694144..c7069d8 100644 --- a/webgui/src/components/riscv/RiscvHelp.vue +++ b/webgui/src/components/riscv/RiscvHelp.vue @@ -2,7 +2,6 @@