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lines changed Original file line number Diff line number Diff line change @@ -26,7 +26,14 @@ Directory Structure:
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- hdl
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- rtl
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- - **EF_AES.v**: Verilog source code for the EF_AES design, including the core logic of the UART module.
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+ - **aes_core.v**: Verilog source code for the EF_AES design
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+ - **aes_decipher_block.v**: Verilog source code for the EF_AES design
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+ - **aes_encipher_block.v**: Verilog source code for the EF_AES design
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+ - **aes_inv_sbox.v**: Verilog source code for the EF_AES design
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+ - **aes_key_mem.v**: Verilog source code for the EF_AES design
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+ - **aes_sbox.v**: Verilog source code for the EF_AES design
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+ - **aes.v**: Verilog source code for the EF_AES design
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- **bus_wrappers**
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- **EF_AES_AHBL.v**: Verilog wrapper to interface the EF_AES with the AMBA High-performance Bus (AHB-Lite) protocol.
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- **EF_AES_APB.v**: Verilog wrapper to interface the EF_AES with the Advanced Peripheral Bus (APB) protocol.
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