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NouranAbdelazizNouranAbdelaziz
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fix compilation error in wrappers and add self clear for init for ahbl
1 parent 8439ed1 commit 3d02a9b

15 files changed

+127
-42
lines changed

‎EF_AES.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,7 @@ registers:
109109
- name: next_reg
110110
bit_offset: 1
111111
bit_width: 1
112-
write_port: read_data
112+
write_port: next
113113
description: Next bit
114114
- name: encdec_reg
115115
bit_offset: 2

‎fw/EF_AES_regs.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. ([email protected])
55

‎hdl/rtl/bus_wrappers/EF_AES_AHBL.dev.v

+21-5
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. ([email protected])
55
@@ -78,8 +78,8 @@ module EF_AES_AHBL (
7878
`AHBL_CTRL_SIGNALS
7979

8080
wire [1-1:0] encdec;
81-
wire [1-1:0] init;
82-
wire [1-1:0] next;
81+
reg [1-1:0] init;
82+
reg [1-1:0] next;
8383
wire [1-1:0] ready;
8484
wire [256-1:0] key;
8585
wire [1-1:0] keylen;
@@ -93,8 +93,6 @@ module EF_AES_AHBL (
9393
assign STATUS_WIRE[7 : 7] = result_valid;
9494

9595
reg [7:0] CTRL_REG;
96-
assign init = CTRL_REG[0 : 0];
97-
assign read_data = CTRL_REG[1 : 1];
9896
assign encdec = CTRL_REG[2 : 2];
9997
assign keylen = CTRL_REG[3 : 3];
10098
`AHBL_REG(CTRL_REG, 0, 8)
@@ -189,6 +187,24 @@ module EF_AES_AHBL (
189187

190188
assign IRQ = |MIS_REG;
191189

190+
191+
reg valid_ctrl_wr;
192+
193+
always @(posedge HCLK or negedge HRESETn)
194+
if (~HRESETn) begin
195+
init <= 1'h0;
196+
next <= 1'h0;
197+
valid_ctrl_wr <= 1'b0;
198+
end else if (valid_ctrl_wr) begin
199+
init <= CTRL_REG[0];
200+
next <= CTRL_REG[1];
201+
valid_ctrl_wr <= last_HADDR[15:0]==CTRL_REG_OFFSET & ahbl_we;
202+
end else begin
203+
init <= 1'h0;
204+
next <= 1'h0;
205+
valid_ctrl_wr <= last_HADDR[15:0]==CTRL_REG_OFFSET & ahbl_we;
206+
end
207+
192208
aes_core instance_to_wrap (
193209
.clk(clk),
194210
.reset_n(reset_n),

‎hdl/rtl/bus_wrappers/EF_AES_AHBL.v

+20-5
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. ([email protected])
55
@@ -97,8 +97,8 @@ module EF_AES_AHBL (
9797
wire ahbl_re = ~last_HWRITE & ahbl_valid;
9898

9999
wire [1-1:0] encdec;
100-
wire [1-1:0] init;
101-
wire [1-1:0] next;
100+
reg [1-1:0] init;
101+
reg [1-1:0] next;
102102
wire [1-1:0] ready;
103103
wire [256-1:0] key;
104104
wire [1-1:0] keylen;
@@ -112,8 +112,6 @@ module EF_AES_AHBL (
112112
assign STATUS_WIRE[7 : 7] = result_valid;
113113

114114
reg [7:0] CTRL_REG;
115-
assign init = CTRL_REG[0 : 0];
116-
assign read_data = CTRL_REG[1 : 1];
117115
assign encdec = CTRL_REG[2 : 2];
118116
assign keylen = CTRL_REG[3 : 3];
119117
always @(posedge HCLK or negedge HRESETn)
@@ -251,6 +249,23 @@ module EF_AES_AHBL (
251249
end
252250

253251
assign IRQ = |MIS_REG;
252+
253+
reg valid_ctrl_wr;
254+
255+
always @(posedge HCLK or negedge HRESETn)
256+
if (~HRESETn) begin
257+
init <= 1'h0;
258+
next <= 1'h0;
259+
valid_ctrl_wr <= 1'b0;
260+
end else if (valid_ctrl_wr) begin
261+
init <= CTRL_REG[0];
262+
next <= CTRL_REG[1];
263+
valid_ctrl_wr <= last_HADDR[15:0]==CTRL_REG_OFFSET & ahbl_we;
264+
end else begin
265+
init <= 1'h0;
266+
next <= 1'h0;
267+
valid_ctrl_wr <= last_HADDR[15:0]==CTRL_REG_OFFSET & ahbl_we;
268+
end
254269

255270
aes_core instance_to_wrap (
256271
.clk(clk),

‎hdl/rtl/bus_wrappers/EF_AES_APB.dev.v

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. ([email protected])
55
@@ -94,7 +94,7 @@ module EF_AES_APB (
9494

9595
reg [7:0] CTRL_REG;
9696
assign init = CTRL_REG[0 : 0];
97-
assign read_data = CTRL_REG[1 : 1];
97+
assign next = CTRL_REG[1 : 1];
9898
assign encdec = CTRL_REG[2 : 2];
9999
assign keylen = CTRL_REG[3 : 3];
100100
`APB_REG(CTRL_REG, 0, 8)

‎hdl/rtl/bus_wrappers/EF_AES_APB.v

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. ([email protected])
55
@@ -95,8 +95,8 @@ module EF_AES_APB (
9595
assign STATUS_WIRE[7 : 7] = result_valid;
9696

9797
reg [7:0] CTRL_REG;
98-
assign init = CTRL_REG[0 : 0];
99-
assign read_data = CTRL_REG[1 : 1];
98+
assign init = CTRL_REG[0 : 0];
99+
assign next = CTRL_REG[1 : 1];
100100
assign encdec = CTRL_REG[2 : 2];
101101
assign keylen = CTRL_REG[3 : 3];
102102
always @(posedge PCLK or negedge PRESETn)

‎hdl/rtl/bus_wrappers/EF_AES_WB.dev.v

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. ([email protected])
55
@@ -94,7 +94,7 @@ module EF_AES_WB (
9494

9595
reg [7:0] CTRL_REG;
9696
assign init = CTRL_REG[0 : 0];
97-
assign read_data = CTRL_REG[1 : 1];
97+
assign next = CTRL_REG[1 : 1];
9898
assign encdec = CTRL_REG[2 : 2];
9999
assign keylen = CTRL_REG[3 : 3];
100100
`WB_REG(CTRL_REG, 0, 8)

‎hdl/rtl/bus_wrappers/EF_AES_WB.v

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. ([email protected])
55
@@ -96,8 +96,8 @@ module EF_AES_WB (
9696
assign STATUS_WIRE[7 : 7] = result_valid;
9797

9898
reg [7:0] CTRL_REG;
99-
assign init = CTRL_REG[0 : 0];
100-
assign read_data = CTRL_REG[1 : 1];
99+
assign init = CTRL_REG[0 : 0];
100+
assign next = CTRL_REG[1 : 1];
101101
assign encdec = CTRL_REG[2 : 2];
102102
assign keylen = CTRL_REG[3 : 3];
103103
always @(posedge clk_i or posedge rst_i)

‎hdl/rtl/bus_wrappers/dft/EF_AES_AHBL_DFT.dev.v

+20-5
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. ([email protected])
55
@@ -31,6 +31,7 @@ module EF_AES_AHBL (
3131
inout VPWR,
3232
inout VGND,
3333
`endif
34+
input wire sc_testmode,
3435
`AHBL_SLAVE_PORTS
3536
);
3637

@@ -78,8 +79,6 @@ module EF_AES_AHBL (
7879
`AHBL_CTRL_SIGNALS
7980

8081
wire [1-1:0] encdec;
81-
wire [1-1:0] init;
82-
wire [1-1:0] next;
8382
wire [1-1:0] ready;
8483
wire [256-1:0] key;
8584
wire [1-1:0] keylen;
@@ -93,8 +92,6 @@ module EF_AES_AHBL (
9392
assign STATUS_WIRE[7 : 7] = result_valid;
9493

9594
reg [7:0] CTRL_REG;
96-
assign init = CTRL_REG[0 : 0];
97-
assign read_data = CTRL_REG[1 : 1];
9895
assign encdec = CTRL_REG[2 : 2];
9996
assign keylen = CTRL_REG[3 : 3];
10097
`AHBL_REG(CTRL_REG, 0, 8)
@@ -189,6 +186,24 @@ module EF_AES_AHBL (
189186

190187
assign IRQ = |MIS_REG;
191188

189+
190+
reg valid_ctrl_wr;
191+
192+
always @(posedge HCLK or negedge HRESETn)
193+
if (~HRESETn) begin
194+
init <= 1'h0;
195+
next <= 1'h0;
196+
valid_ctrl_wr <= 1'b0;
197+
end else if (valid_ctrl_wr) begin
198+
init <= CTRL_REG[0];
199+
next <= CTRL_REG[1];
200+
valid_ctrl_wr <= last_HADDR[15:0]==CTRL_REG_OFFSET & ahbl_we;
201+
end else begin
202+
init <= 1'h0;
203+
next <= 1'h0;
204+
valid_ctrl_wr <= last_HADDR[15:0]==CTRL_REG_OFFSET & ahbl_we;
205+
end
206+
192207
aes_core instance_to_wrap (
193208
.clk(clk),
194209
.reset_n(reset_n),

‎hdl/rtl/bus_wrappers/dft/EF_AES_AHBL_DFT.v

+22-5
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. ([email protected])
55
@@ -24,6 +24,7 @@
2424

2525
module EF_AES_AHBL (
2626

27+
input wire sc_testmode,
2728
input wire HCLK,
2829
input wire HRESETn,
2930
input wire HWRITE,
@@ -97,8 +98,8 @@ module EF_AES_AHBL (
9798
wire ahbl_re = ~last_HWRITE & ahbl_valid;
9899

99100
wire [1-1:0] encdec;
100-
wire [1-1:0] init;
101-
wire [1-1:0] next;
101+
reg [1-1:0] init;
102+
reg [1-1:0] next;
102103
wire [1-1:0] ready;
103104
wire [256-1:0] key;
104105
wire [1-1:0] keylen;
@@ -112,8 +113,6 @@ module EF_AES_AHBL (
112113
assign STATUS_WIRE[7 : 7] = result_valid;
113114

114115
reg [7:0] CTRL_REG;
115-
assign init = CTRL_REG[0 : 0];
116-
assign read_data = CTRL_REG[1 : 1];
117116
assign encdec = CTRL_REG[2 : 2];
118117
assign keylen = CTRL_REG[3 : 3];
119118
always @(posedge HCLK or negedge HRESETn)
@@ -252,6 +251,24 @@ module EF_AES_AHBL (
252251

253252
assign IRQ = |MIS_REG;
254253

254+
255+
reg valid_ctrl_wr;
256+
257+
always @(posedge HCLK or negedge HRESETn)
258+
if (~HRESETn) begin
259+
init <= 1'h0;
260+
next <= 1'h0;
261+
valid_ctrl_wr <= 1'b0;
262+
end else if (valid_ctrl_wr) begin
263+
init <= CTRL_REG[0];
264+
next <= CTRL_REG[1];
265+
valid_ctrl_wr <= last_HADDR[15:0]==CTRL_REG_OFFSET & ahbl_we;
266+
end else begin
267+
init <= 1'h0;
268+
next <= 1'h0;
269+
valid_ctrl_wr <= last_HADDR[15:0]==CTRL_REG_OFFSET & ahbl_we;
270+
end
271+
255272
aes_core instance_to_wrap (
256273
.clk(clk),
257274
.reset_n(reset_n),

‎hdl/rtl/bus_wrappers/dft/EF_AES_APB_DFT.dev.v

+3-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. ([email protected])
55
@@ -31,6 +31,7 @@ module EF_AES_APB (
3131
inout VPWR,
3232
inout VGND,
3333
`endif
34+
input wire sc_testmode,
3435
`APB_SLAVE_PORTS
3536
);
3637

@@ -94,7 +95,7 @@ module EF_AES_APB (
9495

9596
reg [7:0] CTRL_REG;
9697
assign init = CTRL_REG[0 : 0];
97-
assign read_data = CTRL_REG[1 : 1];
98+
assign next = CTRL_REG[1 : 1];
9899
assign encdec = CTRL_REG[2 : 2];
99100
assign keylen = CTRL_REG[3 : 3];
100101
`APB_REG(CTRL_REG, 0, 8)

‎hdl/rtl/bus_wrappers/dft/EF_AES_APB_DFT.v

+4-3
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. ([email protected])
55
@@ -24,6 +24,7 @@
2424

2525
module EF_AES_APB (
2626

27+
input wire sc_testmode,
2728
input wire PCLK,
2829
input wire PRESETn,
2930
input wire PWRITE,
@@ -95,8 +96,8 @@ module EF_AES_APB (
9596
assign STATUS_WIRE[7 : 7] = result_valid;
9697

9798
reg [7:0] CTRL_REG;
98-
assign init = CTRL_REG[0 : 0];
99-
assign read_data = CTRL_REG[1 : 1];
99+
assign init = CTRL_REG[0 : 0];
100+
assign next = CTRL_REG[1 : 1];
100101
assign encdec = CTRL_REG[2 : 2];
101102
assign keylen = CTRL_REG[3 : 3];
102103
always @(posedge PCLK or negedge PRESETn)

‎hdl/rtl/bus_wrappers/dft/EF_AES_WB_DFT.dev.v

+3-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
Copyright 2024 Efabless Corp.
2+
Copyright 2025 Efabless Corp.
33
44
Author: Efabless Corp. ([email protected])
55
@@ -31,6 +31,7 @@ module EF_AES_WB (
3131
inout VPWR,
3232
inout VGND,
3333
`endif
34+
input wire sc_testmode,
3435
`WB_SLAVE_PORTS
3536
);
3637

@@ -94,7 +95,7 @@ module EF_AES_WB (
9495

9596
reg [7:0] CTRL_REG;
9697
assign init = CTRL_REG[0 : 0];
97-
assign read_data = CTRL_REG[1 : 1];
98+
assign next = CTRL_REG[1 : 1];
9899
assign encdec = CTRL_REG[2 : 2];
99100
assign keylen = CTRL_REG[3 : 3];
100101
`WB_REG(CTRL_REG, 0, 8)

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