From baac5f8d811d43853d59d69957975ead8bbed088 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 12 Feb 2024 17:29:31 -0800 Subject: [PATCH] Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters Signed-off-by: Alex Forencich --- rtl/axis_baser_rx_64.v | 49 +++--- rtl/axis_baser_tx_64.v | 139 ++++++++--------- rtl/axis_xgmii_rx_64.v | 34 +++-- rtl/axis_xgmii_tx_64.v | 141 +++++++++--------- rtl/eth_mac_10g.v | 6 - rtl/eth_mac_10g_fifo.v | 4 - rtl/eth_mac_phy_10g.v | 6 - rtl/eth_mac_phy_10g_fifo.v | 4 - rtl/eth_mac_phy_10g_rx.v | 4 - rtl/eth_mac_phy_10g_tx.v | 4 - tb/eth_mac_10g/Makefile | 2 - tb/eth_mac_10g/test_eth_mac_10g.py | 2 - tb/eth_mac_10g_fifo/Makefile | 2 - tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py | 2 - tb/eth_mac_phy_10g/Makefile | 2 - tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py | 2 - tb/eth_mac_phy_10g_fifo/Makefile | 2 - .../test_eth_mac_phy_10g_fifo.py | 2 - 18 files changed, 181 insertions(+), 226 deletions(-) diff --git a/rtl/axis_baser_rx_64.v b/rtl/axis_baser_rx_64.v index a20d2698..6a279248 100644 --- a/rtl/axis_baser_rx_64.v +++ b/rtl/axis_baser_rx_64.v @@ -36,8 +36,6 @@ module axis_baser_rx_64 # parameter DATA_WIDTH = 64, parameter KEEP_WIDTH = (DATA_WIDTH/8), parameter HDR_WIDTH = 2, - parameter PTP_PERIOD_NS = 4'h6, - parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_FMT_TOD = 1, parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64, @@ -215,6 +213,9 @@ assign crc_valid[2] = crc_next == ~32'he60914ae; assign crc_valid[1] = crc_next == ~32'he38a6876; assign crc_valid[0] = crc_next == ~32'h6b87b1ec; +reg [4+16-1:0] last_ts_reg = 0; +reg [4+16-1:0] ts_inc_reg = 0; + assign m_axis_tdata = m_axis_tdata_reg; assign m_axis_tkeep = m_axis_tkeep_reg; assign m_axis_tvalid = m_axis_tvalid_reg; @@ -287,10 +288,6 @@ always @* begin // idle state - wait for packet reset_crc = 1'b1; - if (PTP_TS_ENABLE) begin - m_axis_tuser_next[1 +: PTP_TS_WIDTH] = (!PTP_TS_FMT_TOD || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg; - end - if (input_type_d1 == INPUT_TYPE_START_0 && cfg_rx_enable) begin // start condition reset_crc = 1'b0; @@ -312,6 +309,10 @@ always @* begin reset_crc = 1'b1; end + if (PTP_TS_ENABLE) begin + m_axis_tuser_next[1 +: PTP_TS_WIDTH] = (!PTP_TS_FMT_TOD || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg; + end + if (input_type_d0 == INPUT_TYPE_DATA) begin state_next = STATE_PAYLOAD; end else if (input_type_d0[3]) begin @@ -410,19 +411,10 @@ always @(posedge clk) begin if (encoded_rx_hdr == SYNC_CTRL && encoded_rx_data[7:0] == BLOCK_TYPE_START_0) begin lanes_swapped <= 1'b0; - start_packet_reg <= 2'b01; input_type_d0 <= INPUT_TYPE_START_0; input_data_d0 <= encoded_rx_data_masked; - - if (PTP_TS_FMT_TOD) begin - ptp_ts_reg[45:0] <= ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); - ptp_ts_reg[95:48] <= ptp_ts[95:48]; - end else begin - ptp_ts_reg <= ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); - end end else if (encoded_rx_hdr == SYNC_CTRL && (encoded_rx_data[7:0] == BLOCK_TYPE_START_4 || encoded_rx_data[7:0] == BLOCK_TYPE_OS_START)) begin lanes_swapped <= 1'b1; - start_packet_reg <= 2'b10; delay_type_valid <= 1'b1; if (delay_type_valid) begin @@ -431,13 +423,6 @@ always @(posedge clk) begin input_type_d0 <= INPUT_TYPE_IDLE; end input_data_d0 <= {encoded_rx_data_masked[31:0], swap_data}; - - if (PTP_TS_FMT_TOD) begin - ptp_ts_reg[45:0] <= ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); - ptp_ts_reg[95:48] <= ptp_ts[95:48]; - end else begin - ptp_ts_reg <= ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); - end end else if (lanes_swapped) begin if (delay_type_valid) begin input_type_d0 <= delay_type; @@ -519,6 +504,23 @@ always @(posedge clk) begin delay_type <= INPUT_TYPE_ERROR; end + if (delay_type == INPUT_TYPE_START_0 && delay_type_valid) begin + start_packet_reg <= 2'b10; + if (PTP_TS_FMT_TOD) begin + ptp_ts_reg[45:0] <= ptp_ts[45:0] + (ts_inc_reg >> 1); + ptp_ts_reg[95:48] <= ptp_ts[95:48]; + end else begin + ptp_ts_reg <= ptp_ts + (ts_inc_reg >> 1); + end + end + + if (input_type_d0 == INPUT_TYPE_START_0) begin + if (!lanes_swapped) begin + start_packet_reg <= 2'b01; + ptp_ts_reg <= ptp_ts; + end + end + input_type_d1 <= input_type_d0; input_data_d1 <= input_data_d0; @@ -530,6 +532,9 @@ always @(posedge clk) begin crc_valid_save <= crc_valid; + last_ts_reg <= ptp_ts; + ts_inc_reg <= ptp_ts - last_ts_reg; + if (rst) begin state_reg <= STATE_IDLE; diff --git a/rtl/axis_baser_tx_64.v b/rtl/axis_baser_tx_64.v index abc52ed5..fbaf8dee 100644 --- a/rtl/axis_baser_tx_64.v +++ b/rtl/axis_baser_tx_64.v @@ -39,8 +39,6 @@ module axis_baser_tx_64 # parameter ENABLE_PADDING = 1, parameter ENABLE_DIC = 1, parameter MIN_FRAME_LENGTH = 64, - parameter PTP_PERIOD_NS = 4'h6, - parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_FMT_TOD = 1, parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64, @@ -199,6 +197,7 @@ reg [3:0] fcs_output_type_1; reg [7:0] ifg_offset; +reg frame_start_reg = 1'b0, frame_start_next; reg frame_reg = 1'b0, frame_next; reg frame_error_reg = 1'b0, frame_error_next; reg [MIN_LEN_WIDTH-1:0] frame_min_count_reg = 0, frame_min_count_next; @@ -208,12 +207,12 @@ reg [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next; reg s_axis_tready_reg = 1'b0, s_axis_tready_next; -reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0, m_axis_ptp_ts_next; -reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_adj_reg = 0, m_axis_ptp_ts_adj_next; -reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0, m_axis_ptp_ts_tag_next; -reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next; -reg m_axis_ptp_ts_valid_int_reg = 1'b0, m_axis_ptp_ts_valid_int_next; -reg m_axis_ptp_ts_borrow_reg = 1'b0, m_axis_ptp_ts_borrow_next; +reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0; +reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_adj_reg = 0; +reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0; +reg m_axis_ptp_ts_valid_reg = 1'b0; +reg m_axis_ptp_ts_valid_int_reg = 1'b0; +reg m_axis_ptp_ts_borrow_reg = 1'b0; reg [31:0] crc_state_reg[7:0]; wire [31:0] crc_state_next[7:0]; @@ -224,9 +223,12 @@ reg [HDR_WIDTH-1:0] encoded_tx_hdr_reg = SYNC_CTRL; reg [DATA_WIDTH-1:0] output_data_reg = {DATA_WIDTH{1'b0}}, output_data_next; reg [3:0] output_type_reg = OUTPUT_TYPE_IDLE, output_type_next; -reg [1:0] start_packet_reg = 2'b00, start_packet_next; +reg [1:0] start_packet_reg = 2'b00; reg error_underflow_reg = 1'b0, error_underflow_next; +reg [4+16-1:0] last_ts_reg = 0; +reg [4+16-1:0] ts_inc_reg = 0; + assign s_axis_tready = s_axis_tready_reg; assign encoded_tx_data = encoded_tx_data_reg; @@ -356,6 +358,7 @@ always @* begin swap_lanes_next = swap_lanes_reg; + frame_start_next = 1'b0; frame_next = frame_reg; frame_error_next = frame_error_reg; frame_min_count_next = frame_min_count_reg; @@ -368,31 +371,15 @@ always @* begin s_tdata_next = s_tdata_reg; s_empty_next = s_empty_reg; - m_axis_ptp_ts_next = m_axis_ptp_ts_reg; - m_axis_ptp_ts_adj_next = m_axis_ptp_ts_adj_reg; - m_axis_ptp_ts_tag_next = m_axis_ptp_ts_tag_reg; - m_axis_ptp_ts_valid_next = 1'b0; - m_axis_ptp_ts_valid_int_next = 1'b0; - m_axis_ptp_ts_borrow_next = m_axis_ptp_ts_borrow_reg; - output_data_next = s_tdata_reg; output_type_next = OUTPUT_TYPE_IDLE; - start_packet_next = 2'b00; error_underflow_next = 1'b0; if (s_axis_tvalid && s_axis_tready) begin frame_next = !s_axis_tlast; end - if (PTP_TS_ENABLE && PTP_TS_FMT_TOD) begin - m_axis_ptp_ts_valid_next = m_axis_ptp_ts_valid_int_reg; - m_axis_ptp_ts_adj_next[15:0] = m_axis_ptp_ts_reg[15:0]; - {m_axis_ptp_ts_borrow_next, m_axis_ptp_ts_adj_next[45:16]} = $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000); - m_axis_ptp_ts_adj_next[47:46] = 0; - m_axis_ptp_ts_adj_next[95:48] = m_axis_ptp_ts_reg[95:48] + 1; - end - case (state_reg) STATE_IDLE: begin // idle state - wait for data @@ -408,49 +395,10 @@ always @* begin s_empty_next = keep2empty(s_axis_tkeep); if (s_axis_tvalid && cfg_tx_enable) begin - // XGMII start and preamble - if (swap_lanes_reg) begin - // lanes swapped - if (PTP_TS_ENABLE) begin - if (PTP_TS_FMT_TOD) begin - m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); - m_axis_ptp_ts_next[95:48] = ptp_ts[95:48]; - end else begin - m_axis_ptp_ts_next = ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); - end - end - start_packet_next = 2'b10; - end else begin - // lanes not swapped - if (PTP_TS_ENABLE) begin - if (PTP_TS_FMT_TOD) begin - m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); - m_axis_ptp_ts_next[95:48] = ptp_ts[95:48]; - end else begin - m_axis_ptp_ts_next = ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); - end - end - start_packet_next = 2'b01; - end - if (PTP_TS_ENABLE) begin - if (PTP_TS_CTRL_IN_TUSER) begin - m_axis_ptp_ts_tag_next = s_axis_tuser >> 2; - if (PTP_TS_FMT_TOD) begin - m_axis_ptp_ts_valid_int_next = s_axis_tuser[1]; - end else begin - m_axis_ptp_ts_valid_next = s_axis_tuser[1]; - end - end else begin - m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; - if (PTP_TS_FMT_TOD) begin - m_axis_ptp_ts_valid_int_next = 1'b1; - end else begin - m_axis_ptp_ts_valid_next = 1'b1; - end - end - end + // Preamble and SFD output_data_next = {ETH_SFD, {7{ETH_PRE}}}; output_type_next = OUTPUT_TYPE_START_0; + frame_start_next = 1'b1; s_axis_tready_next = 1'b1; state_next = STATE_PAYLOAD; end else begin @@ -641,6 +589,7 @@ always @(posedge clk) begin swap_lanes_reg <= swap_lanes_next; + frame_start_reg <= frame_start_next; frame_reg <= frame_next; frame_error_reg <= frame_error_next; frame_min_count_reg <= frame_min_count_next; @@ -653,14 +602,10 @@ always @(posedge clk) begin s_axis_tready_reg <= s_axis_tready_next; - m_axis_ptp_ts_reg <= m_axis_ptp_ts_next; - m_axis_ptp_ts_adj_reg <= m_axis_ptp_ts_adj_next; - m_axis_ptp_ts_tag_reg <= m_axis_ptp_ts_tag_next; - m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_next; - m_axis_ptp_ts_valid_int_reg <= m_axis_ptp_ts_valid_int_next; - m_axis_ptp_ts_borrow_reg <= m_axis_ptp_ts_borrow_next; + m_axis_ptp_ts_valid_reg <= 1'b0; + m_axis_ptp_ts_valid_int_reg <= 1'b0; - start_packet_reg <= start_packet_next; + start_packet_reg <= 2'b00; error_underflow_reg <= error_underflow_next; delay_type_valid <= 1'b0; @@ -690,6 +635,50 @@ always @(posedge clk) begin output_type_reg <= output_type_next; end + if (PTP_TS_ENABLE && PTP_TS_FMT_TOD) begin + m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_int_reg; + m_axis_ptp_ts_adj_reg[15:0] <= m_axis_ptp_ts_reg[15:0]; + {m_axis_ptp_ts_borrow_reg, m_axis_ptp_ts_adj_reg[45:16]} <= $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000); + m_axis_ptp_ts_adj_reg[47:46] <= 0; + m_axis_ptp_ts_adj_reg[95:48] <= m_axis_ptp_ts_reg[95:48] + 1; + end + + if (frame_start_reg) begin + if (swap_lanes_reg) begin + if (PTP_TS_ENABLE) begin + if (PTP_TS_FMT_TOD) begin + m_axis_ptp_ts_reg[45:0] <= ptp_ts[45:0] + (ts_inc_reg >> 1); + m_axis_ptp_ts_reg[95:48] <= ptp_ts[95:48]; + end else begin + m_axis_ptp_ts_reg <= ptp_ts + (ts_inc_reg >> 1); + end + end + start_packet_reg <= 2'b10; + end else begin + if (PTP_TS_ENABLE) begin + m_axis_ptp_ts_reg <= ptp_ts; + end + start_packet_reg <= 2'b01; + end + if (PTP_TS_ENABLE) begin + if (PTP_TS_CTRL_IN_TUSER) begin + m_axis_ptp_ts_tag_reg <= s_axis_tuser >> 2; + if (PTP_TS_FMT_TOD) begin + m_axis_ptp_ts_valid_int_reg <= s_axis_tuser[1]; + end else begin + m_axis_ptp_ts_valid_reg <= s_axis_tuser[1]; + end + end else begin + m_axis_ptp_ts_tag_reg <= s_axis_tuser >> 1; + if (PTP_TS_FMT_TOD) begin + m_axis_ptp_ts_valid_int_reg <= 1'b1; + end else begin + m_axis_ptp_ts_valid_reg <= 1'b1; + end + end + end + end + case (output_type_reg) OUTPUT_TYPE_IDLE: begin encoded_tx_data_reg <= {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL}; @@ -765,9 +754,13 @@ always @(posedge clk) begin crc_state_reg[7] <= 32'hFFFFFFFF; end + last_ts_reg <= ptp_ts; + ts_inc_reg <= ptp_ts - last_ts_reg; + if (rst) begin state_reg <= STATE_IDLE; + frame_start_reg <= 1'b0; frame_reg <= 1'b0; swap_lanes_reg <= 1'b0; diff --git a/rtl/axis_xgmii_rx_64.v b/rtl/axis_xgmii_rx_64.v index 586de38c..132decf6 100644 --- a/rtl/axis_xgmii_rx_64.v +++ b/rtl/axis_xgmii_rx_64.v @@ -36,8 +36,6 @@ module axis_xgmii_rx_64 # parameter DATA_WIDTH = 64, parameter KEEP_WIDTH = (DATA_WIDTH/8), parameter CTRL_WIDTH = (DATA_WIDTH/8), - parameter PTP_PERIOD_NS = 4'h6, - parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_FMT_TOD = 1, parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64, @@ -163,6 +161,9 @@ assign crc_valid[2] = crc_next == ~32'he60914ae; assign crc_valid[1] = crc_next == ~32'he38a6876; assign crc_valid[0] = crc_next == ~32'h6b87b1ec; +reg [4+16-1:0] last_ts_reg = 0; +reg [4+16-1:0] ts_inc_reg = 0; + assign m_axis_tdata = m_axis_tdata_reg; assign m_axis_tkeep = m_axis_tkeep_reg; assign m_axis_tvalid = m_axis_tvalid_reg; @@ -335,6 +336,7 @@ always @(posedge clk) begin ptp_ts_adj_reg[95:48] <= ptp_ts_reg[95:48] + 1; end + // lane swapping and termination character detection if (lanes_swapped) begin xgmii_rxd_d0 <= {xgmii_rxd_masked[31:0], swap_rxd}; xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc}; @@ -369,37 +371,40 @@ always @(posedge clk) begin end end + // start control character detection if (xgmii_rxc[0] && xgmii_rxd[7:0] == XGMII_START) begin lanes_swapped <= 1'b0; - start_packet_reg <= 2'b01; xgmii_start_d0 <= 1'b1; term_lane_reg <= 0; term_present_reg <= 1'b0; framing_error_reg <= xgmii_rxc[7:1] != 0; - - if (PTP_TS_FMT_TOD) begin - ptp_ts_reg[45:0] <= ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); - ptp_ts_reg[95:48] <= ptp_ts[95:48]; - end else begin - ptp_ts_reg <= ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); - end end else if (xgmii_rxc[4] && xgmii_rxd[39:32] == XGMII_START) begin lanes_swapped <= 1'b1; - start_packet_reg <= 2'b10; xgmii_start_swap <= 1'b1; term_lane_reg <= 0; term_present_reg <= 1'b0; framing_error_reg <= xgmii_rxc[7:5] != 0; + end + // capture timestamps + if (xgmii_start_swap) begin + start_packet_reg <= 2'b10; if (PTP_TS_FMT_TOD) begin - ptp_ts_reg[45:0] <= ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); + ptp_ts_reg[45:0] <= ptp_ts[45:0] + (ts_inc_reg >> 1); ptp_ts_reg[95:48] <= ptp_ts[95:48]; end else begin - ptp_ts_reg <= ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); + ptp_ts_reg <= ptp_ts + (ts_inc_reg >> 1); + end + end + + if (xgmii_start_d0) begin + if (!lanes_swapped) begin + start_packet_reg <= 2'b01; + ptp_ts_reg <= ptp_ts; end end @@ -417,6 +422,9 @@ always @(posedge clk) begin xgmii_rxd_d1 <= xgmii_rxd_d0; xgmii_start_d1 <= xgmii_start_d0; + last_ts_reg <= ptp_ts; + ts_inc_reg <= ptp_ts - last_ts_reg; + if (rst) begin state_reg <= STATE_IDLE; diff --git a/rtl/axis_xgmii_tx_64.v b/rtl/axis_xgmii_tx_64.v index cb4235a2..269e2fa1 100644 --- a/rtl/axis_xgmii_tx_64.v +++ b/rtl/axis_xgmii_tx_64.v @@ -39,8 +39,6 @@ module axis_xgmii_tx_64 # parameter ENABLE_PADDING = 1, parameter ENABLE_DIC = 1, parameter MIN_FRAME_LENGTH = 64, - parameter PTP_PERIOD_NS = 4'h6, - parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_FMT_TOD = 1, parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64, @@ -147,6 +145,7 @@ reg [CTRL_WIDTH-1:0] fcs_output_txc_1; reg [7:0] ifg_offset; +reg frame_start_reg = 1'b0, frame_start_next; reg frame_reg = 1'b0, frame_next; reg frame_error_reg = 1'b0, frame_error_next; reg [MIN_LEN_WIDTH-1:0] frame_min_count_reg = 0, frame_min_count_next; @@ -156,20 +155,23 @@ reg [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next; reg s_axis_tready_reg = 1'b0, s_axis_tready_next; -reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0, m_axis_ptp_ts_next; -reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_adj_reg = 0, m_axis_ptp_ts_adj_next; -reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0, m_axis_ptp_ts_tag_next; -reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next; -reg m_axis_ptp_ts_valid_int_reg = 1'b0, m_axis_ptp_ts_valid_int_next; -reg m_axis_ptp_ts_borrow_reg = 1'b0, m_axis_ptp_ts_borrow_next; +reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0; +reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_adj_reg = 0; +reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0; +reg m_axis_ptp_ts_valid_reg = 1'b0; +reg m_axis_ptp_ts_valid_int_reg = 1'b0; +reg m_axis_ptp_ts_borrow_reg = 1'b0; reg [31:0] crc_state_reg[7:0]; wire [31:0] crc_state_next[7:0]; +reg [4+16-1:0] last_ts_reg = 0; +reg [4+16-1:0] ts_inc_reg = 0; + reg [DATA_WIDTH-1:0] xgmii_txd_reg = {CTRL_WIDTH{XGMII_IDLE}}, xgmii_txd_next; reg [CTRL_WIDTH-1:0] xgmii_txc_reg = {CTRL_WIDTH{1'b1}}, xgmii_txc_next; -reg start_packet_reg = 2'b00, start_packet_next; +reg start_packet_reg = 2'b00; reg error_underflow_reg = 1'b0, error_underflow_next; assign s_axis_tready = s_axis_tready_reg; @@ -301,6 +303,7 @@ always @* begin swap_lanes_next = swap_lanes_reg; + frame_start_next = 1'b0; frame_next = frame_reg; frame_error_next = frame_error_reg; frame_min_count_next = frame_min_count_reg; @@ -313,32 +316,16 @@ always @* begin s_tdata_next = s_tdata_reg; s_empty_next = s_empty_reg; - m_axis_ptp_ts_next = m_axis_ptp_ts_reg; - m_axis_ptp_ts_adj_next = m_axis_ptp_ts_adj_reg; - m_axis_ptp_ts_tag_next = m_axis_ptp_ts_tag_reg; - m_axis_ptp_ts_valid_next = 1'b0; - m_axis_ptp_ts_valid_int_next = 1'b0; - m_axis_ptp_ts_borrow_next = m_axis_ptp_ts_borrow_reg; - // XGMII idle xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}}; xgmii_txc_next = {CTRL_WIDTH{1'b1}}; - start_packet_next = 2'b00; error_underflow_next = 1'b0; if (s_axis_tvalid && s_axis_tready) begin frame_next = !s_axis_tlast; end - if (PTP_TS_ENABLE && PTP_TS_FMT_TOD) begin - m_axis_ptp_ts_valid_next = m_axis_ptp_ts_valid_int_reg; - m_axis_ptp_ts_adj_next[15:0] = m_axis_ptp_ts_reg[15:0]; - {m_axis_ptp_ts_borrow_next, m_axis_ptp_ts_adj_next[45:16]} = $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000); - m_axis_ptp_ts_adj_next[47:46] = 0; - m_axis_ptp_ts_adj_next[95:48] = m_axis_ptp_ts_reg[95:48] + 1; - end - case (state_reg) STATE_IDLE: begin // idle state - wait for data @@ -355,49 +342,10 @@ always @* begin s_empty_next = keep2empty(s_axis_tkeep); if (s_axis_tvalid && s_axis_tready) begin - // XGMII start and preamble - if (swap_lanes_reg) begin - // lanes swapped - if (PTP_TS_ENABLE) begin - if (PTP_TS_FMT_TOD) begin - m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); - m_axis_ptp_ts_next[95:48] = ptp_ts[95:48]; - end else begin - m_axis_ptp_ts_next = ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); - end - end - start_packet_next = 2'b10; - end else begin - // lanes not swapped - if (PTP_TS_ENABLE) begin - if (PTP_TS_FMT_TOD) begin - m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); - m_axis_ptp_ts_next[95:48] = ptp_ts[95:48]; - end else begin - m_axis_ptp_ts_next = ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); - end - end - start_packet_next = 2'b01; - end - if (PTP_TS_ENABLE) begin - if (PTP_TS_CTRL_IN_TUSER) begin - m_axis_ptp_ts_tag_next = s_axis_tuser >> 2; - if (PTP_TS_FMT_TOD) begin - m_axis_ptp_ts_valid_int_next = s_axis_tuser[1]; - end else begin - m_axis_ptp_ts_valid_next = s_axis_tuser[1]; - end - end else begin - m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; - if (PTP_TS_FMT_TOD) begin - m_axis_ptp_ts_valid_int_next = 1'b1; - end else begin - m_axis_ptp_ts_valid_next = 1'b1; - end - end - end + // XGMII start, preamble, and SFD xgmii_txd_next = {ETH_SFD, {6{ETH_PRE}}, XGMII_START}; xgmii_txc_next = 8'b00000001; + frame_start_next = 1'b1; s_axis_tready_next = 1'b1; state_next = STATE_PAYLOAD; end else begin @@ -586,6 +534,7 @@ always @(posedge clk) begin swap_lanes_reg <= swap_lanes_next; + frame_start_reg <= frame_start_next; frame_reg <= frame_next; frame_error_reg <= frame_error_next; frame_min_count_reg <= frame_min_count_next; @@ -598,12 +547,55 @@ always @(posedge clk) begin s_axis_tready_reg <= s_axis_tready_next; - m_axis_ptp_ts_reg <= m_axis_ptp_ts_next; - m_axis_ptp_ts_adj_reg <= m_axis_ptp_ts_adj_next; - m_axis_ptp_ts_tag_reg <= m_axis_ptp_ts_tag_next; - m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_next; - m_axis_ptp_ts_valid_int_reg <= m_axis_ptp_ts_valid_int_next; - m_axis_ptp_ts_borrow_reg <= m_axis_ptp_ts_borrow_next; + m_axis_ptp_ts_valid_reg <= 1'b0; + m_axis_ptp_ts_valid_int_reg <= 1'b0; + + start_packet_reg <= 2'b00; + error_underflow_reg <= error_underflow_next; + + if (PTP_TS_ENABLE && PTP_TS_FMT_TOD) begin + m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_int_reg; + m_axis_ptp_ts_adj_reg[15:0] <= m_axis_ptp_ts_reg[15:0]; + {m_axis_ptp_ts_borrow_reg, m_axis_ptp_ts_adj_reg[45:16]} <= $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000); + m_axis_ptp_ts_adj_reg[47:46] <= 0; + m_axis_ptp_ts_adj_reg[95:48] <= m_axis_ptp_ts_reg[95:48] + 1; + end + + if (frame_start_reg) begin + if (swap_lanes_reg) begin + if (PTP_TS_ENABLE) begin + if (PTP_TS_FMT_TOD) begin + m_axis_ptp_ts_reg[45:0] <= ptp_ts[45:0] + (ts_inc_reg >> 1); + m_axis_ptp_ts_reg[95:48] <= ptp_ts[95:48]; + end else begin + m_axis_ptp_ts_reg <= ptp_ts + (ts_inc_reg >> 1); + end + end + start_packet_reg <= 2'b10; + end else begin + if (PTP_TS_ENABLE) begin + m_axis_ptp_ts_reg <= ptp_ts; + end + start_packet_reg <= 2'b01; + end + if (PTP_TS_ENABLE) begin + if (PTP_TS_CTRL_IN_TUSER) begin + m_axis_ptp_ts_tag_reg <= s_axis_tuser >> 2; + if (PTP_TS_FMT_TOD) begin + m_axis_ptp_ts_valid_int_reg <= s_axis_tuser[1]; + end else begin + m_axis_ptp_ts_valid_reg <= s_axis_tuser[1]; + end + end else begin + m_axis_ptp_ts_tag_reg <= s_axis_tuser >> 1; + if (PTP_TS_FMT_TOD) begin + m_axis_ptp_ts_valid_int_reg <= 1'b1; + end else begin + m_axis_ptp_ts_valid_reg <= 1'b1; + end + end + end + end crc_state_reg[0] <= crc_state_next[0]; crc_state_reg[1] <= crc_state_next[1]; @@ -632,12 +624,13 @@ always @(posedge clk) begin xgmii_txc_reg <= xgmii_txc_next; end - start_packet_reg <= start_packet_next; - error_underflow_reg <= error_underflow_next; + last_ts_reg <= ptp_ts; + ts_inc_reg <= ptp_ts - last_ts_reg; if (rst) begin state_reg <= STATE_IDLE; + frame_start_reg <= 1'b0; frame_reg <= 1'b0; swap_lanes_reg <= 1'b0; diff --git a/rtl/eth_mac_10g.v b/rtl/eth_mac_10g.v index dfea2889..54c0e20f 100644 --- a/rtl/eth_mac_10g.v +++ b/rtl/eth_mac_10g.v @@ -39,8 +39,6 @@ module eth_mac_10g # parameter ENABLE_PADDING = 1, parameter ENABLE_DIC = 1, parameter MIN_FRAME_LENGTH = 64, - parameter PTP_PERIOD_NS = 4'h6, - parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_FMT_TOD = 1, parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64, @@ -222,8 +220,6 @@ axis_xgmii_rx_64 #( .DATA_WIDTH(DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH), .CTRL_WIDTH(CTRL_WIDTH), - .PTP_PERIOD_NS(PTP_PERIOD_NS), - .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .PTP_TS_ENABLE(PTP_TS_ENABLE), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_WIDTH(PTP_TS_WIDTH), @@ -253,8 +249,6 @@ axis_xgmii_tx_64 #( .ENABLE_PADDING(ENABLE_PADDING), .ENABLE_DIC(ENABLE_DIC), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .PTP_PERIOD_NS(PTP_PERIOD_NS), - .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .PTP_TS_ENABLE(PTP_TS_ENABLE), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_WIDTH(PTP_TS_WIDTH), diff --git a/rtl/eth_mac_10g_fifo.v b/rtl/eth_mac_10g_fifo.v index 07751769..21c5e386 100644 --- a/rtl/eth_mac_10g_fifo.v +++ b/rtl/eth_mac_10g_fifo.v @@ -53,8 +53,6 @@ module eth_mac_10g_fifo # parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO, parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME, parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME, - parameter PTP_PERIOD_NS = 4'h6, - parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_FMT_TOD = 1, parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64, @@ -333,8 +331,6 @@ eth_mac_10g #( .ENABLE_PADDING(ENABLE_PADDING), .ENABLE_DIC(ENABLE_DIC), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .PTP_PERIOD_NS(PTP_PERIOD_NS), - .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .PTP_TS_ENABLE(PTP_TS_ENABLE), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_WIDTH(PTP_TS_WIDTH), diff --git a/rtl/eth_mac_phy_10g.v b/rtl/eth_mac_phy_10g.v index dc35c283..bc4bfa38 100644 --- a/rtl/eth_mac_phy_10g.v +++ b/rtl/eth_mac_phy_10g.v @@ -39,8 +39,6 @@ module eth_mac_phy_10g # parameter ENABLE_PADDING = 1, parameter ENABLE_DIC = 1, parameter MIN_FRAME_LENGTH = 64, - parameter PTP_PERIOD_NS = 4'h6, - parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_FMT_TOD = 1, parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64, @@ -130,8 +128,6 @@ eth_mac_phy_10g_rx #( .DATA_WIDTH(DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH), .HDR_WIDTH(HDR_WIDTH), - .PTP_PERIOD_NS(PTP_PERIOD_NS), - .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .PTP_TS_ENABLE(PTP_TS_ENABLE), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_WIDTH(PTP_TS_WIDTH), @@ -176,8 +172,6 @@ eth_mac_phy_10g_tx #( .ENABLE_PADDING(ENABLE_PADDING), .ENABLE_DIC(ENABLE_DIC), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .PTP_PERIOD_NS(PTP_PERIOD_NS), - .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .PTP_TS_ENABLE(PTP_TS_ENABLE), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_WIDTH(PTP_TS_WIDTH), diff --git a/rtl/eth_mac_phy_10g_fifo.v b/rtl/eth_mac_phy_10g_fifo.v index cbb555a2..166f6b75 100644 --- a/rtl/eth_mac_phy_10g_fifo.v +++ b/rtl/eth_mac_phy_10g_fifo.v @@ -61,8 +61,6 @@ module eth_mac_phy_10g_fifo # parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO, parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME, parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME, - parameter PTP_PERIOD_NS = 4'h6, - parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_FMT_TOD = 1, parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64, @@ -362,8 +360,6 @@ eth_mac_phy_10g #( .ENABLE_PADDING(ENABLE_PADDING), .ENABLE_DIC(ENABLE_DIC), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .PTP_PERIOD_NS(PTP_PERIOD_NS), - .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .PTP_TS_ENABLE(PTP_TS_ENABLE), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_WIDTH(PTP_TS_WIDTH), diff --git a/rtl/eth_mac_phy_10g_rx.v b/rtl/eth_mac_phy_10g_rx.v index fe733da9..cc6c7a54 100644 --- a/rtl/eth_mac_phy_10g_rx.v +++ b/rtl/eth_mac_phy_10g_rx.v @@ -36,8 +36,6 @@ module eth_mac_phy_10g_rx # parameter DATA_WIDTH = 64, parameter KEEP_WIDTH = (DATA_WIDTH/8), parameter HDR_WIDTH = (DATA_WIDTH/32), - parameter PTP_PERIOD_NS = 4'h6, - parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_FMT_TOD = 1, parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64, @@ -147,8 +145,6 @@ axis_baser_rx_64 #( .DATA_WIDTH(DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH), .HDR_WIDTH(HDR_WIDTH), - .PTP_PERIOD_NS(PTP_PERIOD_NS), - .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .PTP_TS_ENABLE(PTP_TS_ENABLE), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_WIDTH(PTP_TS_WIDTH), diff --git a/rtl/eth_mac_phy_10g_tx.v b/rtl/eth_mac_phy_10g_tx.v index 2d36be4c..b604e1c8 100644 --- a/rtl/eth_mac_phy_10g_tx.v +++ b/rtl/eth_mac_phy_10g_tx.v @@ -39,8 +39,6 @@ module eth_mac_phy_10g_tx # parameter ENABLE_PADDING = 1, parameter ENABLE_DIC = 1, parameter MIN_FRAME_LENGTH = 64, - parameter PTP_PERIOD_NS = 4'h6, - parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_FMT_TOD = 1, parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64, @@ -123,8 +121,6 @@ axis_baser_tx_64 #( .ENABLE_PADDING(ENABLE_PADDING), .ENABLE_DIC(ENABLE_DIC), .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .PTP_PERIOD_NS(PTP_PERIOD_NS), - .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .PTP_TS_ENABLE(PTP_TS_ENABLE), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), .PTP_TS_WIDTH(PTP_TS_WIDTH), diff --git a/tb/eth_mac_10g/Makefile b/tb/eth_mac_10g/Makefile index d31579ae..6bc26596 100644 --- a/tb/eth_mac_10g/Makefile +++ b/tb/eth_mac_10g/Makefile @@ -47,8 +47,6 @@ export PARAM_CTRL_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) export PARAM_ENABLE_PADDING := 1 export PARAM_ENABLE_DIC := 1 export PARAM_MIN_FRAME_LENGTH := 64 -export PARAM_PTP_PERIOD_NS := 6 -export PARAM_PTP_PERIOD_FNS := 26214 export PARAM_PTP_TS_ENABLE := 1 export PARAM_PTP_TS_FMT_TOD := 1 export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96) diff --git a/tb/eth_mac_10g/test_eth_mac_10g.py b/tb/eth_mac_10g/test_eth_mac_10g.py index 87abf9d1..177b28e2 100644 --- a/tb/eth_mac_10g/test_eth_mac_10g.py +++ b/tb/eth_mac_10g/test_eth_mac_10g.py @@ -745,8 +745,6 @@ def test_eth_mac_10g(request, data_width, enable_dic, pfc_en): parameters['ENABLE_PADDING'] = 1 parameters['ENABLE_DIC'] = enable_dic parameters['MIN_FRAME_LENGTH'] = 64 - parameters['PTP_PERIOD_NS'] = 0x6 if parameters['DATA_WIDTH'] == 64 else 0x3 - parameters['PTP_PERIOD_FNS'] = 0x6666 if parameters['DATA_WIDTH'] == 64 else 0x3333 parameters['PTP_TS_ENABLE'] = 1 parameters['PTP_TS_FMT_TOD'] = 1 parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64 diff --git a/tb/eth_mac_10g_fifo/Makefile b/tb/eth_mac_10g_fifo/Makefile index 663b4f01..66c386df 100644 --- a/tb/eth_mac_10g_fifo/Makefile +++ b/tb/eth_mac_10g_fifo/Makefile @@ -62,8 +62,6 @@ export PARAM_RX_FRAME_FIFO := 1 export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_PTP_PERIOD_NS := 6 -export PARAM_PTP_PERIOD_FNS := 26214 export PARAM_PTP_TS_ENABLE := 1 export PARAM_PTP_TS_FMT_TOD := 1 export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96) diff --git a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py index 6298e161..73a67e9a 100644 --- a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py +++ b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py @@ -369,8 +369,6 @@ def test_eth_mac_10g_fifo(request, data_width, enable_dic): parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO'] parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME'] parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME'] - parameters['PTP_PERIOD_NS'] = 0x6 if parameters['DATA_WIDTH'] == 64 else 0x3 - parameters['PTP_PERIOD_FNS'] = 0x6666 if parameters['DATA_WIDTH'] == 64 else 0x3333 parameters['PTP_TS_ENABLE'] = 1 parameters['PTP_TS_FMT_TOD'] = 1 parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64 diff --git a/tb/eth_mac_phy_10g/Makefile b/tb/eth_mac_phy_10g/Makefile index d0e2a4ae..edfcc0b8 100644 --- a/tb/eth_mac_phy_10g/Makefile +++ b/tb/eth_mac_phy_10g/Makefile @@ -48,8 +48,6 @@ export PARAM_HDR_WIDTH := 2 export PARAM_ENABLE_PADDING := 1 export PARAM_ENABLE_DIC := 1 export PARAM_MIN_FRAME_LENGTH := 64 -export PARAM_PTP_PERIOD_NS := 6 -export PARAM_PTP_PERIOD_FNS := 26214 export PARAM_PTP_TS_ENABLE := 1 export PARAM_PTP_TS_FMT_TOD := 1 export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96) diff --git a/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py b/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py index 0bb0d167..99df2e2c 100644 --- a/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py +++ b/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py @@ -478,8 +478,6 @@ def test_eth_mac_phy_10g(request, data_width, enable_dic): parameters['ENABLE_PADDING'] = 1 parameters['ENABLE_DIC'] = enable_dic parameters['MIN_FRAME_LENGTH'] = 64 - parameters['PTP_PERIOD_NS'] = 0x6 if parameters['DATA_WIDTH'] == 64 else 0x3 - parameters['PTP_PERIOD_FNS'] = 0x6666 if parameters['DATA_WIDTH'] == 64 else 0x3333 parameters['PTP_TS_ENABLE'] = 1 parameters['PTP_TS_FMT_TOD'] = 1 parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64 diff --git a/tb/eth_mac_phy_10g_fifo/Makefile b/tb/eth_mac_phy_10g_fifo/Makefile index b7cc3d01..b92be278 100644 --- a/tb/eth_mac_phy_10g_fifo/Makefile +++ b/tb/eth_mac_phy_10g_fifo/Makefile @@ -67,8 +67,6 @@ export PARAM_RX_FRAME_FIFO := 1 export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO) export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME) export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME) -export PARAM_PTP_PERIOD_NS := 6 -export PARAM_PTP_PERIOD_FNS := 26214 export PARAM_PTP_TS_ENABLE := 1 export PARAM_PTP_TS_FMT_TOD := 1 export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96) diff --git a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py index 91c8118e..93c48606 100644 --- a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py +++ b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py @@ -435,8 +435,6 @@ def test_eth_mac_phy_10g_fifo(request, data_width, enable_dic): parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO'] parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME'] parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME'] - parameters['PTP_PERIOD_NS'] = 0x6 if parameters['DATA_WIDTH'] == 64 else 0x3 - parameters['PTP_PERIOD_FNS'] = 0x6666 if parameters['DATA_WIDTH'] == 64 else 0x3333 parameters['PTP_TS_ENABLE'] = 1 parameters['PTP_TS_FMT_TOD'] = 1 parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64