Adds if-conversion lowering for Intel platform.

Major changes include:

1. Adding `ccmp` (and promoted cmp) logic into emitter backend.
2. Hooking `TryLowerAndOrToCCMP` from ARM pathway into Intel pathway.
3. Hooking `optimizeCompareChainCondBlock` from ARM pathway into Intel
   pathway.

Author: anthonycanino

src/coreclr/jit/codegen.h

@@ -649,6 +649,7 @@ class CodeGen final : public CodeGenInterface
 #if defined(TARGET_AMD64)
     void genAmd64EmitterUnitTestsSse2();
     void genAmd64EmitterUnitTestsApx();
+    void genAmd64EmitterUnitTestsCCMP();
 #endif
 
 #endif // defined(DEBUG)
@@ -911,6 +912,9 @@ class CodeGen final : public CodeGenInterface
 #ifdef TARGET_ARM64
     void genCodeForCCMP(GenTreeCCMP* ccmp);
 #endif
+#ifdef TARGET_AMD64
+    void genCodeForCCMP(GenTreeCCMP* ccmp);
+#endif // TARGET_AMD64
     void genCodeForSelect(GenTreeOp* select);
     void genIntrinsic(GenTreeIntrinsic* treeNode);
     void genPutArgStk(GenTreePutArgStk* treeNode);
@@ -1655,6 +1659,8 @@ class CodeGen final : public CodeGenInterface
     static insOpts ShiftOpToInsOpts(genTreeOps op);
 #elif defined(TARGET_XARCH)
     static instruction JumpKindToCmov(emitJumpKind condition);
+    static instruction JumpKindToCcmp(emitJumpKind condition);
+    static insOpts     OptsFromCFlags(insCflags flags);
 #endif
 
 #if !defined(TARGET_LOONGARCH64) && !defined(TARGET_RISCV64)

src/coreclr/jit/codegenlinear.cpp

@@ -2702,6 +2702,10 @@ void CodeGen::genEmitterUnitTests()
     {
         genAmd64EmitterUnitTestsApx();
     }
+    if (unitTestSectionAll || (strstr(unitTestSection, "ccmp") != nullptr))
+    {
+        genAmd64EmitterUnitTestsCCMP();
+    }
 
 #elif defined(TARGET_ARM64)
     if (unitTestSectionAll || (strstr(unitTestSection, "general") != nullptr))

src/coreclr/jit/codegenxarch.cpp

@@ -2299,7 +2299,7 @@ void Compiler::compSetProcessor()
         if (canUseApxEncoding())
         {
             // TODO-Xarch-apx:
-            //   At this stage, since no machine will pass the CPUID check for APX, we need a special stress mode that 
+            //   At this stage, since no machine will pass the CPUID check for APX, we need a special stress mode that
             //   enables REX2 on incompatible platform, `DoJitStressRex2Encoding` is expected to be removed eventually.
             codeGen->GetEmitter()->SetUseRex2Encoding(true);
             codeGen->GetEmitter()->SetUsePromotedEVEXEncoding(true);

src/coreclr/jit/compiler.cpp

@@ -7091,6 +7091,8 @@ class Compiler
     bool optSwitchConvert(BasicBlock* firstBlock, int testsCount, ssize_t* testValues, weight_t falseLikelihood, GenTree* nodeToTest);
     bool optSwitchDetectAndConvert(BasicBlock* firstBlock);
 
+    bool optSwitchDetectLikely(BasicBlock* firstBlock);
+
     PhaseStatus optInvertLoops();    // Invert loops so they're entered at top and tested at bottom.
     PhaseStatus optOptimizeFlow();   // Simplify flow graph and do tail duplication
     PhaseStatus optOptimizeLayout(); // Optimize the BasicBlock layout of the method

src/coreclr/jit/compiler.h

@@ -797,9 +797,12 @@ class emitter
         unsigned _idCustom5 : 1;
         unsigned _idCustom6 : 1;
 
-#define _idEvexbContext   (_idCustom6 << 1) | _idCustom5 /* Evex.b: embedded broadcast, embedded rounding, embedded SAE */
-#define _idEvexNdContext  _idCustom5 /* bits used for the APX-EVEX.nd context for promoted legacy instructions */
-#define _idEvexNfContext  _idCustom6 /* bits used for the APX-EVEX.nf context for promoted legacy/vex instructions */
+#define _idEvexbContext (_idCustom6 << 1) | _idCustom5 /* Evex.b: embedded broadcast, embedded rounding, embedded SAE  \
+                                                        */
+#define _idEvexNdContext _idCustom5 /* bits used for the APX-EVEX.nd context for promoted legacy instructions */
+#define _idEvexNfContext _idCustom6 /* bits used for the APX-EVEX.nf context for promoted legacy/vex instructions */
+#define _idEvexDFV       (_idCustom4 << 3) | (_idCustom3 << 2) | (_idCustom2 << 1) | _idCustom1
+
 #endif //  TARGET_XARCH
 
 #ifdef TARGET_ARM64
@@ -1015,6 +1018,7 @@ class emitter
                 regNumber _idReg3 : REGNUM_BITS;
                 regNumber _idReg4 : REGNUM_BITS;
             };
+
 #elif defined(TARGET_LOONGARCH64)
             struct
             {
@@ -1674,7 +1678,6 @@ class emitter
 
             _idCustom5 = ((value >> 0) & 1);
             _idCustom6 = ((value >> 1) & 1);
-            
         }
 
         unsigned idGetEvexbContext() const
@@ -1736,6 +1739,21 @@ class emitter
             assert(!idIsEvexNfContextSet());
             _idEvexNfContext = 1;
         }
+
+        unsigned idGetEvexDFV() const
+        {
+            return _idEvexDFV;
+        }
+
+        void idSetEvexDFV(insOpts instOptions)
+        {
+            unsigned value = static_cast<unsigned>((instOptions & INS_OPTS_EVEX_dfv_MASK) >> 8);
+
+            _idCustom1 = ((value >> 0) & 1);
+            _idCustom2 = ((value >> 1) & 1);
+            _idCustom3 = ((value >> 2) & 1);
+            _idCustom4 = ((value >> 3) & 1);
+        }
 #endif
 
 #ifdef TARGET_ARMARCH

src/coreclr/jit/emit.h

@@ -8,6 +8,8 @@
 
 #if defined(TARGET_XARCH)
 
+// todo-anthony : should we define the cc for ccmp here?
+
 //       jump   reverse instruction
 JMP_SMALL(jmp   , jmp   , jmp    )
 JMP_SMALL(jo    , jno   , jo     )