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Improve support for 512-bit Vector<T> (#111472)
* improve support for 512-bit Vector<T> * fix size check * add MaxVectorTBitWidth configs to jitstress-isas-x86 pipeline * clamp Vector<T> size to largest accelerated fixed-sized vector * move PreferredVectorBitWidth logic to VM * tidying * tidying2
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40 files changed

+391
-596
lines changed

40 files changed

+391
-596
lines changed

‎eng/pipelines/common/templates/runtimes/run-test-job.yml

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -386,6 +386,9 @@ jobs:
386386
- jitstress_isas_x86_nosse41
387387
- jitstress_isas_x86_nosse42
388388
- jitstress_isas_x86_nossse3
389+
- jitstress_isas_x86_vectort128
390+
- jitstress_isas_x86_vectort512
391+
- jitstress_isas_x86_noavx512_vectort128
389392
- jitstress_isas_1_x86_noaes
390393
- jitstress_isas_1_x86_noavx
391394
- jitstress_isas_1_x86_noavx2

‎src/coreclr/inc/clrconfigvalues.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -688,6 +688,9 @@ RETAIL_CONFIG_DWORD_INFO(INTERNAL_GDBJitEmitDebugFrame, W("GDBJitEmitDebugFrame"
688688
#endif
689689

690690
RETAIL_CONFIG_DWORD_INFO_EX(EXTERNAL_MaxVectorTBitWidth, W("MaxVectorTBitWidth"), 0, "The maximum decimal width, in bits, that Vector<T> is allowed to be. A value less than 128 is treated as the system default.", CLRConfig::LookupOptions::ParseIntegerAsBase10)
691+
#if defined(TARGET_AMD64) || defined(TARGET_X86)
692+
RETAIL_CONFIG_DWORD_INFO_EX(EXTERNAL_PreferredVectorBitWidth, W("PreferredVectorBitWidth"), 0, "The maximum decimal width, in bits, of fixed-width vectors that may be considered hardware accelerated. A value less than 128 is treated as the system default.", CLRConfig::LookupOptions::ParseIntegerAsBase10)
693+
#endif // defined(TARGET_AMD64) || defined(TARGET_X86)
691694

692695
//
693696
// Hardware Intrinsic ISAs; keep in sync with jitconfigvalues.h

‎src/coreclr/inc/corjitflags.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -64,10 +64,6 @@ class CORJIT_FLAGS
6464
CORJIT_FLAG_SOFTFP_ABI = 30, // Enable armel calling convention
6565
#endif
6666

67-
#if defined(TARGET_X86) || defined(TARGET_AMD64)
68-
CORJIT_FLAG_VECTOR512_THROTTLING = 31, // On x86/x64, 512-bit vector usage may incur CPU frequency throttling
69-
#endif
70-
7167
};
7268

7369
CORJIT_FLAGS()

‎src/coreclr/inc/jiteeversionguid.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -37,11 +37,11 @@
3737

3838
#include <minipal/guid.h>
3939

40-
constexpr GUID JITEEVersionIdentifier = { /* 4463d6ac-dfcb-4ab0-a941-c53b56089b7c */
41-
0x4463d6ac,
42-
0xdfcb,
43-
0x4ab0,
44-
{0xa9, 0x41, 0xc5, 0x3b, 0x56, 0x08, 0x9b, 0x7c}
40+
constexpr GUID JITEEVersionIdentifier = { /* 78acb599-d9be-4ea1-8e93-546ec43e0487 */
41+
0x78acb599,
42+
0xd9be,
43+
0x4ea1,
44+
{0x8e, 0x93, 0x54, 0x6e, 0xc4, 0x3e, 0x04, 0x87}
4545
};
4646

4747
#endif // JIT_EE_VERSIONING_GUID_H

‎src/coreclr/jit/compiler.cpp

Lines changed: 28 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1984,9 +1984,34 @@ void Compiler::compSetProcessor()
19841984
// don't actually exist. The JIT is in charge of adding those and ensuring
19851985
// the total sum of flags is still valid.
19861986
#if defined(TARGET_XARCH)
1987-
// Get the preferred vector bitwidth, rounding down to the nearest multiple of 128-bits
1988-
uint32_t preferredVectorBitWidth = (ReinterpretHexAsDecimal(JitConfig.PreferredVectorBitWidth()) / 128) * 128;
1989-
uint32_t preferredVectorByteLength = preferredVectorBitWidth / 8;
1987+
// If the VM passed in a virtual vector ISA, it was done to communicate PreferredVectorBitWidth.
1988+
// No check is done for the validity of the value, since it will be clamped to max supported by
1989+
// hardware and config when queried. We will, therefore, remove the marker ISA and allow it to
1990+
// be re-added if appropriate based on the hardware ISA evaluations below.
1991+
1992+
uint32_t preferredVectorBitWidth = 0;
1993+
if (instructionSetFlags.HasInstructionSet(InstructionSet_Vector128))
1994+
{
1995+
instructionSetFlags.RemoveInstructionSet(InstructionSet_Vector128);
1996+
preferredVectorBitWidth = 128;
1997+
}
1998+
else if (instructionSetFlags.HasInstructionSet(InstructionSet_Vector256))
1999+
{
2000+
instructionSetFlags.RemoveInstructionSet(InstructionSet_Vector256);
2001+
preferredVectorBitWidth = 256;
2002+
}
2003+
else if (instructionSetFlags.HasInstructionSet(InstructionSet_Vector512))
2004+
{
2005+
instructionSetFlags.RemoveInstructionSet(InstructionSet_Vector512);
2006+
preferredVectorBitWidth = 512;
2007+
}
2008+
2009+
opts.preferredVectorByteLength = preferredVectorBitWidth / BITS_PER_BYTE;
2010+
2011+
// Only one marker ISA should have been passed in, and it should now be cleared.
2012+
assert(!instructionSetFlags.HasInstructionSet(InstructionSet_Vector128) &&
2013+
!instructionSetFlags.HasInstructionSet(InstructionSet_Vector256) &&
2014+
!instructionSetFlags.HasInstructionSet(InstructionSet_Vector512));
19902015

19912016
if (instructionSetFlags.HasInstructionSet(InstructionSet_SSE))
19922017
{
@@ -2018,29 +2043,13 @@ void Compiler::compSetProcessor()
20182043
assert(instructionSetFlags.HasInstructionSet(InstructionSet_AVX512DQ_VL));
20192044

20202045
instructionSetFlags.AddInstructionSet(InstructionSet_Vector512);
2021-
2022-
if ((preferredVectorByteLength == 0) && jitFlags.IsSet(JitFlags::JIT_FLAG_VECTOR512_THROTTLING))
2023-
{
2024-
// Some architectures can experience frequency throttling when
2025-
// executing 512-bit width instructions. To account for this we set the
2026-
// default preferred vector width to 256-bits in some scenarios. Power
2027-
// users can override this with `DOTNET_PreferredVectorBitWidth=512` to
2028-
// allow using such instructions where hardware support is available.
2029-
//
2030-
// Do not condition this based on stress mode as it makes the support
2031-
// reported inconsistent across methods and breaks expectations/functionality
2032-
2033-
preferredVectorByteLength = 256 / 8;
2034-
}
20352046
}
20362047
else
20372048
{
20382049
// We shouldn't have EVEX enabled if neither AVX512 nor AVX10v1 are supported
20392050
assert(instructionSetFlags.HasInstructionSet(InstructionSet_AVX10v1));
20402051
}
20412052
}
2042-
2043-
opts.preferredVectorByteLength = preferredVectorByteLength;
20442053
#elif defined(TARGET_ARM64)
20452054
if (instructionSetFlags.HasInstructionSet(InstructionSet_AdvSimd))
20462055
{

‎src/coreclr/jit/importer.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3861,7 +3861,7 @@ GenTree* Compiler::impImportStaticReadOnlyField(CORINFO_FIELD_HANDLE field, CORI
38613861
int simdWidth = getSIMDTypeSizeInBytes(fieldClsHnd);
38623862
if ((simdWidth > 0) && IsBaselineSimdIsaSupported())
38633863
{
3864-
assert((totalSize <= 32) && (totalSize <= MaxStructSize));
3864+
assert((totalSize <= 64) && (totalSize <= MaxStructSize));
38653865
var_types simdType = getSIMDTypeForSize(simdWidth);
38663866

38673867
bool hwAccelerated = true;

‎src/coreclr/jit/jitconfigvalues.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -381,8 +381,6 @@ CONFIG_INTEGER(JitStressPromotedEvexEncoding, "JitStressPromotedEvexEncoding", 0
381381
CONFIG_INTEGER(JitStressEvexEncoding, "JitStressEvexEncoding", 0)
382382
#endif
383383

384-
RELEASE_CONFIG_INTEGER(PreferredVectorBitWidth, "PreferredVectorBitWidth", 0) // The preferred decimal width, in bits, to use for any implicit vectorization emitted. A value less than 128 is treated as the system default.
385-
386384
//
387385
// Hardware Intrinsic ISAs; keep in sync with clrconfigvalues.h
388386
//

‎src/coreclr/jit/jitee.h

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,6 @@ class JitFlags
4444
JIT_FLAG_SOFTFP_ABI = 30, // Enable armel calling convention
4545
#endif
4646

47-
#if defined(TARGET_XARCH)
48-
JIT_FLAG_VECTOR512_THROTTLING = 31, // On Xarch, 512-bit vector usage may incur CPU frequency throttling
49-
#endif
50-
5147
// Note: the mcs tool uses the currently unused upper flags bits when outputting SuperPMI MC file flags.
5248
// See EXTRA_JIT_FLAGS and spmidumphelper.cpp. Currently, these are bits 56 through 63. If they overlap,
5349
// something needs to change.
@@ -147,10 +143,6 @@ class JitFlags
147143
FLAGS_EQUAL(CORJIT_FLAGS::CORJIT_FLAG_SOFTFP_ABI, JIT_FLAG_SOFTFP_ABI);
148144
#endif // TARGET_ARM
149145

150-
#if defined(TARGET_X86) || defined(TARGET_AMD64)
151-
FLAGS_EQUAL(CORJIT_FLAGS::CORJIT_FLAG_VECTOR512_THROTTLING, JIT_FLAG_VECTOR512_THROTTLING);
152-
#endif // TARGET_ARM
153-
154146
#undef FLAGS_EQUAL
155147
}
156148

‎src/coreclr/tools/Common/Compiler/InstructionSetSupport.cs

Lines changed: 16 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -11,34 +11,26 @@
1111

1212
namespace ILCompiler
1313
{
14-
[Flags]
15-
public enum InstructionSetSupportFlags
16-
{
17-
Vector512Throttling = 0x1,
18-
}
19-
2014
public class InstructionSetSupport
2115
{
2216
private readonly TargetArchitecture _targetArchitecture;
2317
private readonly InstructionSetFlags _optimisticInstructionSets;
2418
private readonly InstructionSetFlags _supportedInstructionSets;
2519
private readonly InstructionSetFlags _unsupportedInstructionSets;
2620
private readonly InstructionSetFlags _nonSpecifiableInstructionSets;
27-
private readonly InstructionSetSupportFlags _flags;
2821

2922
public InstructionSetSupport(InstructionSetFlags supportedInstructionSets, InstructionSetFlags unsupportedInstructionSets, TargetArchitecture architecture) :
3023
this(supportedInstructionSets, unsupportedInstructionSets, supportedInstructionSets, default(InstructionSetFlags), architecture)
3124
{
3225
}
3326

34-
public InstructionSetSupport(InstructionSetFlags supportedInstructionSets, InstructionSetFlags unsupportedInstructionSets, InstructionSetFlags optimisticInstructionSets, InstructionSetFlags nonSpecifiableInstructionSets, TargetArchitecture architecture, InstructionSetSupportFlags flags = 0)
27+
public InstructionSetSupport(InstructionSetFlags supportedInstructionSets, InstructionSetFlags unsupportedInstructionSets, InstructionSetFlags optimisticInstructionSets, InstructionSetFlags nonSpecifiableInstructionSets, TargetArchitecture architecture)
3528
{
3629
_supportedInstructionSets = supportedInstructionSets;
3730
_unsupportedInstructionSets = unsupportedInstructionSets;
3831
_optimisticInstructionSets = optimisticInstructionSets;
3932
_targetArchitecture = architecture;
4033
_nonSpecifiableInstructionSets = nonSpecifiableInstructionSets;
41-
_flags = flags;
4234
}
4335

4436
public bool IsInstructionSetSupported(InstructionSet instructionSet)
@@ -63,8 +55,6 @@ public bool IsInstructionSetExplicitlyUnsupported(InstructionSet instructionSet)
6355

6456
public TargetArchitecture Architecture => _targetArchitecture;
6557

66-
public InstructionSetSupportFlags Flags => _flags;
67-
6858
public static string GetHardwareIntrinsicId(TargetArchitecture architecture, TypeDesc potentialTypeDesc)
6959
{
7060
if (!potentialTypeDesc.IsIntrinsic || !(potentialTypeDesc is MetadataType potentialType))
@@ -121,10 +111,13 @@ public SimdVectorLength GetVectorTSimdVector()
121111
Debug.Assert(InstructionSet.X64_VectorT256 == InstructionSet.X86_VectorT256);
122112
Debug.Assert(InstructionSet.X64_VectorT512 == InstructionSet.X86_VectorT512);
123113

124-
// TODO-XArch: Add support for 512-bit Vector<T>
125-
Debug.Assert(!IsInstructionSetOptimisticallySupported(InstructionSet.X64_VectorT512));
126-
127-
if (IsInstructionSetOptimisticallySupported(InstructionSet.X64_VectorT256))
114+
if (IsInstructionSetOptimisticallySupported(InstructionSet.X64_VectorT512))
115+
{
116+
Debug.Assert(!IsInstructionSetOptimisticallySupported(InstructionSet.X64_VectorT128));
117+
Debug.Assert(!IsInstructionSetOptimisticallySupported(InstructionSet.X64_VectorT256));
118+
return SimdVectorLength.Vector512Bit;
119+
}
120+
else if (IsInstructionSetOptimisticallySupported(InstructionSet.X64_VectorT256))
128121
{
129122
Debug.Assert(!IsInstructionSetOptimisticallySupported(InstructionSet.X64_VectorT128));
130123
return SimdVectorLength.Vector256Bit;
@@ -437,15 +430,15 @@ public bool ComputeInstructionSetFlags(int maxVectorTBitWidth,
437430
Debug.Assert((maxVectorTBitWidth == 0) || (maxVectorTBitWidth >= 128));
438431
supportedInstructionSets.AddInstructionSet(InstructionSet.X86_VectorT128);
439432

440-
if (supportedInstructionSets.HasInstructionSet(InstructionSet.X86_AVX2))
433+
if (supportedInstructionSets.HasInstructionSet(InstructionSet.X86_AVX512F) && (maxVectorTBitWidth >= 512))
441434
{
442-
if ((maxVectorTBitWidth == 0) || (maxVectorTBitWidth >= 256))
443-
{
444-
supportedInstructionSets.RemoveInstructionSet(InstructionSet.X86_VectorT128);
445-
supportedInstructionSets.AddInstructionSet(InstructionSet.X86_VectorT256);
446-
}
447-
448-
// TODO-XArch: Add support for 512-bit Vector<T>
435+
supportedInstructionSets.RemoveInstructionSet(InstructionSet.X86_VectorT128);
436+
supportedInstructionSets.AddInstructionSet(InstructionSet.X86_VectorT512);
437+
}
438+
else if (supportedInstructionSets.HasInstructionSet(InstructionSet.X86_AVX2) && (maxVectorTBitWidth is 0 or >= 256))
439+
{
440+
supportedInstructionSets.RemoveInstructionSet(InstructionSet.X86_VectorT128);
441+
supportedInstructionSets.AddInstructionSet(InstructionSet.X86_VectorT256);
449442
}
450443
break;
451444
}

‎src/coreclr/tools/Common/InstructionSetHelpers.cs

Lines changed: 39 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,6 @@ public static InstructionSetSupport ConfigureInstructionSetSupport(string instru
2020
string mustNotBeMessage, string invalidImplicationMessage, Logger logger, bool optimizingForSize = false)
2121
{
2222
InstructionSetSupportBuilder instructionSetSupportBuilder = new(targetArchitecture);
23-
InstructionSetSupportFlags flags = 0;
2423

2524
// Ready to run images are built with certain instruction set baselines
2625
if ((targetArchitecture == TargetArchitecture.X86) || (targetArchitecture == TargetArchitecture.X64))
@@ -45,6 +44,8 @@ public static InstructionSetSupport ConfigureInstructionSetSupport(string instru
4544
// compile both branches of IsSupported checks.
4645
bool allowOptimistic = !optimizingForSize;
4746

47+
bool throttleAvx512 = false;
48+
4849
if (instructionSet == "native")
4950
{
5051
// We're compiling for a specific chip
@@ -92,7 +93,7 @@ public static InstructionSetSupport ConfigureInstructionSetSupport(string instru
9293
// * Cascade Lake
9394
// * Cooper Lake
9495

95-
flags |= InstructionSetSupportFlags.Vector512Throttling;
96+
throttleAvx512 = true;
9697
}
9798
}
9899
else if (extendedModel == 0x06)
@@ -101,13 +102,13 @@ public static InstructionSetSupport ConfigureInstructionSetSupport(string instru
101102
{
102103
// * Cannon Lake
103104

104-
flags |= InstructionSetSupportFlags.Vector512Throttling;
105+
throttleAvx512 = true;
105106
}
106107
}
107108
}
108109
}
109110

110-
if ((flags & InstructionSetSupportFlags.Vector512Throttling) != 0 && logger.IsVerbose)
111+
if (throttleAvx512 && logger.IsVerbose)
111112
logger.LogMessage("Vector512 is throttled");
112113
}
113114

@@ -180,7 +181,7 @@ public static InstructionSetSupport ConfigureInstructionSetSupport(string instru
180181
InstructionSetSupportBuilder optimisticInstructionSetSupportBuilder = new InstructionSetSupportBuilder(instructionSetSupportBuilder);
181182

182183
// Optimistically assume some instruction sets are present.
183-
if (allowOptimistic && (targetArchitecture == TargetArchitecture.X86 || targetArchitecture == TargetArchitecture.X64))
184+
if (allowOptimistic && targetArchitecture is TargetArchitecture.X86 or TargetArchitecture.X64)
184185
{
185186
// We set these hardware features as opportunistically enabled as most of hardware in the wild supports them.
186187
// Note that we do not indicate support for AVX, or any other instruction set which uses the VEX encodings as
@@ -235,7 +236,7 @@ public static InstructionSetSupport ConfigureInstructionSetSupport(string instru
235236
optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("gfni_v512");
236237
}
237238
}
238-
else if (targetArchitecture == TargetArchitecture.ARM64)
239+
else if (allowOptimistic && targetArchitecture is TargetArchitecture.ARM64)
239240
{
240241
optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("aes");
241242
optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("crc");
@@ -252,12 +253,42 @@ public static InstructionSetSupport ConfigureInstructionSetSupport(string instru
252253
optimisticInstructionSet.Remove(unsupportedInstructionSet);
253254
optimisticInstructionSet.Add(supportedInstructionSet);
254255

256+
if (throttleAvx512)
257+
{
258+
Debug.Assert(InstructionSet.X86_AVX512F == InstructionSet.X64_AVX512F);
259+
if (supportedInstructionSet.HasInstructionSet(InstructionSet.X86_AVX512F))
260+
{
261+
Debug.Assert(InstructionSet.X86_Vector256 == InstructionSet.X64_Vector256);
262+
Debug.Assert(InstructionSet.X86_VectorT256 == InstructionSet.X64_VectorT256);
263+
Debug.Assert(InstructionSet.X86_VectorT512 == InstructionSet.X64_VectorT512);
264+
265+
// AVX-512 is supported, but we are compiling specifically for hardware that has a performance penalty for
266+
// using 512-bit ops. We want to tell JIT not to consider Vector512 to be hardware accelerated, which we do
267+
// by passing a PreferredVectorBitWidth value, in the form of a virtual vector ISA of the appropriate size.
268+
//
269+
// If we are downgrading the max accelerated vector size, we also need to downgrade Vector<T> size.
270+
271+
supportedInstructionSet.AddInstructionSet(InstructionSet.X86_Vector256);
272+
273+
if (supportedInstructionSet.HasInstructionSet(InstructionSet.X86_VectorT512))
274+
{
275+
supportedInstructionSet.RemoveInstructionSet(InstructionSet.X86_VectorT512);
276+
supportedInstructionSet.AddInstructionSet(InstructionSet.X86_VectorT256);
277+
}
278+
279+
if (optimisticInstructionSet.HasInstructionSet(InstructionSet.X86_VectorT512))
280+
{
281+
optimisticInstructionSet.RemoveInstructionSet(InstructionSet.X86_VectorT512);
282+
optimisticInstructionSet.AddInstructionSet(InstructionSet.X86_VectorT256);
283+
}
284+
}
285+
}
286+
255287
return new InstructionSetSupport(supportedInstructionSet,
256288
unsupportedInstructionSet,
257289
optimisticInstructionSet,
258290
InstructionSetSupportBuilder.GetNonSpecifiableInstructionSetsForArch(targetArchitecture),
259-
targetArchitecture,
260-
flags);
291+
targetArchitecture);
261292
}
262293
}
263294
}

‎src/coreclr/tools/Common/JitInterface/CorInfoImpl.cs

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4216,9 +4216,6 @@ private uint getJitFlags(ref CORJIT_FLAGS flags, uint sizeInBytes)
42164216
case TargetArchitecture.X86:
42174217
Debug.Assert(InstructionSet.X86_SSE2 == InstructionSet.X64_SSE2);
42184218
Debug.Assert(_compilation.InstructionSetSupport.IsInstructionSetSupported(InstructionSet.X86_SSE2));
4219-
4220-
if ((_compilation.InstructionSetSupport.Flags & InstructionSetSupportFlags.Vector512Throttling) != 0)
4221-
flags.Set(CorJitFlag.CORJIT_FLAG_VECTOR512_THROTTLING);
42224219
break;
42234220

42244221
case TargetArchitecture.ARM64:

‎src/coreclr/tools/Common/JitInterface/CorInfoTypes.cs

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1403,9 +1403,6 @@ public enum CorJitFlag : uint
14031403
// ARM only
14041404
CORJIT_FLAG_RELATIVE_CODE_RELOCS = 29, // JIT should generate PC-relative address computations instead of EE relocation records
14051405
CORJIT_FLAG_SOFTFP_ABI = 30, // Enable armel calling convention
1406-
1407-
// x86/x64 only
1408-
CORJIT_FLAG_VECTOR512_THROTTLING = 31, // On x86/x64, 512-bit vector usage may incur CPU frequency throttling
14091406
}
14101407

14111408
public struct CORJIT_FLAGS

‎src/coreclr/tools/superpmi/superpmi-shared/methodcontext.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1240,11 +1240,6 @@ const char* CorJitFlagToString(CORJIT_FLAGS::CorJitFlag flag)
12401240
return "CORJIT_FLAG_SOFTFP_ABI";
12411241
#endif // defined(TARGET_ARM)
12421242

1243-
#if defined(TARGET_X86) || defined(TARGET_AMD64)
1244-
case CORJIT_FLAGS::CorJitFlag::CORJIT_FLAG_VECTOR512_THROTTLING:
1245-
return "CORJIT_FLAG_VECTOR512_THROTTLING";
1246-
#endif // defined(TARGET_XARCH)
1247-
12481243
default:
12491244
return "<unknown>";
12501245
}

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