From c5259920eadc1c21daf9d308f79e64b7f13de071 Mon Sep 17 00:00:00 2001
From: Dong Heng <dongheng@espressif.com>
Date: Thu, 12 Oct 2023 16:14:44 +0800
Subject: [PATCH] xtensa/esp32s3: Support to read data from flash to PSRAM

---
 arch/xtensa/src/esp32s3/esp32s3_spiflash.c | 94 +++++++++++++++++++---
 1 file changed, 84 insertions(+), 10 deletions(-)

diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiflash.c b/arch/xtensa/src/esp32s3/esp32s3_spiflash.c
index 837acedb9c8f2..5db389888c91b 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_spiflash.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_spiflash.c
@@ -250,6 +250,48 @@ static sem_t g_disable_non_iram_isr_on_core[CONFIG_SMP_NCPUS];
  * Private Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: spiflash_suspend_cache
+ *
+ * Description:
+ *   Suspend CPU cache.
+ *
+ ****************************************************************************/
+
+static void spiflash_suspend_cache(void)
+{
+  int cpu = up_cpu_index();
+#ifdef CONFIG_SMP
+  int other_cpu = cpu ? 0 : 1;
+#endif
+
+  spi_flash_disable_cache(cpu);
+#ifdef CONFIG_SMP
+  spi_flash_disable_cache(other_cpu);
+#endif
+}
+
+/****************************************************************************
+ * Name: spiflash_resume_cache
+ *
+ * Description:
+ *   Resume CPU cache.
+ *
+ ****************************************************************************/
+
+static void spiflash_resume_cache(void)
+{
+  int cpu = up_cpu_index();
+#ifdef CONFIG_SMP
+  int other_cpu = cpu ? 0 : 1;
+#endif
+
+  spi_flash_restore_cache(cpu);
+#ifdef CONFIG_SMP
+  spi_flash_restore_cache(other_cpu);
+#endif
+}
+
 /****************************************************************************
  * Name: spiflash_start
  *
@@ -304,11 +346,6 @@ static void spiflash_start(void)
   nxsched_set_priority(tcb, saved_priority);
 
   esp32s3_irq_noniram_disable();
-
-  spi_flash_disable_cache(cpu);
-#ifdef CONFIG_SMP
-  spi_flash_disable_cache(other_cpu);
-#endif
 }
 
 /****************************************************************************
@@ -334,11 +371,6 @@ static void spiflash_end(void)
   DEBUGASSERT(other_cpu != cpu);
 #endif
 
-  spi_flash_restore_cache(cpu);
-#ifdef CONFIG_SMP
-  spi_flash_restore_cache(other_cpu);
-#endif
-
   /* Signal to spi_flash_op_block_task that flash operation is complete */
 
   g_flash_op_complete = true;
@@ -812,6 +844,7 @@ int spi_flash_erase_range(uint32_t start_address, uint32_t size)
   uint32_t addr = start_address;
 
   spiflash_start();
+  spiflash_suspend_cache();
 
   for (uint32_t i = 0; i < size; i += FLASH_SECTOR_SIZE)
     {
@@ -825,6 +858,7 @@ int spi_flash_erase_range(uint32_t start_address, uint32_t size)
   wait_flash_idle();
   disable_flash_write();
 
+  spiflash_resume_cache();
   spiflash_end();
 
   return ret;
@@ -854,6 +888,9 @@ int spi_flash_write(uint32_t dest_addr, const void *buffer, uint32_t size)
   uint32_t tx_addr = dest_addr;
 
   spiflash_start();
+#ifndef CONFIG_ESP32S3_SPIRAM
+  spiflash_suspend_cache();
+#endif
 
   for (int i = 0; i < size; i += SPI_BUFFER_BYTES)
     {
@@ -862,11 +899,25 @@ int spi_flash_write(uint32_t dest_addr, const void *buffer, uint32_t size)
 
       memcpy(spi_buffer, tx_buf, n);
 
+#ifdef CONFIG_ESP32S3_SPIRAM
+
+      /* Disable cache, and then write data from SRAM to flash */
+
+      spiflash_suspend_cache();
+#endif
+
       wait_flash_idle();
       enable_flash_write();
 
       WRITE_DATA_TO_FLASH(tx_addr, spi_buffer, n);
 
+#ifdef CONFIG_ESP32S3_SPIRAM
+
+      /* Re-enable cache, and then copy data from PSRAM to SRAM */
+
+      spiflash_resume_cache();
+#endif
+
       tx_bytes -= n;
       tx_buf += n;
       tx_addr += n;
@@ -875,6 +926,9 @@ int spi_flash_write(uint32_t dest_addr, const void *buffer, uint32_t size)
   wait_flash_idle();
   disable_flash_write();
 
+#ifndef CONFIG_ESP32S3_SPIRAM
+  spiflash_resume_cache();
+#endif
   spiflash_end();
 
   return ret;
@@ -904,20 +958,40 @@ int spi_flash_read(uint32_t src_addr, void *dest, uint32_t size)
   uint32_t rx_addr = src_addr;
 
   spiflash_start();
+#ifndef CONFIG_ESP32S3_SPIRAM
+  spiflash_suspend_cache();
+#endif
 
   for (uint32_t i = 0; i < size; i += SPI_BUFFER_BYTES)
     {
       uint32_t spi_buffer[SPI_BUFFER_WORDS];
       uint32_t n = MIN(rx_bytes, SPI_BUFFER_BYTES);
 
+#ifdef CONFIG_ESP32S3_SPIRAM
+
+      /* Disable cache, and then read data from flash to SRAM */
+
+      spiflash_suspend_cache();
+#endif
+
       READ_DATA_FROM_FLASH(rx_addr, spi_buffer, n);
 
+#ifdef CONFIG_ESP32S3_SPIRAM
+
+      /* Re-enable cache, and then copy data from SRAM to PSRAM */
+
+      spiflash_resume_cache();
+#endif
+
       memcpy(rx_buf, spi_buffer, n);
       rx_bytes -= n;
       rx_buf += n;
       rx_addr += n;
     }
 
+#ifndef CONFIG_ESP32S3_SPIRAM
+  spiflash_resume_cache();
+#endif
   spiflash_end();
 
   return ret;