glossary.tex

\newglossaryentry{barricelli}
{
name=Barricelli,
description={is the name of the genetic algorithm-solving MIMD computer designed as a solution for the project documented in this report. Barricelli is also the name of a famous Norwegian-Italian mathematician, after whom the computer is named}
}

\newglossaryentry{galapagos}
{
name=Galapagos,
description={is the name of the instruction set architecture designed for the Barricelli computer}
}

\newglossaryentry{galapagos assembler}
{
name=Galapagos Assembler,
description={The assembler for Galapagos Assembly written in Python.}
}

\newglossaryentry{MIMD}
{
name=MIMD,
description={Multiple Instruction, Multiple Data}
}

\newglossaryentry{individual}
{
name=individual,
description={A single, feasible solution to a hard problem in genetic algorithms.}
}

\newglossaryentry{RISC}
{
name=RISC,
description={Reduced instruction set computing, a CPU design strategy focusing on simple instructions}
}

\newglossaryentry{MIPS}
{
name=MIPS,
description={Microprocessor without Interlocked Pipeline Stages, a RISC instruction set architecture}
}

\newglossaryentry{nop}
{
name=nop,
description={No OPeration, an assembly instruction that does not perform anything, used when one has to delay execution for a specific amount of clock cycles.}
}

\newglossaryentry{FPGA}
{
name=FPGA,
description={Field Programmable Gate Array, an integrated circuit that can be programmed to perform a variety of operations, for instance acting as a processor}
}

\newglossaryentry{DSP slice}
{
name=DSP slice,
description={Digital signal processor slices, dedicated circuitry in FGPAs that contain specialised components to perform certain operation as fast as possible}
}

\newglossaryentry{LUT}
{
name=LUT,
description={LookUp Table, one of the base component of FPGAs, basically large truth tables implemented in hardware}
}

\newglossaryentry{SCU}
{
name=SCU,
description={is the EFM32 microcontroller which is used as a System control unit}
}

\newglossaryentry{VHDL}
{
name=VHDL,
description={is the programming language in which the processor in implemented. VHDL is short for \gls{VHSIC} Hardware Description Language}
}

\newglossaryentry{VHSIC}
{
name=VHSIC,
description={is short for Very High-Speed Integrated Circuit}
}

\newglossaryentry{isim}
{
name=isim,
description={isim is a simulator part of the Xilinx developer suite}
}

\newglossaryentry{BRAM}
{
name=BRAM,
description={Block RAM, dedicated circuitry within a FPGA used as RAM}
}

\newglossaryentry{genetic controller}
{
name=Genetic controller,
description={The controller that controls the genetic pipeline}
}

\newglossaryentry{rated pool}
{
name=Rated pool,
description={A memory pool of individuals that have been evaluated and are ready for the selection stage of a genetic algorithm}
}

\newglossaryentry{unrated pool}
{
name=unrated controller,
description={A memory pool of "newborn" individuals that are ready to be evaluated}
}

\newglossaryentry{rated controller}
{
name=rated controller,
description={Memory controller responsible for the rated pool}
}

\newglossaryentry{unrated controller}
{
name=unrated controller,
description={Memory controller responsible for the rated pool}
}

\newglossaryentry{data controller}
{
name=data controller,
description={Memory controller responsible for the data memory access}
}

\newglossaryentry{ISA}
{
name=ISA,
description={Instruction Set Architecture, a set of opcodes and the native commands implemented by a particular processor}
}

\newglossaryentry{SRAM}
{
name=SRAM,
description={Static Random Access Memory, very fast RAM that is more expensive and less dense than dynamic RAM}
}

\newglossaryentry{harvard machine}
{
name=Harvard machine,
description={A computer architecture with physically separate instruction and data memory pools}
}

\newglossaryentry{search space}
{
name=Search space,
description={the collection of parameters to be searched over}
}

\newglossaryentry{EBI}
{
name=EBI,
description={External Bus Interface}
}