Merge pull request #636 from diffblue/synth-indexed-part-select

Verilog: Synthesis for indexed part select

Author: tautschnig

regression/verilog/part-select/indexed-part-select4.desc

@@ -1,9 +1,8 @@
-KNOWNBUG
+CORE
 indexed-part-select4.sv
 --bound 0
 ^EXIT=0$
 ^SIGNAL=0$
 --
 ^warning: ignoring
 --
-Synthesis-time constant folding for the index does not work.

src/verilog/verilog_synthesis.cpp

@@ -1060,20 +1060,24 @@ void verilog_synthesist::assignment_rec(
     const exprt &lhs_index = part_select.index();
     const exprt &lhs_width = part_select.width();
 
-    mp_integer index, width;
+    auto index_opt = synthesis_constant(lhs_index);
 
-    if(to_integer_non_constant(lhs_index, index))
+    if(!index_opt.has_value())
     {
       throw errort().with_location(lhs_index.source_location())
         << "failed to convert part select index";
     }
 
-    if(to_integer_non_constant(lhs_width, width))
+    auto width_opt = synthesis_constant(lhs_width);
+
+    if(!width_opt.has_value())
     {
       throw errort().with_location(lhs_width.source_location())
         << "failed to convert part select width";
     }
 
+    mp_integer index = *index_opt, width = *width_opt;
+
     // turn
     //   a[i]=e
     // into
@@ -1325,14 +1329,16 @@ void verilog_synthesist::assignment_member_rec(
     const exprt &lhs_index = part_select.index();
     const exprt &lhs_width = part_select.width();
 
-    mp_integer index, width;
+    auto index_opt = synthesis_constant(lhs_index);
 
-    if(to_integer_non_constant(lhs_index, index))
+    if(!index_opt.has_value())
     {
       throw errort().with_location(lhs_index.source_location())
         << "failed to convert part select index";
     }
 
+    mp_integer index = index_opt.value(), width;
+
     if(to_integer_non_constant(lhs_width, width))
     {
       throw errort().with_location(lhs_width.source_location())