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cscvon8
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cscvon8
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#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1110-g18392a46)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "C:\dev\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\dev\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\dev\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\dev\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\dev\iverilog\lib\ivl\va_math.vpi";
:vpi_module "C:\dev\iverilog\lib\ivl\v2009.vpi";
S_000001e73eff1ab0 .scope package, "$unit" "$unit" 2 1;
.timescale 0 0;
S_000001e73eff1c40 .scope module, "icarus_tb" "icarus_tb" 3 8;
.timescale -9 -12;
P_000001e73f055c10 .param/l "AddressSize" 0 3 10, +C4<00000000000000000000000000010000>;
P_000001e73f055c48 .param/l "HalfClock" 0 3 12, +C4<00000000000000000000000011100110>;
P_000001e73f055c80 .param/l "WordSize" 0 3 11, +C4<00000000000000000000000000001000>;
v000001e73f0fab50_0 .net "PCval", 15 0, L_000001e73f0fc130; 1 drivers
v000001e73f0faf10_0 .var "clk", 0 0;
v000001e73f0fae70_0 .var "counter", 3 0;
v000001e73f0fc090_0 .var "reset", 0 0;
E_000001e73f053ae0 .event negedge, v000001e73f07c430_0;
E_000001e73f052f60/0 .event negedge, v000001e73f07c430_0;
E_000001e73f052f60/1 .event posedge, v000001e73f07c430_0;
E_000001e73f052f60 .event/or E_000001e73f052f60/0, E_000001e73f052f60/1;
S_000001e73eff1dd0 .scope module, "DUT" "ttlcsvon8" 3 46, 4 16 0, S_000001e73eff1c40;
.timescale -9 -12;
.port_info 0 /INPUT 1 "i_clk";
.port_info 1 /INPUT 1 "reset";
.port_info 2 /OUTPUT 16 "PCval";
P_000001e73f0aad90 .param/l "AddressSize" 0 4 18, +C4<00000000000000000000000000010000>;
P_000001e73f0aadc8 .param/l "WordSize" 0 4 19, +C4<00000000000000000000000000001000>;
L_000001e73f065980/d .functor NOT 1, v000001e73f0faf10_0, C4<0>, C4<0>, C4<0>;
L_000001e73f065980 .delay 1 (5000,5000,5000) L_000001e73f065980/d;
L_000001e73f065440/d .functor NOT 1, L_000001e73f0fabf0, C4<0>, C4<0>, C4<0>;
L_000001e73f065440 .delay 1 (5000,5000,5000) L_000001e73f065440/d;
L_000001e73f065280 .functor OR 1, L_000001e73f0fcd10, L_000001e73f0fc950, C4<0>, C4<0>;
L_000001e73f065670/d .functor NOT 1, L_000001e73f0fdb70, C4<0>, C4<0>, C4<0>;
L_000001e73f065670 .delay 1 (5000,5000,5000) L_000001e73f065670/d;
L_000001e73f0656e0/d .functor NOT 1, L_000001e73f0fcbd0, C4<0>, C4<0>, C4<0>;
L_000001e73f0656e0 .delay 1 (5000,5000,5000) L_000001e73f0656e0/d;
L_000001e73f0654b0/d .functor NOT 1, L_000001e73f0fd850, C4<0>, C4<0>, C4<0>;
L_000001e73f0654b0 .delay 1 (5000,5000,5000) L_000001e73f0654b0/d;
L_000001e73f0652f0/d .functor NOT 1, L_000001e73f0fc8b0, C4<0>, C4<0>, C4<0>;
L_000001e73f0652f0 .delay 1 (5000,5000,5000) L_000001e73f0652f0/d;
L_000001e73f065360/d .functor NOT 1, L_000001e73f0fde90, C4<0>, C4<0>, C4<0>;
L_000001e73f065360 .delay 1 (5000,5000,5000) L_000001e73f065360/d;
L_000001e73f065b40 .functor AND 1, L_000001e73f065670, v000001e73f0fc090_0, C4<1>, C4<1>;
L_000001e73f065130 .functor BUFZ 16, L_000001e73f0fc130, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
v000001e73f0f8810_0 .net "AHload", 0 0, L_000001e73f0652f0; 1 drivers
v000001e73f0f9ad0_0 .net "AHval", 7 0, L_000001e73f0fd2b0; 1 drivers
v000001e73f0f84f0_0 .net "ALUena", 0 0, L_000001e73f0fdc10; 1 drivers
v000001e73f0f8a90_0 .net "ALUindex", 20 0, L_000001e73f14b260; 1 drivers
v000001e73f0f92b0_0 .net "ALUop", 4 0, L_000001e73f0fc810; 1 drivers
v000001e73f0f8bd0_0 .net "ALUresult", 15 0, L_000001e73f14c5c0; 1 drivers
v000001e73f0f90d0_0 .net "ALload", 0 0, L_000001e73f065360; 1 drivers
v000001e73f0f93f0_0 .net "ALval", 7 0, L_000001e73f0fd530; 1 drivers
v000001e73f0f9990_0 .net "ARena", 0 0, L_000001e73f0fa1f0; 1 drivers
v000001e73f0f9530_0 .net "Aload", 0 0, L_000001e73f0656e0; 1 drivers
v000001e73f0f8d10_0 .net "Aval", 7 0, L_000001e73f0fd170; 1 drivers
v000001e73f0f9030_0 .net "Bload", 0 0, L_000001e73f0654b0; 1 drivers
v000001e73f0f9b70_0 .net "Bval", 7 0, L_000001e73f0fcb30; 1 drivers
v000001e73f0f8090_0 .net "Carry", 0 0, L_000001e73f14ad60; 1 drivers
v000001e73f0f95d0_0 .net "DbusOp", 1 0, L_000001e73f0fc450; 1 drivers
v000001e73f0f81d0_0 .net "Decodeindex", 11 0, L_000001e73f0fb370; 1 drivers
v000001e73f0f9e90_0 .net "DivByZero", 0 0, L_000001e73f14b080; 1 drivers
v000001e73f0f8b30_0 .net "IOload", 0 0, L_000001e73f0fdf30; 1 drivers
v000001e73f0f9170_0 .net "IRload", 0 0, L_000001e73f065670; 1 drivers
v000001e73f0f86d0_0 .net "IRval", 7 0, L_000001e73f0fd030; 1 drivers
v000001e73f0f9670_0 .net "JumpOp", 2 0, L_000001e73f0fc770; 1 drivers
v000001e73f0f9710_0 .net "LoadOp", 2 0, L_000001e73f0fc630; 1 drivers
v000001e73f0f98f0_0 .net "MEMena", 0 0, L_000001e73f0fd210; 1 drivers
v000001e73f0f8c70_0 .net "MEMload", 0 0, L_000001e73f0fd990; 1 drivers
v000001e73f0f8e50_0 .net "MEMresult", 7 0, L_000001e73f0fdad0; 1 drivers
v000001e73f0f8130_0 .net "Negative", 0 0, L_000001e73f14bda0; 1 drivers
v000001e73f0f8770_0 .net "Overflow", 0 0, L_000001e73f14af40; 1 drivers
v000001e73f0f97b0_0 .net "PCcarry", 0 0, L_000001e73f064fe0; 1 drivers
v000001e73f0f9c10_0 .net "PChival", 7 0, L_000001e73f14ae00; 1 drivers
v000001e73f0f9850_0 .net "PCincr", 0 0, L_000001e73f0fc310; 1 drivers
v000001e73f0f9a30_0 .net "PCload", 0 0, L_000001e73f14c0c0; 1 drivers
v000001e73f0f9cb0_0 .net "PCload_bar", 0 0, L_000001e73f14bc60; 1 drivers
v000001e73f0f9d50_0 .net "PCloval", 7 0, L_000001e73f14b760; 1 drivers
v000001e73f0f9df0_0 .net "PCunused", 0 0, L_000001e73f065050; 1 drivers
v000001e73f0fc6d0_0 .net "PCval", 15 0, L_000001e73f0fc130; alias, 1 drivers
v000001e73f0fb9b0_0 .net "RAMresult", 7 0, L_000001e73f0fd710; 1 drivers
v000001e73f0fb7d0_0 .net "RAMselect", 0 0, L_000001e73f065440; 1 drivers
v000001e73f0fa150_0 .net "ROMresult", 7 0, L_000001e73f0fd7b0; 1 drivers
v000001e73f0fadd0_0 .net "ROMselect", 0 0, L_000001e73f0faa10; 1 drivers
v000001e73f0fa8d0_0 .net "Zero", 0 0, L_000001e73f14a5e0; 1 drivers
L_000001e73f0fe848 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f0fba50_0 .net/2u *"_ivl_134", 0 0, L_000001e73f0fe848; 1 drivers
L_000001e73f0fe890 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f0fac90_0 .net/2u *"_ivl_136", 0 0, L_000001e73f0fe890; 1 drivers
L_000001e73f0fe8d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f0fafb0_0 .net/2u *"_ivl_138", 0 0, L_000001e73f0fe8d8; 1 drivers
L_000001e73f0feba8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v000001e73f0fb870_0 .net/2u *"_ivl_142", 1 0, L_000001e73f0feba8; 1 drivers
v000001e73f0fbe10_0 .net *"_ivl_144", 0 0, L_000001e73f14aae0; 1 drivers
L_000001e73f0febf0 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v000001e73f0fc3b0_0 .net/2u *"_ivl_146", 1 0, L_000001e73f0febf0; 1 drivers
v000001e73f0fbaf0_0 .net *"_ivl_148", 0 0, L_000001e73f14a220; 1 drivers
v000001e73f0fa3d0_0 .net *"_ivl_151", 7 0, L_000001e73f14ab80; 1 drivers
o000001e73f0b3628 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
; Elide local net with no drivers, v000001e73f0fc590_0 name=_ivl_152
v000001e73f0fad30_0 .net *"_ivl_154", 7 0, L_000001e73f14bd00; 1 drivers
v000001e73f0fbb90_0 .net *"_ivl_33", 0 0, L_000001e73f0fabf0; 1 drivers
o000001e73f0b36b8 .functor BUFZ 1, C4<z>; HiZ drive
; Elide local net with no drivers, v000001e73f0fb230_0 name=_ivl_40
v000001e73f0fbc30_0 .net *"_ivl_42", 0 0, L_000001e73f0fcd10; 1 drivers
L_000001e73f0fe2f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f0fb910_0 .net/2u *"_ivl_44", 0 0, L_000001e73f0fe2f0; 1 drivers
v000001e73f0fc1d0_0 .net *"_ivl_46", 0 0, L_000001e73f0fc950; 1 drivers
v000001e73f0fa330_0 .net *"_ivl_49", 0 0, L_000001e73f065280; 1 drivers
v000001e73f0fa290_0 .net *"_ivl_57", 0 0, L_000001e73f0fdb70; 1 drivers
v000001e73f0fa970_0 .net *"_ivl_61", 0 0, L_000001e73f0fcbd0; 1 drivers
v000001e73f0fb0f0_0 .net *"_ivl_65", 0 0, L_000001e73f0fd850; 1 drivers
v000001e73f0fbcd0_0 .net *"_ivl_71", 0 0, L_000001e73f0fc8b0; 1 drivers
v000001e73f0fbd70_0 .net *"_ivl_75", 0 0, L_000001e73f0fde90; 1 drivers
L_000001e73f0fe3c8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v000001e73f0fb5f0_0 .net/2u *"_ivl_80", 1 0, L_000001e73f0fe3c8; 1 drivers
RS_000001e73f0b38c8 .resolv tri, L_000001e73f14ac20, L_000001e73f065130;
v000001e73f0fb690_0 .net8 "addressbus", 15 0, RS_000001e73f0b38c8; 2 drivers
v000001e73f0faab0_0 .net "clk_bar", 0 0, L_000001e73f065980; 1 drivers
v000001e73f0fb730_0 .net "controlbus", 15 0, L_000001e73f0fa830; 1 drivers
v000001e73f0fbeb0_0 .net "databus", 7 0, L_000001e73f14c3e0; 1 drivers
v000001e73f0fbf50_0 .net "dread_out", 7 0, L_000001e73f0657c0; 1 drivers
v000001e73f0fb410_0 .net "dwrite_in", 3 0, L_000001e73f0fd490; 1 drivers
v000001e73f0fa510_0 .net "dwrite_out", 7 0, L_000001e73f065ad0; 1 drivers
v000001e73f0fbff0_0 .net "i_clk", 0 0, v000001e73f0faf10_0; 1 drivers
v000001e73f0fb050_0 .net "jumpInput", 7 0, L_000001e73f14b120; 1 drivers
v000001e73f0fc4f0_0 .net "reset", 0 0, v000001e73f0fc090_0; 1 drivers
v000001e73f0fb190_0 .net "uSeq_unused", 0 0, L_000001e73f065600; 1 drivers
v000001e73f0fb2d0_0 .net "uSreset", 0 0, L_000001e73f0fc270; 1 drivers
v000001e73f0fa470_0 .net "uSval", 3 0, L_000001e73f065520; 1 drivers
L_000001e73f0fc130 .concat [ 8 8 0 0], L_000001e73f14b760, L_000001e73f14ae00;
L_000001e73f0fb370 .concat [ 4 8 0 0], L_000001e73f065520, L_000001e73f0fd030;
L_000001e73f0fc270 .part L_000001e73f0fa830, 15, 1;
L_000001e73f0fc310 .part L_000001e73f0fa830, 14, 1;
L_000001e73f0fa1f0 .part L_000001e73f0fa830, 13, 1;
L_000001e73f0fc770 .part L_000001e73f0fa830, 10, 3;
L_000001e73f0fc450 .part L_000001e73f0fa830, 8, 2;
L_000001e73f0fc630 .part L_000001e73f0fa830, 5, 3;
L_000001e73f0fc810 .part L_000001e73f0fa830, 0, 5;
L_000001e73f0faa10 .part RS_000001e73f0b38c8, 15, 1;
L_000001e73f0fabf0 .part RS_000001e73f0b38c8, 15, 1;
L_000001e73f0fcdb0 .part RS_000001e73f0b38c8, 0, 15;
L_000001e73f0fd3f0 .part RS_000001e73f0b38c8, 0, 15;
L_000001e73f0fcd10 .cmp/eeq 1, L_000001e73f0faa10, o000001e73f0b36b8;
L_000001e73f0fc950 .cmp/eeq 1, L_000001e73f0faa10, L_000001e73f0fe2f0;
L_000001e73f0fdad0 .functor MUXZ 8, L_000001e73f0fd710, L_000001e73f0fd7b0, L_000001e73f065280, C4<>;
L_000001e73f0fdb70 .part L_000001e73f0657c0, 1, 1;
L_000001e73f0fcbd0 .part L_000001e73f0657c0, 2, 1;
L_000001e73f0fd850 .part L_000001e73f0657c0, 3, 1;
L_000001e73f0fd990 .part L_000001e73f0657c0, 4, 1;
L_000001e73f0fc8b0 .part L_000001e73f0657c0, 5, 1;
L_000001e73f0fde90 .part L_000001e73f0657c0, 6, 1;
L_000001e73f0fdf30 .part L_000001e73f0657c0, 7, 1;
L_000001e73f0fd490 .concat [ 2 2 0 0], L_000001e73f0fc450, L_000001e73f0fe3c8;
L_000001e73f0fd210 .part L_000001e73f065ad0, 0, 1;
L_000001e73f0fdc10 .part L_000001e73f065ad0, 1, 1;
L_000001e73f14ac20 .concat [ 8 8 0 0], L_000001e73f0fd530, L_000001e73f0fd2b0;
L_000001e73f14c520 .part RS_000001e73f0b38c8, 0, 8;
L_000001e73f14bee0 .part RS_000001e73f0b38c8, 8, 8;
L_000001e73f14b260 .concat [ 8 8 5 0], L_000001e73f0fcb30, L_000001e73f0fd170, L_000001e73f0fc810;
L_000001e73f14b080 .part L_000001e73f14c5c0, 12, 1;
L_000001e73f14bda0 .part L_000001e73f14c5c0, 11, 1;
L_000001e73f14a5e0 .part L_000001e73f14c5c0, 10, 1;
L_000001e73f14af40 .part L_000001e73f14c5c0, 9, 1;
L_000001e73f14ad60 .part L_000001e73f14c5c0, 8, 1;
LS_000001e73f14b120_0_0 .concat [ 1 1 1 1], L_000001e73f0fe8d8, L_000001e73f14ad60, L_000001e73f14af40, L_000001e73f14a5e0;
LS_000001e73f14b120_0_4 .concat [ 1 1 1 1], L_000001e73f14bda0, L_000001e73f14b080, L_000001e73f0fe890, L_000001e73f0fe848;
L_000001e73f14b120 .concat [ 4 4 0 0], LS_000001e73f14b120_0_0, LS_000001e73f14b120_0_4;
L_000001e73f14aae0 .cmp/eq 2, L_000001e73f0fc450, L_000001e73f0feba8;
L_000001e73f14a220 .cmp/eq 2, L_000001e73f0fc450, L_000001e73f0febf0;
L_000001e73f14ab80 .part L_000001e73f14c5c0, 0, 8;
L_000001e73f14bd00 .functor MUXZ 8, o000001e73f0b3628, L_000001e73f14ab80, L_000001e73f14a220, C4<>;
L_000001e73f14c3e0 .functor MUXZ 8, L_000001e73f14bd00, L_000001e73f0fdad0, L_000001e73f14aae0, C4<>;
S_000001e73eff4420 .scope module, "A" "ttl_74574" 4 132, 5 5 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "Output_bar";
.port_info 1 /INPUT 1 "clk";
.port_info 2 /INPUT 8 "D";
.port_info 3 /OUTPUT 8 "Q";
P_000001e73eff45b0 .param/l "DELAY_FALL" 0 5 5, +C4<00000000000000000000000000000111>;
P_000001e73eff45e8 .param/l "DELAY_RISE" 0 5 5, +C4<00000000000000000000000000000111>;
P_000001e73eff4620 .param/l "WIDTH" 0 5 5, +C4<00000000000000000000000000001000>;
v000001e73f05b9a0_0 .net "D", 7 0, L_000001e73f14c3e0; alias, 1 drivers
L_000001e73f0fe458 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f05ca80_0 .net "Output_bar", 0 0, L_000001e73f0fe458; 1 drivers
v000001e73f05c760_0 .net "Q", 7 0, L_000001e73f0fd170; alias, 1 drivers
v000001e73f05c8a0_0 .var "Q_current", 7 0;
v000001e73f05b360_0 .net *"_ivl_1", 0 0, L_000001e73f0fddf0; 1 drivers
o000001e73f0b0178 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
; Elide local net with no drivers, v000001e73f05c940_0 name=_ivl_2
v000001e73f05c9e0_0 .net "clk", 0 0, L_000001e73f0656e0; alias, 1 drivers
E_000001e73f0530a0 .event posedge, v000001e73f05c9e0_0;
L_000001e73f0fddf0 .reduce/nor L_000001e73f0fe458;
L_000001e73f0fd170 .delay 8 (7000,7000,7000) L_000001e73f0fd170/d;
L_000001e73f0fd170/d .functor MUXZ 8, o000001e73f0b0178, v000001e73f05c8a0_0, L_000001e73f0fddf0, C4<>;
S_000001e73eff4660 .scope module, "AH" "ttl_74574" 4 135, 5 5 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "Output_bar";
.port_info 1 /INPUT 1 "clk";
.port_info 2 /INPUT 8 "D";
.port_info 3 /OUTPUT 8 "Q";
P_000001e73efe0870 .param/l "DELAY_FALL" 0 5 5, +C4<00000000000000000000000000000111>;
P_000001e73efe08a8 .param/l "DELAY_RISE" 0 5 5, +C4<00000000000000000000000000000111>;
P_000001e73efe08e0 .param/l "WIDTH" 0 5 5, +C4<00000000000000000000000000001000>;
v000001e73f05cb20_0 .net "D", 7 0, L_000001e73f14c3e0; alias, 1 drivers
v000001e73f05ba40_0 .net "Output_bar", 0 0, L_000001e73f0fa1f0; alias, 1 drivers
v000001e73f05cbc0_0 .net "Q", 7 0, L_000001e73f0fd2b0; alias, 1 drivers
v000001e73f05bc20_0 .var "Q_current", 7 0;
v000001e73f05cd00_0 .net *"_ivl_1", 0 0, L_000001e73f0fd0d0; 1 drivers
o000001e73f0b0358 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
; Elide local net with no drivers, v000001e73f05bae0_0 name=_ivl_2
v000001e73f05cda0_0 .net "clk", 0 0, L_000001e73f0652f0; alias, 1 drivers
E_000001e73f053120 .event posedge, v000001e73f05cda0_0;
L_000001e73f0fd0d0 .reduce/nor L_000001e73f0fa1f0;
L_000001e73f0fd2b0 .delay 8 (7000,7000,7000) L_000001e73f0fd2b0/d;
L_000001e73f0fd2b0/d .functor MUXZ 8, o000001e73f0b0358, v000001e73f05bc20_0, L_000001e73f0fd0d0, C4<>;
S_000001e73efdd650 .scope module, "AL" "ttl_74574" 4 136, 5 5 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "Output_bar";
.port_info 1 /INPUT 1 "clk";
.port_info 2 /INPUT 8 "D";
.port_info 3 /OUTPUT 8 "Q";
P_000001e73eff47f0 .param/l "DELAY_FALL" 0 5 5, +C4<00000000000000000000000000000111>;
P_000001e73eff4828 .param/l "DELAY_RISE" 0 5 5, +C4<00000000000000000000000000000111>;
P_000001e73eff4860 .param/l "WIDTH" 0 5 5, +C4<00000000000000000000000000001000>;
v000001e73f05bb80_0 .net "D", 7 0, L_000001e73f14c3e0; alias, 1 drivers
v000001e73f05b540_0 .net "Output_bar", 0 0, L_000001e73f0fa1f0; alias, 1 drivers
v000001e73f05b0e0_0 .net "Q", 7 0, L_000001e73f0fd530; alias, 1 drivers
v000001e73f05b220_0 .var "Q_current", 7 0;
v000001e73f05b4a0_0 .net *"_ivl_1", 0 0, L_000001e73f0fd350; 1 drivers
o000001e73f0b0508 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
; Elide local net with no drivers, v000001e73f05b5e0_0 name=_ivl_2
v000001e73f05b720_0 .net "clk", 0 0, L_000001e73f065360; alias, 1 drivers
E_000001e73f0532e0 .event posedge, v000001e73f05b720_0;
L_000001e73f0fd350 .reduce/nor L_000001e73f0fa1f0;
L_000001e73f0fd530 .delay 8 (7000,7000,7000) L_000001e73f0fd530/d;
L_000001e73f0fd530/d .functor MUXZ 8, o000001e73f0b0508, v000001e73f05b220_0, L_000001e73f0fd350, C4<>;
S_000001e73efdd7e0 .scope module, "ALU" "rom" 4 163, 6 4 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 21 "Address";
.port_info 1 /INOUT 16 "Data";
.port_info 2 /INPUT 1 "CS_bar";
.port_info 3 /INPUT 1 "OE_bar";
P_000001e73f05e3f0 .param/l "AddressSize" 0 6 6, +C4<00000000000000000000000000010101>;
P_000001e73f05e428 .param/l "DELAY_FALL" 0 6 10, +C4<00000000000000000000000000101101>;
P_000001e73f05e460 .param/l "DELAY_RISE" 0 6 9, +C4<00000000000000000000000000101101>;
P_000001e73f05e498 .param/str "Filename" 0 6 8, "alu.rom";
P_000001e73f05e4d0 .param/l "WordSize" 0 6 7, +C4<00000000000000000000000000010000>;
L_000001e73f0651a0 .functor AND 1, L_000001e73f14aa40, L_000001e73f14b940, C4<1>, C4<1>;
v000001e73f05b860_0 .net "Address", 20 0, L_000001e73f14b260; alias, 1 drivers
L_000001e73f0fe800 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f04b080_0 .net "CS_bar", 0 0, L_000001e73f0fe800; 1 drivers
v000001e73f04b260_0 .net "Data", 15 0, L_000001e73f14c5c0; alias, 1 drivers
v000001e73f04b300 .array "Mem", 2097151 0, 15 0;
v000001e73f049820_0 .net "OE_bar", 0 0, L_000001e73f0fdc10; alias, 1 drivers
v000001e73f04a680_0 .net *"_ivl_1", 0 0, L_000001e73f14aa40; 1 drivers
L_000001e73f0fe7b8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v000001e73f049c80_0 .net *"_ivl_11", 1 0, L_000001e73f0fe7b8; 1 drivers
o000001e73f0b0748 .functor BUFZ 16, C4<zzzzzzzzzzzzzzzz>; HiZ drive
; Elide local net with no drivers, v000001e73f04a4a0_0 name=_ivl_12
v000001e73f0328d0_0 .net *"_ivl_3", 0 0, L_000001e73f14b940; 1 drivers
v000001e73f032a10_0 .net *"_ivl_5", 0 0, L_000001e73f0651a0; 1 drivers
v000001e73f033050_0 .net *"_ivl_6", 15 0, L_000001e73f14c200; 1 drivers
v000001e73f0330f0_0 .net *"_ivl_8", 22 0, L_000001e73f14a180; 1 drivers
L_000001e73f14aa40 .reduce/nor L_000001e73f0fe800;
L_000001e73f14b940 .reduce/nor L_000001e73f0fdc10;
L_000001e73f14c200 .array/port v000001e73f04b300, L_000001e73f14a180;
L_000001e73f14a180 .concat [ 21 2 0 0], L_000001e73f14b260, L_000001e73f0fe7b8;
L_000001e73f14c5c0 .delay 16 (45000,45000,45000) L_000001e73f14c5c0/d;
L_000001e73f14c5c0/d .functor MUXZ 16, o000001e73f0b0748, L_000001e73f14c200, L_000001e73f0651a0, C4<>;
S_000001e73efdd970 .scope module, "B" "ttl_74574" 4 133, 5 5 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "Output_bar";
.port_info 1 /INPUT 1 "clk";
.port_info 2 /INPUT 8 "D";
.port_info 3 /OUTPUT 8 "Q";
P_000001e73efd0dc0 .param/l "DELAY_FALL" 0 5 5, +C4<00000000000000000000000000000111>;
P_000001e73efd0df8 .param/l "DELAY_RISE" 0 5 5, +C4<00000000000000000000000000000111>;
P_000001e73efd0e30 .param/l "WIDTH" 0 5 5, +C4<00000000000000000000000000001000>;
v000001e73f0317f0_0 .net "D", 7 0, L_000001e73f14c3e0; alias, 1 drivers
L_000001e73f0fe4a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f0319d0_0 .net "Output_bar", 0 0, L_000001e73f0fe4a0; 1 drivers
v000001e73f006750_0 .net "Q", 7 0, L_000001e73f0fcb30; alias, 1 drivers
v000001e73f006890_0 .var "Q_current", 7 0;
v000001e73f006cf0_0 .net *"_ivl_1", 0 0, L_000001e73f0fc9f0; 1 drivers
o000001e73f0b09b8 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
; Elide local net with no drivers, v000001e73f07ac40_0 name=_ivl_2
v000001e73f07bb40_0 .net "clk", 0 0, L_000001e73f0654b0; alias, 1 drivers
E_000001e73f050920 .event posedge, v000001e73f07bb40_0;
L_000001e73f0fc9f0 .reduce/nor L_000001e73f0fe4a0;
L_000001e73f0fcb30 .delay 8 (7000,7000,7000) L_000001e73f0fcb30/d;
L_000001e73f0fcb30/d .functor MUXZ 8, o000001e73f0b09b8, v000001e73f006890_0, L_000001e73f0fc9f0, C4<>;
S_000001e73efd0e70 .scope module, "Decoder" "rom" 4 81, 6 4 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 12 "Address";
.port_info 1 /INOUT 16 "Data";
.port_info 2 /INPUT 1 "CS_bar";
.port_info 3 /INPUT 1 "OE_bar";
P_000001e73f060b50 .param/l "AddressSize" 0 6 6, +C4<00000000000000000000000000001100>;
P_000001e73f060b88 .param/l "DELAY_FALL" 0 6 10, +C4<00000000000000000000000000101101>;
P_000001e73f060bc0 .param/l "DELAY_RISE" 0 6 9, +C4<00000000000000000000000000101101>;
P_000001e73f060bf8 .param/str "Filename" 0 6 8, "ucode.rom";
P_000001e73f060c30 .param/l "WordSize" 0 6 7, +C4<00000000000000000000000000010000>;
L_000001e73f0659f0 .functor AND 1, L_000001e73f0fa6f0, L_000001e73f0fa5b0, C4<1>, C4<1>;
v000001e73f07aba0_0 .net "Address", 11 0, L_000001e73f0fb370; alias, 1 drivers
L_000001e73f0fe1d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f07b5a0_0 .net "CS_bar", 0 0, L_000001e73f0fe1d0; 1 drivers
v000001e73f07a6a0_0 .net "Data", 15 0, L_000001e73f0fa830; alias, 1 drivers
v000001e73f07a240 .array "Mem", 4095 0, 15 0;
L_000001e73f0fe218 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f07a1a0_0 .net "OE_bar", 0 0, L_000001e73f0fe218; 1 drivers
v000001e73f07a740_0 .net *"_ivl_1", 0 0, L_000001e73f0fa6f0; 1 drivers
L_000001e73f0fe188 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v000001e73f07bbe0_0 .net *"_ivl_11", 1 0, L_000001e73f0fe188; 1 drivers
o000001e73f0b0bf8 .functor BUFZ 16, C4<zzzzzzzzzzzzzzzz>; HiZ drive
; Elide local net with no drivers, v000001e73f07b780_0 name=_ivl_12
v000001e73f07bd20_0 .net *"_ivl_3", 0 0, L_000001e73f0fa5b0; 1 drivers
v000001e73f07b6e0_0 .net *"_ivl_5", 0 0, L_000001e73f0659f0; 1 drivers
v000001e73f07ace0_0 .net *"_ivl_6", 15 0, L_000001e73f0fa650; 1 drivers
v000001e73f07bdc0_0 .net *"_ivl_8", 13 0, L_000001e73f0fa790; 1 drivers
L_000001e73f0fa6f0 .reduce/nor L_000001e73f0fe1d0;
L_000001e73f0fa5b0 .reduce/nor L_000001e73f0fe218;
L_000001e73f0fa650 .array/port v000001e73f07a240, L_000001e73f0fa790;
L_000001e73f0fa790 .concat [ 12 2 0 0], L_000001e73f0fb370, L_000001e73f0fe188;
L_000001e73f0fa830 .delay 16 (45000,45000,45000) L_000001e73f0fa830/d;
L_000001e73f0fa830/d .functor MUXZ 16, o000001e73f0b0bf8, L_000001e73f0fa650, L_000001e73f0659f0, C4<>;
S_000001e73efd1000 .scope module, "IR" "ttl_74574" 4 134, 5 5 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "Output_bar";
.port_info 1 /INPUT 1 "clk";
.port_info 2 /INPUT 8 "D";
.port_info 3 /OUTPUT 8 "Q";
P_000001e73efd1190 .param/l "DELAY_FALL" 0 5 5, +C4<00000000000000000000000000000111>;
P_000001e73efd11c8 .param/l "DELAY_RISE" 0 5 5, +C4<00000000000000000000000000000111>;
P_000001e73efd1200 .param/l "WIDTH" 0 5 5, +C4<00000000000000000000000000001000>;
v000001e73f07a920_0 .net "D", 7 0, L_000001e73f14c3e0; alias, 1 drivers
L_000001e73f0fe4e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f07a7e0_0 .net "Output_bar", 0 0, L_000001e73f0fe4e8; 1 drivers
v000001e73f07ad80_0 .net "Q", 7 0, L_000001e73f0fd030; alias, 1 drivers
v000001e73f07b820_0 .var "Q_current", 7 0;
v000001e73f07a880_0 .net *"_ivl_1", 0 0, L_000001e73f0fcf90; 1 drivers
o000001e73f0b0e68 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
; Elide local net with no drivers, v000001e73f07b320_0 name=_ivl_2
v000001e73f07b640_0 .net "clk", 0 0, L_000001e73f065b40; 1 drivers
E_000001e73f04fca0 .event posedge, v000001e73f07b640_0;
L_000001e73f0fcf90 .reduce/nor L_000001e73f0fe4e8;
L_000001e73f0fd030 .delay 8 (7000,7000,7000) L_000001e73f0fd030/d;
L_000001e73f0fd030/d .functor MUXZ 8, o000001e73f0b0e68, v000001e73f07b820_0, L_000001e73f0fcf90, C4<>;
S_000001e73efd7eb0 .scope module, "PChi" "ttl_74593" 4 151, 7 5 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "G";
.port_info 1 /INPUT 1 "G_bar";
.port_info 2 /INPUT 1 "CCK";
.port_info 3 /INPUT 1 "CCKEN";
.port_info 4 /INPUT 1 "CCKEN_bar";
.port_info 5 /INPUT 1 "CLOAD_bar";
.port_info 6 /INPUT 1 "CCLR_bar";
.port_info 7 /INPUT 1 "RCK";
.port_info 8 /INPUT 1 "RCKEN_bar";
.port_info 9 /OUTPUT 1 "RCO_bar";
.port_info 10 /OUTPUT 8 "Q";
.port_info 11 /INPUT 8 "inQ";
P_000001e73efd8040 .param/l "DELAY_FALL" 0 7 5, +C4<00000000000000000000000000011110>;
P_000001e73efd8078 .param/l "DELAY_RISE" 0 7 5, +C4<00000000000000000000000000011110>;
P_000001e73efd80b0 .param/l "WIDTH" 0 7 5, +C4<00000000000000000000000000001000>;
L_000001e73f065e50 .functor NOT 1, L_000001e73f14be40, C4<0>, C4<0>, C4<0>;
L_000001e73f065050/d .functor BUFZ 1, L_000001e73f065e50, C4<0>, C4<0>, C4<0>;
L_000001e73f065050 .delay 1 (30000,30000,30000) L_000001e73f065050/d;
L_000001e73f0fe698 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_000001e73f065d00 .functor NOT 1, L_000001e73f0fe698, C4<0>, C4<0>, C4<0>;
L_000001e73f0650c0 .functor AND 1, L_000001e73f0fa1f0, L_000001e73f065d00, C4<1>, C4<1>;
v000001e73f07a9c0_0 .net "CCK", 0 0, L_000001e73f064fe0; alias, 1 drivers
L_000001e73f0fe6e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f07ae20_0 .net "CCKEN", 0 0, L_000001e73f0fe6e0; 1 drivers
L_000001e73f0fe728 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f07aa60_0 .net "CCKEN_bar", 0 0, L_000001e73f0fe728; 1 drivers
v000001e73f07b960_0 .net "CCLR_bar", 0 0, v000001e73f0fc090_0; alias, 1 drivers
v000001e73f07b3c0_0 .net "CLOAD_bar", 0 0, L_000001e73f14bc60; alias, 1 drivers
v000001e73f07ab00_0 .var "Cntr", 7 0;
v000001e73f07baa0_0 .net "Cntr_next", 7 0, L_000001e73f14b580; 1 drivers
v000001e73f07aec0_0 .net "G", 0 0, L_000001e73f0fa1f0; alias, 1 drivers
v000001e73f07a380_0 .net "G_bar", 0 0, L_000001e73f0fe698; 1 drivers
v000001e73f07b8c0_0 .net "Q", 7 0, L_000001e73f14ae00; alias, 1 drivers
v000001e73f07bc80_0 .var "R", 7 0;
v000001e73f07af60_0 .net "RCK", 0 0, L_000001e73f065980; alias, 1 drivers
L_000001e73f0fe770 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f07ba00_0 .net "RCKEN_bar", 0 0, L_000001e73f0fe770; 1 drivers
v000001e73f07a2e0_0 .net "RCO_bar", 0 0, L_000001e73f065050; alias, 1 drivers
v000001e73f07b000_0 .net "RCO_current", 0 0, L_000001e73f065e50; 1 drivers
v000001e73f07b0a0_0 .net *"_ivl_1", 0 0, L_000001e73f14be40; 1 drivers
v000001e73f07b280_0 .net *"_ivl_10", 0 0, L_000001e73f065d00; 1 drivers
v000001e73f07b140_0 .net *"_ivl_13", 0 0, L_000001e73f0650c0; 1 drivers
o000001e73f0b12b8 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
; Elide local net with no drivers, v000001e73f07b1e0_0 name=_ivl_14
L_000001e73f0fe650 .functor BUFT 1, C4<00000001>, C4<0>, C4<0>, C4<0>;
v000001e73f07be60_0 .net/2u *"_ivl_4", 7 0, L_000001e73f0fe650; 1 drivers
v000001e73f07b460_0 .net "inQ", 7 0, L_000001e73f14bee0; 1 drivers
v000001e73f07b500_0 .var "prev_CCK", 0 0;
v000001e73f07bf00_0 .var "prev_CLOAD_bar", 0 0;
E_000001e73f04ff60 .event posedge, v000001e73f07af60_0;
E_000001e73f0508a0 .event posedge, v000001e73f07a9c0_0;
E_000001e73f04fd60 .event negedge, v000001e73f07a9c0_0;
E_000001e73f050660 .event posedge, v000001e73f07b3c0_0;
E_000001e73f0506e0 .event negedge, v000001e73f07b3c0_0;
L_000001e73f14be40 .reduce/and L_000001e73f14ae00;
L_000001e73f14b580 .arith/sum 8, v000001e73f07ab00_0, L_000001e73f0fe650;
L_000001e73f14ae00 .delay 8 (30000,30000,30000) L_000001e73f14ae00/d;
L_000001e73f14ae00/d .functor MUXZ 8, o000001e73f0b12b8, v000001e73f07ab00_0, L_000001e73f0650c0, C4<>;
S_000001e73efd81c0 .scope module, "PClo" "ttl_74593" 4 148, 7 5 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "G";
.port_info 1 /INPUT 1 "G_bar";
.port_info 2 /INPUT 1 "CCK";
.port_info 3 /INPUT 1 "CCKEN";
.port_info 4 /INPUT 1 "CCKEN_bar";
.port_info 5 /INPUT 1 "CLOAD_bar";
.port_info 6 /INPUT 1 "CCLR_bar";
.port_info 7 /INPUT 1 "RCK";
.port_info 8 /INPUT 1 "RCKEN_bar";
.port_info 9 /OUTPUT 1 "RCO_bar";
.port_info 10 /OUTPUT 8 "Q";
.port_info 11 /INPUT 8 "inQ";
P_000001e73f0adf30 .param/l "DELAY_FALL" 0 7 5, +C4<00000000000000000000000000011110>;
P_000001e73f0adf68 .param/l "DELAY_RISE" 0 7 5, +C4<00000000000000000000000000011110>;
P_000001e73f0adfa0 .param/l "WIDTH" 0 7 5, +C4<00000000000000000000000000001000>;
L_000001e73f065bb0 .functor NOT 1, L_000001e73f14afe0, C4<0>, C4<0>, C4<0>;
L_000001e73f064fe0/d .functor BUFZ 1, L_000001e73f065bb0, C4<0>, C4<0>, C4<0>;
L_000001e73f064fe0 .delay 1 (30000,30000,30000) L_000001e73f064fe0/d;
L_000001e73f0fe578 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_000001e73f065c20 .functor NOT 1, L_000001e73f0fe578, C4<0>, C4<0>, C4<0>;
L_000001e73f065c90 .functor AND 1, L_000001e73f0fa1f0, L_000001e73f065c20, C4<1>, C4<1>;
v000001e73f07a060_0 .net "CCK", 0 0, L_000001e73f065980; alias, 1 drivers
v000001e73f07a100_0 .net "CCKEN", 0 0, L_000001e73f0fc310; alias, 1 drivers
L_000001e73f0fe5c0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v000001e73f07a420_0 .net "CCKEN_bar", 0 0, L_000001e73f0fe5c0; 1 drivers
v000001e73f07a4c0_0 .net "CCLR_bar", 0 0, v000001e73f0fc090_0; alias, 1 drivers
v000001e73f07a560_0 .net "CLOAD_bar", 0 0, L_000001e73f14bc60; alias, 1 drivers
v000001e73f07a600_0 .var "Cntr", 7 0;
v000001e73f07cb10_0 .net "Cntr_next", 7 0, L_000001e73f14acc0; 1 drivers
v000001e73f07d650_0 .net "G", 0 0, L_000001e73f0fa1f0; alias, 1 drivers
v000001e73f07d510_0 .net "G_bar", 0 0, L_000001e73f0fe578; 1 drivers
v000001e73f07dbf0_0 .net "Q", 7 0, L_000001e73f14b760; alias, 1 drivers
v000001e73f07cf70_0 .var "R", 7 0;
v000001e73f07ca70_0 .net "RCK", 0 0, L_000001e73f065980; alias, 1 drivers
L_000001e73f0fe608 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f07d5b0_0 .net "RCKEN_bar", 0 0, L_000001e73f0fe608; 1 drivers
v000001e73f07d970_0 .net "RCO_bar", 0 0, L_000001e73f064fe0; alias, 1 drivers
v000001e73f07d330_0 .net "RCO_current", 0 0, L_000001e73f065bb0; 1 drivers
v000001e73f07d6f0_0 .net *"_ivl_1", 0 0, L_000001e73f14afe0; 1 drivers
v000001e73f07c570_0 .net *"_ivl_10", 0 0, L_000001e73f065c20; 1 drivers
v000001e73f07da10_0 .net *"_ivl_13", 0 0, L_000001e73f065c90; 1 drivers
o000001e73f0b1828 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
; Elide local net with no drivers, v000001e73f07dab0_0 name=_ivl_14
L_000001e73f0fe530 .functor BUFT 1, C4<00000001>, C4<0>, C4<0>, C4<0>;
v000001e73f07c4d0_0 .net/2u *"_ivl_4", 7 0, L_000001e73f0fe530; 1 drivers
v000001e73f07df10_0 .net "inQ", 7 0, L_000001e73f14c520; 1 drivers
v000001e73f07c6b0_0 .var "prev_CCK", 0 0;
v000001e73f07d3d0_0 .var "prev_CLOAD_bar", 0 0;
E_000001e73f04fce0 .event negedge, v000001e73f07af60_0;
L_000001e73f14afe0 .reduce/and L_000001e73f14b760;
L_000001e73f14acc0 .arith/sum 8, v000001e73f07a600_0, L_000001e73f0fe530;
L_000001e73f14b760 .delay 8 (30000,30000,30000) L_000001e73f14b760/d;
L_000001e73f14b760/d .functor MUXZ 8, o000001e73f0b1828, v000001e73f07a600_0, L_000001e73f065c90, C4<>;
S_000001e73f0ae0b0 .scope module, "RAM" "ram" 4 95, 8 4 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 15 "Address";
.port_info 1 /INPUT 8 "InData";
.port_info 2 /INPUT 1 "CS_bar";
.port_info 3 /INPUT 1 "WE_bar";
.port_info 4 /INPUT 1 "OE_bar";
.port_info 5 /OUTPUT 8 "OutData";
P_000001e73f05e870 .param/l "AddressSize" 0 8 6, +C4<00000000000000000000000000001111>;
P_000001e73f05e8a8 .param/l "DELAY_FALL" 0 8 10, +C4<00000000000000000000000000110111>;
P_000001e73f05e8e0 .param/l "DELAY_RISE" 0 8 9, +C4<00000000000000000000000000110111>;
P_000001e73f05e918 .param/str "Filename" 0 8 8, "empty.ram";
P_000001e73f05e950 .param/l "WordSize" 0 8 7, +C4<00000000000000000000000000001000>;
L_000001e73f065d70 .functor AND 1, L_000001e73f0fd670, L_000001e73f0fd8f0, C4<1>, C4<1>;
v000001e73f07c750_0 .net "Address", 14 0, L_000001e73f0fd3f0; 1 drivers
v000001e73f07c250_0 .net "CS_bar", 0 0, L_000001e73f065440; alias, 1 drivers
v000001e73f07c930_0 .net "InData", 7 0, L_000001e73f14c3e0; alias, 1 drivers
v000001e73f07c610 .array "Mem", 32767 0, 7 0;
v000001e73f07ccf0_0 .net "OE_bar", 0 0, L_000001e73f0fd210; alias, 1 drivers
v000001e73f07d790_0 .net "OutData", 7 0, L_000001e73f0fd710; alias, 1 drivers
v000001e73f07d830_0 .net "WE_bar", 0 0, L_000001e73f0fd990; alias, 1 drivers
v000001e73f07d8d0_0 .net *"_ivl_1", 0 0, L_000001e73f0fd670; 1 drivers
L_000001e73f0fe2a8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v000001e73f07cc50_0 .net *"_ivl_11", 1 0, L_000001e73f0fe2a8; 1 drivers
o000001e73f0b1ca8 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
; Elide local net with no drivers, v000001e73f07c7f0_0 name=_ivl_12
v000001e73f07db50_0 .net *"_ivl_3", 0 0, L_000001e73f0fd8f0; 1 drivers
v000001e73f07d470_0 .net *"_ivl_5", 0 0, L_000001e73f065d70; 1 drivers
v000001e73f07d0b0_0 .net *"_ivl_6", 7 0, L_000001e73f0fdcb0; 1 drivers
v000001e73f07d010_0 .net *"_ivl_8", 16 0, L_000001e73f0fda30; 1 drivers
E_000001e73f050760 .event negedge, v000001e73f07ccf0_0, v000001e73f07d830_0, v000001e73f07c250_0;
L_000001e73f0fd670 .reduce/nor L_000001e73f065440;
L_000001e73f0fd8f0 .reduce/nor L_000001e73f0fd210;
L_000001e73f0fdcb0 .array/port v000001e73f07c610, L_000001e73f0fda30;
L_000001e73f0fda30 .concat [ 15 2 0 0], L_000001e73f0fd3f0, L_000001e73f0fe2a8;
L_000001e73f0fd710 .delay 8 (55000,55000,55000) L_000001e73f0fd710/d;
L_000001e73f0fd710/d .functor MUXZ 8, o000001e73f0b1ca8, L_000001e73f0fdcb0, L_000001e73f065d70, C4<>;
S_000001e73f0ae240 .scope module, "ROM" "rom" 4 92, 6 4 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 15 "Address";
.port_info 1 /INOUT 8 "Data";
.port_info 2 /INPUT 1 "CS_bar";
.port_info 3 /INPUT 1 "OE_bar";
P_000001e73f05f170 .param/l "AddressSize" 0 6 6, +C4<00000000000000000000000000001111>;
P_000001e73f05f1a8 .param/l "DELAY_FALL" 0 6 10, +C4<00000000000000000000000010010110>;
P_000001e73f05f1e0 .param/l "DELAY_RISE" 0 6 9, +C4<00000000000000000000000010010110>;
P_000001e73f05f218 .param/str "Filename" 0 6 8, "instr.rom";
P_000001e73f05f250 .param/l "WordSize" 0 6 7, +C4<00000000000000000000000000001000>;
L_000001e73f065210 .functor AND 1, L_000001e73f0fb550, L_000001e73f0fcef0, C4<1>, C4<1>;
v000001e73f07ce30_0 .net "Address", 14 0, L_000001e73f0fcdb0; 1 drivers
v000001e73f07dc90_0 .net "CS_bar", 0 0, L_000001e73f0faa10; alias, 1 drivers
v000001e73f07d150_0 .net "Data", 7 0, L_000001e73f0fd7b0; alias, 1 drivers
v000001e73f07c9d0 .array "Mem", 32767 0, 7 0;
v000001e73f07cbb0_0 .net "OE_bar", 0 0, L_000001e73f0fd210; alias, 1 drivers
v000001e73f07dd30_0 .net *"_ivl_1", 0 0, L_000001e73f0fb550; 1 drivers
L_000001e73f0fe260 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v000001e73f07ddd0_0 .net *"_ivl_11", 1 0, L_000001e73f0fe260; 1 drivers
o000001e73f0b1fa8 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
; Elide local net with no drivers, v000001e73f07d1f0_0 name=_ivl_12
v000001e73f07c2f0_0 .net *"_ivl_3", 0 0, L_000001e73f0fcef0; 1 drivers
v000001e73f07c1b0_0 .net *"_ivl_5", 0 0, L_000001e73f065210; 1 drivers
v000001e73f07d290_0 .net *"_ivl_6", 7 0, L_000001e73f0fd5d0; 1 drivers
v000001e73f07de70_0 .net *"_ivl_8", 16 0, L_000001e73f0fca90; 1 drivers
L_000001e73f0fb550 .reduce/nor L_000001e73f0faa10;
L_000001e73f0fcef0 .reduce/nor L_000001e73f0fd210;
L_000001e73f0fd5d0 .array/port v000001e73f07c9d0, L_000001e73f0fca90;
L_000001e73f0fca90 .concat [ 15 2 0 0], L_000001e73f0fcdb0, L_000001e73f0fe260;
L_000001e73f0fd7b0 .delay 8 (150000,150000,150000) L_000001e73f0fd7b0/d;
L_000001e73f0fd7b0/d .functor MUXZ 8, o000001e73f0b1fa8, L_000001e73f0fd5d0, L_000001e73f065210, C4<>;
S_000001e73efee5c0 .scope module, "UART" "uart" 4 189, 9 4 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 8 "data";
.port_info 1 /INPUT 1 "TX";
v000001e73f07c070_0 .net "TX", 0 0, L_000001e73f0fdf30; alias, 1 drivers
v000001e73f07c110_0 .net "data", 7 0, L_000001e73f14c3e0; alias, 1 drivers
E_000001e73f04ffa0 .event negedge, v000001e73f07c070_0;
S_000001e73efee750 .scope module, "dbus_reader" "ttl_74138" 4 109, 10 5 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "Enable1_bar";
.port_info 1 /INPUT 1 "Enable2_bar";
.port_info 2 /INPUT 1 "Enable3";
.port_info 3 /INPUT 3 "A";
.port_info 4 /OUTPUT 8 "Y";
P_000001e73efee8e0 .param/l "DELAY_FALL" 0 10 6, +C4<00000000000000000000000000010101>;
P_000001e73efee918 .param/l "DELAY_RISE" 0 10 6, +C4<00000000000000000000000000010101>;
P_000001e73efee950 .param/l "WIDTH_IN" 0 10 5, +C4<00000000000000000000000000000011>;
P_000001e73efee988 .param/l "WIDTH_OUT" 0 10 5, +C4<00000000000000000000000000001000>;
L_000001e73f0657c0/d .functor BUFZ 8, v000001e73f0f5110_0, C4<00000000>, C4<00000000>, C4<00000000>;
L_000001e73f0657c0 .delay 8 (21000,21000,21000) L_000001e73f0657c0/d;
v000001e73f07c390_0 .net "A", 2 0, L_000001e73f0fc630; alias, 1 drivers
v000001e73f07c430_0 .net "Enable1_bar", 0 0, v000001e73f0faf10_0; alias, 1 drivers
L_000001e73f0fe338 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f07c890_0 .net "Enable2_bar", 0 0, L_000001e73f0fe338; 1 drivers
L_000001e73f0fe380 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v000001e73f07cd90_0 .net "Enable3", 0 0, L_000001e73f0fe380; 1 drivers
v000001e73f07ced0_0 .net "Y", 7 0, L_000001e73f0657c0; alias, 1 drivers
v000001e73f0f5110_0 .var "computed", 7 0;
v000001e73f0f6010_0 .var/i "i", 31 0;
E_000001e73f04ffe0 .event anyedge, v000001e73f07c430_0, v000001e73f07c890_0, v000001e73f07cd90_0, v000001e73f07c390_0;
S_000001e73efe7900 .scope module, "dbus_writer" "ttl_74139" 4 129, 11 5 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 2 "Enable_bar";
.port_info 1 /INPUT 4 "A_2D";
.port_info 2 /OUTPUT 8 "Y_2D";
P_000001e73f060910 .param/l "BLOCKS" 0 11 5, +C4<00000000000000000000000000000010>;
P_000001e73f060948 .param/l "DELAY_FALL" 0 11 7, +C4<00000000000000000000000000011001>;
P_000001e73f060980 .param/l "DELAY_RISE" 0 11 7, +C4<00000000000000000000000000011001>;
P_000001e73f0609b8 .param/l "WIDTH_IN" 0 11 6, +C4<00000000000000000000000000000010>;
P_000001e73f0609f0 .param/l "WIDTH_OUT" 0 11 5, +C4<00000000000000000000000000000100>;
L_000001e73f065830 .functor BUFZ 4, L_000001e73f0fd490, C4<0000>, C4<0000>, C4<0000>;
L_000001e73f065910 .functor BUFZ 8, L_000001e73f0fce50, C4<00000000>, C4<00000000>, C4<00000000>;
L_000001e73f065ad0/d .functor BUFZ 8, L_000001e73f065910, C4<00000000>, C4<00000000>, C4<00000000>;
L_000001e73f065ad0 .delay 8 (25000,25000,25000) L_000001e73f065ad0/d;
v000001e73f0f57f0 .array "A", 1 0;
v000001e73f0f57f0_0 .net v000001e73f0f57f0 0, 1 0, L_000001e73f0fcc70; 1 drivers
v000001e73f0f57f0_1 .net v000001e73f0f57f0 1, 1 0, L_000001e73f0fdd50; 1 drivers
v000001e73f0f6bf0_0 .net "A_2D", 3 0, L_000001e73f0fd490; alias, 1 drivers
L_000001e73f0fe410 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v000001e73f0f5430_0 .net "Enable_bar", 1 0, L_000001e73f0fe410; 1 drivers
v000001e73f0f6510_0 .net "PK_IN_BUS", 3 0, L_000001e73f065830; 1 drivers
v000001e73f0f6e70_0 .net "PK_OUT_BUS", 7 0, L_000001e73f0fce50; 1 drivers
v000001e73f0f68d0_0 .net "Y_2D", 7 0, L_000001e73f065ad0; alias, 1 drivers
v000001e73f0f5d90 .array "computed", 1 0, 3 0;
v000001e73f0f6830_0 .net "computed_2D", 7 0, L_000001e73f065910; 1 drivers
v000001e73f0f51b0_0 .var/i "i", 31 0;
v000001e73f0f5ed0_0 .var/i "j", 31 0;
E_000001e73f050960 .event anyedge, v000001e73f0f5430_0, v000001e73f0f57f0_0, v000001e73f0f57f0_1;
L_000001e73f0fcc70 .part L_000001e73f065830, 0, 2;
L_000001e73f0fdd50 .part L_000001e73f065830, 2, 2;
v000001e73f0f5d90_0 .array/port v000001e73f0f5d90, 0;
v000001e73f0f5d90_1 .array/port v000001e73f0f5d90, 1;
L_000001e73f0fce50 .concat8 [ 4 4 0 0], v000001e73f0f5d90_0, v000001e73f0f5d90_1;
S_000001e73f0f7d00 .scope generate, "genblk1[0]" "genblk1[0]" 11 38, 11 38 0, S_000001e73efe7900;
.timescale -9 -12;
P_000001e73f0502e0 .param/l "unpk_idx" 0 11 38, +C4<00>;
S_000001e73f0f7210 .scope generate, "genblk1[1]" "genblk1[1]" 11 38, 11 38 0, S_000001e73efe7900;
.timescale -9 -12;
P_000001e73f050c20 .param/l "unpk_idx" 0 11 38, +C4<01>;
S_000001e73f0f76c0 .scope generate, "genblk2[0]" "genblk2[0]" 11 39, 11 39 0, S_000001e73efe7900;
.timescale -9 -12;
P_000001e73f050b60 .param/l "pk_idx" 0 11 39, +C4<00>;
v000001e73f0f5a70_0 .net *"_ivl_2", 3 0, v000001e73f0f5d90_0; 1 drivers
S_000001e73f0f79e0 .scope generate, "genblk2[1]" "genblk2[1]" 11 39, 11 39 0, S_000001e73efe7900;
.timescale -9 -12;
P_000001e73f050020 .param/l "pk_idx" 0 11 39, +C4<01>;
v000001e73f0f6290_0 .net *"_ivl_2", 3 0, v000001e73f0f5d90_1; 1 drivers
S_000001e73f0f7e90 .scope module, "jumpLogic" "ttl_74151" 4 177, 12 5 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "Output_bar";
.port_info 1 /INPUT 8 "I";
.port_info 2 /INPUT 3 "S";
.port_info 3 /OUTPUT 1 "Y";
.port_info 4 /OUTPUT 1 "Y_bar";
P_000001e73f0aab90 .param/l "DELAY_FALL" 0 12 5, +C4<00000000000000000000000000010100>;
P_000001e73f0aabc8 .param/l "DELAY_RISE" 0 12 5, +C4<00000000000000000000000000010100>;
L_000001e73f030eb0 .functor NOT 1, L_000001e73f14bb20, C4<0>, C4<0>, C4<0>;
v000001e73f0f63d0_0 .net "I", 7 0, L_000001e73f14b120; alias, 1 drivers
v000001e73f0f5250_0 .net "Output_bar", 0 0, v000001e73f0faf10_0; alias, 1 drivers
v000001e73f0f6d30_0 .net "S", 2 0, L_000001e73f0fc770; alias, 1 drivers
v000001e73f0f5c50_0 .net "Y", 0 0, L_000001e73f14c0c0; alias, 1 drivers
v000001e73f0f6470_0 .net "Y_bar", 0 0, L_000001e73f14bc60; alias, 1 drivers
L_000001e73f0fe920 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>;
v000001e73f0f5e30_0 .net/2u *"_ivl_0", 2 0, L_000001e73f0fe920; 1 drivers
v000001e73f0f65b0_0 .net *"_ivl_11", 0 0, L_000001e73f14b1c0; 1 drivers
L_000001e73f0fe9b0 .functor BUFT 1, C4<010>, C4<0>, C4<0>, C4<0>;
v000001e73f0f56b0_0 .net/2u *"_ivl_12", 2 0, L_000001e73f0fe9b0; 1 drivers
v000001e73f0f5f70_0 .net *"_ivl_14", 0 0, L_000001e73f14a0e0; 1 drivers
v000001e73f0f52f0_0 .net *"_ivl_17", 0 0, L_000001e73f14aea0; 1 drivers
L_000001e73f0fe9f8 .functor BUFT 1, C4<011>, C4<0>, C4<0>, C4<0>;
v000001e73f0f5750_0 .net/2u *"_ivl_18", 2 0, L_000001e73f0fe9f8; 1 drivers
v000001e73f0f5cf0_0 .net *"_ivl_2", 0 0, L_000001e73f14c660; 1 drivers
v000001e73f0f6790_0 .net *"_ivl_20", 0 0, L_000001e73f14b9e0; 1 drivers
v000001e73f0f6970_0 .net *"_ivl_23", 0 0, L_000001e73f14a400; 1 drivers
L_000001e73f0fea40 .functor BUFT 1, C4<100>, C4<0>, C4<0>, C4<0>;
v000001e73f0f60b0_0 .net/2u *"_ivl_24", 2 0, L_000001e73f0fea40; 1 drivers
v000001e73f0f6150_0 .net *"_ivl_26", 0 0, L_000001e73f14b3a0; 1 drivers
v000001e73f0f61f0_0 .net *"_ivl_29", 0 0, L_000001e73f14b440; 1 drivers
L_000001e73f0fea88 .functor BUFT 1, C4<101>, C4<0>, C4<0>, C4<0>;
v000001e73f0f6330_0 .net/2u *"_ivl_30", 2 0, L_000001e73f0fea88; 1 drivers
v000001e73f0f6650_0 .net *"_ivl_32", 0 0, L_000001e73f14b4e0; 1 drivers
v000001e73f0f66f0_0 .net *"_ivl_35", 0 0, L_000001e73f14b800; 1 drivers
L_000001e73f0fead0 .functor BUFT 1, C4<110>, C4<0>, C4<0>, C4<0>;
v000001e73f0f6a10_0 .net/2u *"_ivl_36", 2 0, L_000001e73f0fead0; 1 drivers
v000001e73f0f5390_0 .net *"_ivl_38", 0 0, L_000001e73f14a360; 1 drivers
v000001e73f0f6ab0_0 .net *"_ivl_41", 0 0, L_000001e73f14a9a0; 1 drivers
v000001e73f0f6b50_0 .net *"_ivl_43", 0 0, L_000001e73f14c480; 1 drivers
v000001e73f0f6c90_0 .net *"_ivl_44", 0 0, L_000001e73f14bf80; 1 drivers
v000001e73f0f5890_0 .net *"_ivl_46", 0 0, L_000001e73f14b620; 1 drivers
v000001e73f0f5b10_0 .net *"_ivl_48", 0 0, L_000001e73f14b6c0; 1 drivers
v000001e73f0f6dd0_0 .net *"_ivl_5", 0 0, L_000001e73f14a900; 1 drivers
v000001e73f0f6f10_0 .net *"_ivl_50", 0 0, L_000001e73f14b8a0; 1 drivers
v000001e73f0f5930_0 .net *"_ivl_52", 0 0, L_000001e73f14ba80; 1 drivers
v000001e73f0f5070_0 .net *"_ivl_54", 0 0, L_000001e73f14c020; 1 drivers
L_000001e73f0fe968 .functor BUFT 1, C4<001>, C4<0>, C4<0>, C4<0>;
v000001e73f0f54d0_0 .net/2u *"_ivl_6", 2 0, L_000001e73f0fe968; 1 drivers
v000001e73f0f5570_0 .net *"_ivl_61", 0 0, L_000001e73f14bbc0; 1 drivers
L_000001e73f0feb18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001e73f0f5610_0 .net/2u *"_ivl_62", 0 0, L_000001e73f0feb18; 1 drivers
v000001e73f0f59d0_0 .net *"_ivl_67", 0 0, L_000001e73f14c700; 1 drivers
L_000001e73f0feb60 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v000001e73f0f5bb0_0 .net/2u *"_ivl_68", 0 0, L_000001e73f0feb60; 1 drivers
v000001e73f0f83b0_0 .net *"_ivl_8", 0 0, L_000001e73f14b300; 1 drivers
v000001e73f0f9490_0 .net "internal_Y", 0 0, L_000001e73f14bb20; 1 drivers
v000001e73f0f8950_0 .net "internal_Y_bar", 0 0, L_000001e73f030eb0; 1 drivers
L_000001e73f14c660 .cmp/eq 3, L_000001e73f0fc770, L_000001e73f0fe920;
L_000001e73f14a900 .part L_000001e73f14b120, 0, 1;
L_000001e73f14b300 .cmp/eq 3, L_000001e73f0fc770, L_000001e73f0fe968;
L_000001e73f14b1c0 .part L_000001e73f14b120, 1, 1;
L_000001e73f14a0e0 .cmp/eq 3, L_000001e73f0fc770, L_000001e73f0fe9b0;
L_000001e73f14aea0 .part L_000001e73f14b120, 2, 1;
L_000001e73f14b9e0 .cmp/eq 3, L_000001e73f0fc770, L_000001e73f0fe9f8;
L_000001e73f14a400 .part L_000001e73f14b120, 3, 1;
L_000001e73f14b3a0 .cmp/eq 3, L_000001e73f0fc770, L_000001e73f0fea40;
L_000001e73f14b440 .part L_000001e73f14b120, 4, 1;
L_000001e73f14b4e0 .cmp/eq 3, L_000001e73f0fc770, L_000001e73f0fea88;
L_000001e73f14b800 .part L_000001e73f14b120, 5, 1;
L_000001e73f14a360 .cmp/eq 3, L_000001e73f0fc770, L_000001e73f0fead0;
L_000001e73f14a9a0 .part L_000001e73f14b120, 6, 1;
L_000001e73f14c480 .part L_000001e73f14b120, 7, 1;
L_000001e73f14bf80 .functor MUXZ 1, L_000001e73f14c480, L_000001e73f14a9a0, L_000001e73f14a360, C4<>;
L_000001e73f14b620 .functor MUXZ 1, L_000001e73f14bf80, L_000001e73f14b800, L_000001e73f14b4e0, C4<>;
L_000001e73f14b6c0 .functor MUXZ 1, L_000001e73f14b620, L_000001e73f14b440, L_000001e73f14b3a0, C4<>;
L_000001e73f14b8a0 .functor MUXZ 1, L_000001e73f14b6c0, L_000001e73f14a400, L_000001e73f14b9e0, C4<>;
L_000001e73f14ba80 .functor MUXZ 1, L_000001e73f14b8a0, L_000001e73f14aea0, L_000001e73f14a0e0, C4<>;
L_000001e73f14c020 .functor MUXZ 1, L_000001e73f14ba80, L_000001e73f14b1c0, L_000001e73f14b300, C4<>;
L_000001e73f14bb20 .functor MUXZ 1, L_000001e73f14c020, L_000001e73f14a900, L_000001e73f14c660, C4<>;
L_000001e73f14bbc0 .reduce/nor v000001e73f0faf10_0;
L_000001e73f14c0c0 .delay 1 (20000,20000,20000) L_000001e73f14c0c0/d;
L_000001e73f14c0c0/d .functor MUXZ 1, L_000001e73f0feb18, L_000001e73f14bb20, L_000001e73f14bbc0, C4<>;
L_000001e73f14c700 .reduce/nor v000001e73f0faf10_0;
L_000001e73f14bc60 .delay 1 (20000,20000,20000) L_000001e73f14bc60/d;
L_000001e73f14bc60/d .functor MUXZ 1, L_000001e73f0feb60, L_000001e73f030eb0, L_000001e73f14c700, C4<>;
S_000001e73f0f73a0 .scope module, "uSeq" "ttl_74161" 4 77, 13 5 0, S_000001e73eff1dd0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "Clear_bar";
.port_info 1 /INPUT 1 "Load_bar";
.port_info 2 /INPUT 1 "ENT";
.port_info 3 /INPUT 1 "ENP";
.port_info 4 /INPUT 4 "D";
.port_info 5 /INPUT 1 "Clk";
.port_info 6 /OUTPUT 1 "RCO";
.port_info 7 /OUTPUT 4 "Q";
P_000001e73efee9d0 .param/l "DELAY_FALL" 0 13 5, +C4<00000000000000000000000000010110>;
P_000001e73efeea08 .param/l "DELAY_RISE" 0 13 5, +C4<00000000000000000000000000010110>;
P_000001e73efeea40 .param/l "WIDTH" 0 13 5, +C4<00000000000000000000000000000100>;
L_000001e73f0fe0b0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
L_000001e73f065a60 .functor AND 1, L_000001e73f0fe0b0, L_000001e73f0fb4b0, C4<1>, C4<1>;
L_000001e73f065600/d .functor BUFZ 1, L_000001e73f065a60, C4<0>, C4<0>, C4<0>;
L_000001e73f065600 .delay 1 (22000,22000,22000) L_000001e73f065600/d;
L_000001e73f065520/d .functor BUFZ 4, v000001e73f0f8310_0, C4<0000>, C4<0000>, C4<0000>;
L_000001e73f065520 .delay 4 (22000,22000,22000) L_000001e73f065520/d;
v000001e73f0f88b0_0 .net "Clear_bar", 0 0, v000001e73f0fc090_0; alias, 1 drivers
v000001e73f0f9f30_0 .net "Clk", 0 0, v000001e73f0faf10_0; alias, 1 drivers
L_000001e73f0fe140 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>;
v000001e73f0f8db0_0 .net "D", 3 0, L_000001e73f0fe140; 1 drivers
L_000001e73f0fe0f8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v000001e73f0f8590_0 .net "ENP", 0 0, L_000001e73f0fe0f8; 1 drivers
v000001e73f0f8450_0 .net "ENT", 0 0, L_000001e73f0fe0b0; 1 drivers
v000001e73f0f8ef0_0 .net "Load_bar", 0 0, L_000001e73f0fc270; alias, 1 drivers
v000001e73f0f8270_0 .net "Q", 3 0, L_000001e73f065520; alias, 1 drivers
v000001e73f0f8310_0 .var "Q_current", 3 0;
v000001e73f0f9210_0 .net "Q_next", 3 0, L_000001e73f0fa0b0; 1 drivers
v000001e73f0f9350_0 .net "RCO", 0 0, L_000001e73f065600; alias, 1 drivers
v000001e73f0f8f90_0 .net "RCO_current", 0 0, L_000001e73f065a60; 1 drivers
L_000001e73f0fe068 .functor BUFT 1, C4<0001>, C4<0>, C4<0>, C4<0>;
v000001e73f0f89f0_0 .net/2u *"_ivl_0", 3 0, L_000001e73f0fe068; 1 drivers
v000001e73f0f8630_0 .net *"_ivl_5", 0 0, L_000001e73f0fb4b0; 1 drivers
E_000001e73f050860/0 .event negedge, v000001e73f07b960_0;
E_000001e73f050860/1 .event posedge, v000001e73f07c430_0;
E_000001e73f050860 .event/or E_000001e73f050860/0, E_000001e73f050860/1;
L_000001e73f0fa0b0 .arith/sum 4, v000001e73f0f8310_0, L_000001e73f0fe068;
L_000001e73f0fb4b0 .reduce/and v000001e73f0f8310_0;
.scope S_000001e73f0f73a0;
T_0 ;
%wait E_000001e73f050860;
%load/vec4 v000001e73f0f88b0_0;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_0.0, 8;
%pushi/vec4 0, 0, 4;
%assign/vec4 v000001e73f0f8310_0, 0;
%jmp T_0.1;
T_0.0 ;
%load/vec4 v000001e73f0f8ef0_0;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_0.2, 8;
%load/vec4 v000001e73f0f8db0_0;
%assign/vec4 v000001e73f0f8310_0, 0;
T_0.2 ;
%load/vec4 v000001e73f0f8ef0_0;
%load/vec4 v000001e73f0f8450_0;
%and;
%load/vec4 v000001e73f0f8590_0;
%and;
%flag_set/vec4 8;
%jmp/0xz T_0.4, 8;
%load/vec4 v000001e73f0f9210_0;
%assign/vec4 v000001e73f0f8310_0, 0;
T_0.4 ;
T_0.1 ;
%jmp T_0;
.thread T_0;
.scope S_000001e73efd0e70;
T_1 ;
%vpi_call/w 6 20 "$readmemh", P_000001e73f060bf8, v000001e73f07a240 {0 0 0};
%end;
.thread T_1;
.scope S_000001e73f0ae240;
T_2 ;
%vpi_call/w 6 20 "$readmemh", P_000001e73f05f218, v000001e73f07c9d0 {0 0 0};
%end;
.thread T_2;
.scope S_000001e73f0ae0b0;
T_3 ;
%vpi_call/w 8 21 "$readmemh", P_000001e73f05e918, v000001e73f07c610 {0 0 0};
%end;
.thread T_3;
.scope S_000001e73f0ae0b0;
T_4 ;
%wait E_000001e73f050760;
%load/vec4 v000001e73f07c250_0;
%nor/r;
%load/vec4 v000001e73f07d830_0;
%nor/r;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.0, 8;
%load/vec4 v000001e73f07c930_0;
%load/vec4 v000001e73f07c750_0;
%pad/u 17;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v000001e73f07c610, 0, 4;
T_4.0 ;
%load/vec4 v000001e73f07d830_0;
%nor/r;
%load/vec4 v000001e73f07ccf0_0;
%nor/r;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.2, 8;
%vpi_call/w 8 36 "$display", "ram error: both OE_bar & WE_bar active" {0 0 0};
T_4.2 ;
%jmp T_4;
.thread T_4;
.scope S_000001e73efee750;
T_5 ;
%wait E_000001e73f04ffe0;
%pushi/vec4 0, 0, 32;
%store/vec4 v000001e73f0f6010_0, 0, 32;
T_5.0 ;
%load/vec4 v000001e73f0f6010_0;
%cmpi/s 8, 0, 32;
%jmp/0xz T_5.1, 5;
%load/vec4 v000001e73f07c430_0;
%nor/r;
%load/vec4 v000001e73f07c890_0;
%nor/r;
%and;
%load/vec4 v000001e73f07cd90_0;
%and;
%load/vec4 v000001e73f0f6010_0;
%load/vec4 v000001e73f07c390_0;
%pad/u 32;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_5.2, 8;
%pushi/vec4 0, 0, 1;
%ix/getv/s 4, v000001e73f0f6010_0;
%store/vec4 v000001e73f0f5110_0, 4, 1;
%jmp T_5.3;
T_5.2 ;
%pushi/vec4 1, 0, 1;
%ix/getv/s 4, v000001e73f0f6010_0;
%store/vec4 v000001e73f0f5110_0, 4, 1;
T_5.3 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v000001e73f0f6010_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v000001e73f0f6010_0, 0, 32;
%jmp T_5.0;
T_5.1 ;
%jmp T_5;
.thread T_5, $push;
.scope S_000001e73efe7900;
T_6 ;
%wait E_000001e73f050960;
%pushi/vec4 0, 0, 32;
%store/vec4 v000001e73f0f51b0_0, 0, 32;
T_6.0 ;
%load/vec4 v000001e73f0f51b0_0;
%cmpi/s 2, 0, 32;
%jmp/0xz T_6.1, 5;
%pushi/vec4 0, 0, 32;
%store/vec4 v000001e73f0f5ed0_0, 0, 32;
T_6.2 ;
%load/vec4 v000001e73f0f5ed0_0;
%cmpi/s 4, 0, 32;
%jmp/0xz T_6.3, 5;
%load/vec4 v000001e73f0f5430_0;
%load/vec4 v000001e73f0f51b0_0;
%part/s 1;
%nor/r;
%load/vec4 v000001e73f0f5ed0_0;
%ix/getv/s 4, v000001e73f0f51b0_0;
%load/vec4a v000001e73f0f57f0, 4;
%pad/u 32;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_6.4, 8;
%pushi/vec4 0, 0, 1;
%ix/getv/s 4, v000001e73f0f51b0_0;
%flag_mov 8, 4;
%ix/getv/s 5, v000001e73f0f5ed0_0;
%flag_or 4, 8;
%store/vec4a v000001e73f0f5d90, 4, 5;
%jmp T_6.5;
T_6.4 ;
%pushi/vec4 1, 0, 1;
%ix/getv/s 4, v000001e73f0f51b0_0;
%flag_mov 8, 4;
%ix/getv/s 5, v000001e73f0f5ed0_0;
%flag_or 4, 8;
%store/vec4a v000001e73f0f5d90, 4, 5;
T_6.5 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v000001e73f0f5ed0_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v000001e73f0f5ed0_0, 0, 32;
%jmp T_6.2;
T_6.3 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v000001e73f0f51b0_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v000001e73f0f51b0_0, 0, 32;
%jmp T_6.0;
T_6.1 ;
%jmp T_6;
.thread T_6, $push;
.scope S_000001e73eff4420;
T_7 ;
%pushi/vec4 0, 0, 8;
%store/vec4 v000001e73f05c8a0_0, 0, 8;
%end;
.thread T_7, $init;
.scope S_000001e73eff4420;
T_8 ;
%wait E_000001e73f0530a0;
%load/vec4 v000001e73f05b9a0_0;
%assign/vec4 v000001e73f05c8a0_0, 0;
%jmp T_8;
.thread T_8;
.scope S_000001e73efdd970;
T_9 ;
%pushi/vec4 0, 0, 8;
%store/vec4 v000001e73f006890_0, 0, 8;
%end;
.thread T_9, $init;
.scope S_000001e73efdd970;
T_10 ;
%wait E_000001e73f050920;
%load/vec4 v000001e73f0317f0_0;
%assign/vec4 v000001e73f006890_0, 0;
%jmp T_10;
.thread T_10;
.scope S_000001e73efd1000;
T_11 ;
%pushi/vec4 0, 0, 8;
%store/vec4 v000001e73f07b820_0, 0, 8;
%end;
.thread T_11, $init;
.scope S_000001e73efd1000;
T_12 ;
%wait E_000001e73f04fca0;
%load/vec4 v000001e73f07a920_0;
%assign/vec4 v000001e73f07b820_0, 0;
%jmp T_12;
.thread T_12;
.scope S_000001e73eff4660;
T_13 ;
%pushi/vec4 0, 0, 8;
%store/vec4 v000001e73f05bc20_0, 0, 8;
%end;
.thread T_13, $init;
.scope S_000001e73eff4660;
T_14 ;
%wait E_000001e73f053120;
%load/vec4 v000001e73f05cb20_0;
%assign/vec4 v000001e73f05bc20_0, 0;
%jmp T_14;
.thread T_14;
.scope S_000001e73efdd650;
T_15 ;
%pushi/vec4 0, 0, 8;
%store/vec4 v000001e73f05b220_0, 0, 8;
%end;
.thread T_15, $init;
.scope S_000001e73efdd650;
T_16 ;
%wait E_000001e73f0532e0;
%load/vec4 v000001e73f05bb80_0;
%assign/vec4 v000001e73f05b220_0, 0;
%jmp T_16;
.thread T_16;
.scope S_000001e73efd81c0;
T_17 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e73f07d3d0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e73f07c6b0_0, 0, 1;
%end;
.thread T_17, $init;
.scope S_000001e73efd81c0;
T_18 ;
%wait E_000001e73f0506e0;
%load/vec4 v000001e73f07a560_0;
%cmpi/e 0, 0, 1;
%jmp/0xz T_18.0, 6;
%pushi/vec4 0, 0, 1;
%assign/vec4 v000001e73f07d3d0_0, 0;
T_18.0 ;
%jmp T_18;
.thread T_18;
.scope S_000001e73efd81c0;
T_19 ;