Description of current Verilog files:
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darkriscv.v: the DarkRISCV core
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darksocv.v: a primitive system on-chip w/ the DarkRISCV core wired to ROM and RAM memories and IO
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darkuart.v: a small full-duplex UART w/ programmable baud-rate
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darkpll.v: different PLLs for different FPGAs
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config.vh: configuration file!
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lib: 3rd party modules:
- SDRAM controller: from kianRiscV https://github.com/splinedrive/kianRiscV/blob/master/linux_socs/kianv_harris_mcycle_edition/sdram/mt48lc16m16a2_ctrl.v
TODO:
- add a cache controller
- add a SPI controller
- add a GbE controller