refs.bib

@misc{fritchmancim2021,
  author       = {Dan Fritchman},
  title        = {All-Digital In-Memory Computation for Machine Learning and Neural Network Acceleration},
  url          = {https://github.com/dan-fritchman/NonAnalogComputeInMemoryArticle},
  note         = {Accessed December 2023},
  year         = {2021}
}

@article{laygo,
  author  = {Han, Jaeduk and Bae, Woorham and Chang, Eric and Wang, Zhongkai and Nikolić, Borivoje and Alon, Elad},
  journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
  title   = {LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies},
  year    = {2021},
  volume  = {68},
  number  = {3},
  pages   = {1012-1022},
  doi     = {10.1109/TCSI.2020.3046524}
}

@mastersthesis{werblun2019,
  author   = {Werblun, Nicholas},
  editor   = {Stojanovic, Vladimir},
  title    = {Closing the Analog Design Loop with the Berkeley Analog Generator},
  school   = {EECS Department, University of California, Berkeley},
  year     = {2019},
  url      = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-23.html},
  number   = {UCB/EECS-2019-23},
  abstract = {Analog and mixed signal IC design is notoriously difficult and slow due in large part to the layout. Modern integrated circuit fabrication with such small devices can have significant interconnect parasitics that can drastically affect the behavior of a circuit’s design. The implication is that simulations of circuit’s behavior are unreliable until after the interconnect parasitics are extracted from the layout and included in the simulation. The Berkeley Analog Generator (BAG) is a Python-based tool that interfaces with the Cadence Virtuoso software [3] that aims to solve the above problem. BAG allows the user to write parametrizable generator scripts that will automatically generate the entire layout and schematic, as well as run the layout-versus-schematic (LVS) and post-layout extraction (PEX) tools and export the results in a time that ranges from seconds to minutes based on circuit complexity. Designers who have decided on a certain topology can write a layout and schematic generator script in a high level programming language with class based hierarchy once, and then any changes in the circuit simply require changing the corresponding parameters file containing the circuit specifications. Additionally, BAG allows the automation of simulation and post-processing of simulation data as well as implementation of higher-level design scripts that encapsulate designer insights and methodology, as well as opens the doors for automated optimizer-driven circuit design. This report shows examples of many common circuit blocks and their BAG implementation in an advanced process node, as well as an example of how BAG can be used to speed up the design process. Although the generator scripting offers the implementation in a higher-level language, certain implementation strategies and methodologies work better than others, and this report aims at presenting a systematic generator writing methodology and illustrates it on a set of typical analog-mixed signal blocks found in a high-speed link front-end. In three months, a library of generators ranging from small basic circuits to entire receiver chains were written; then in roughly two weeks, an LVS/PEX verified design for a 25Gbps optical communication link receiver in a 14nm FinFET process was created using BAG cells and test benches. Further possibilities and uses of BAG are also discussed.}
}

@inproceedings{chang2018bag2,
  title        = {BAG2: A process-portable framework for generator-based AMS circuit design},
  author       = {Chang, Eric and Han, Jaeduk and Bae, Woorham and Wang, Zhongkai and Narevsky, Nathan and NikoliC, Borivoje and Alon, Elad},
  booktitle    = {2018 IEEE Custom Integrated Circuits Conference (CICC)},
  pages        = {1--8},
  year         = {2018},
  organization = {IEEE}
}

@inproceedings{kunal2019align,
  title     = {ALIGN: Open-source analog layout automation from the ground up},
  author    = {Kunal, Kishor and Madhusudan, Meghna and Sharma, Arvind K and Xu, Wenbin and Burns, Steven M and Harjani, Ramesh and Hu, Jiang and Kirkpatrick, Desmond A and Sapatnekar, Sachin S},
  booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019},
  pages     = {1--4},
  year      = {2019}
}

@article{chen2020magical,
  title     = {MAGICAL: An open-source fully automated analog IC layout system from netlist to GDSII},
  author    = {Chen, Hao and Liu, Mingjie and Xu, Biying and Zhu, Keren and Tang, Xiyuan and Li, Shaolan and Lin, Yibo and Sun, Nan and Pan, David Z},
  journal   = {IEEE Design \& Test},
  volume    = {38},
  number    = {2},
  pages     = {19--26},
  year      = {2020},
  publisher = {IEEE}
}

@inproceedings{ye2023ted,
  author    = {Ye, Zuochang and Wang, Zhikai and Xin, Jian and Wang, Yuan and Qin, Qian and Chai, Chenkai and Lu, Yukai and Hao, Jinglei and Xiao, Jianhao and Wang, Yan},
  booktitle = {2023 International Symposium of Electronics Design Automation (ISEDA)},
  title     = {TED: A Python-Based Analog Design Environment for Agile Circuit Development},
  year      = {2023},
  volume    = {},
  number    = {},
  pages     = {5-10},
  doi       = {10.1109/ISEDA59274.2023.10218475}
}


@inproceedings{autockt,
  author    = {Settaluri, Keertana and Haj-Ali, Ameer and Huang, Qijing and Hakhamaneshi, Kourosh and Nikolic, Borivoje},
  booktitle = {2020 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
  title     = {AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs},
  year      = {2020},
  volume    = {},
  number    = {},
  pages     = {490-495},
  doi       = {10.23919/DATE48585.2020.9116200}
}

@inproceedings{bagnet,
  author    = {Hakhamaneshi, Kourosh and Werblun, Nick and Abbeel, Pieter and Stojanović, Vladimir},
  booktitle = {2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
  title     = {BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks},
  year      = {2019},
  volume    = {},
  number    = {},
  pages     = {1-8},
  doi       = {10.1109/ICCAD45719.2019.8942062}
}

@inproceedings{gupta98ilp,
  author    = {Gupta, A. and Hayes, J.P.},
  booktitle = {1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)},
  title     = {Optimal 2-D cell layout with integrated transistor folding},
  year      = {1998},
  volume    = {},
  number    = {},
  pages     = {128-135},
  doi       = {10.1145/288548.288590}
}


@inproceedings{schweikardt2022edp,
  author    = {Schweikardt, Matthias and Scheible, Juergen},
  booktitle = {2022 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)},
  title     = {Expert Design Plan: A Toolbox for Procedural Automation of Analog Integrated Circuit Design},
  year      = {2022},
  volume    = {},
  number    = {},
  pages     = {1-4},
  doi       = {10.1109/SMACD55068.2022.9816336}
}

@inproceedings{aida,
  author    = {Martins, Ricardo and Lourenço, Nuno and Canelas, António and Póvoa, Ricardo and Horta, Nuno},
  booktitle = {2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)},
  title     = {AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation},
  year      = {2015},
  volume    = {},
  number    = {},
  pages     = {1-4},
  doi       = {10.1109/SMACD.2015.7301703}
}

@inproceedings{spence89,
  author    = {Spence, R. and Toumazou, C. and Cheung, P. and Makris, C. and Berrah, C. and Singha, M. and Xiao Xiangming and Stone, J.},
  booktitle = {IEE Colloquium on VLSI Analogue Design},
  title     = {Approaches to analogue IC synthesis},
  year      = {1989},
  volume    = {},
  number    = {},
  pages     = {1/1-1/6},
  doi       = {}
}


@article{laygenii,
  author  = {Martins, Ricardo and Lourenço, Nuno and Horta, Nuno},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  title   = {LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits},
  year    = {2013},
  volume  = {32},
  number  = {11},
  pages   = {1641-1654},
  doi     = {10.1109/TCAD.2013.2269050}
}

@inproceedings{unutulmaz2011lds,
  author    = {Unutulmaz, A. and Dündar, G. and Fernández, F.V.},
  booktitle = {2011 20th European Conference on Circuit Theory and Design (ECCTD)},
  title     = {LDS - A description script for layout templates},
  year      = {2011},
  volume    = {},
  number    = {},
  pages     = {857-860},
  doi       = {10.1109/ECCTD.2011.6043824}
}

@article{habal2011,
  author  = {Habal, Husni and Graeb, Helmut},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  title   = {Constraint-Based Layout-Driven Sizing of Analog Circuits},
  year    = {2011},
  volume  = {30},
  number  = {8},
  pages   = {1089-1102},
  doi     = {10.1109/TCAD.2011.2158732}
}

@inproceedings{chisel12,
  author    = {Bachrach, Jonathan and Vo, Huy and Richards, Brian and Lee, Yunsup and Waterman, Andrew and Avižienis, Rimas and Wawrzynek, John and Asanović, Krste},
  booktitle = {DAC Design Automation Conference 2012},
  title     = {Chisel: Constructing hardware in a Scala embedded language},
  year      = {2012},
  volume    = {},
  number    = {},
  pages     = {1212-1221},
  doi       = {10.1145/2228360.2228584}
}

@inproceedings{nvcell,
  author    = {Ren, Haoxing and Fojtik, Matthew},
  booktitle = {2021 58th ACM/IEEE Design Automation Conference (DAC)},
  title     = {Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning},
  year      = {2021},
  volume    = {},
  number    = {},
  pages     = {1291-1294},
  doi       = {10.1109/DAC18074.2021.9586188}
}

@inproceedings{ryzhenko2012,
  author    = {Ryzhenko, Nikolai and Burns, Steven},
  booktitle = {DAC Design Automation Conference 2012},
  title     = {Standard cell routing via Boolean satisfiability},
  year      = {2012},
  volume    = {},
  number    = {},
  pages     = {603-612},
  doi       = {10.1145/2228360.2228470}
}

@article{bonncell,
  author  = {Van Cleeff, Pascal and Hougardy, Stefan and Silvanus, Jannik and Werner, Tobias},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  title   = {BonnCell: Automatic Cell Layout in the 7-nm Era},
  year    = {2020},
  volume  = {39},
  number  = {10},
  pages   = {2872-2885},
  doi     = {10.1109/TCAD.2019.2962782}
}

@inproceedings{matsakis2014,
  author    = {Matsakis, Nicholas D. and Klock, Felix S.},
  title     = {The Rust Language},
  year      = {2014},
  isbn      = {9781450332170},
  publisher = {Association for Computing Machinery},
  address   = {New York, NY, USA},
  url       = {https://doi-org.libproxy.berkeley.edu/10.1145/2663171.2663188},
  doi       = {10.1145/2663171.2663188},
  abstract  = {Rust is a new programming language for developing reliable and efficient systems. It is designed to support concurrency and parallelism in building applications and libraries that take full advantage of modern hardware. Rust's static type system is safe1 and expressive and provides strong guarantees about isolation, concurrency, and memory safety.Rust also offers a clear performance model, making it easier to predict and reason about program efficiency. One important way it accomplishes this is by allowing fine-grained control over memory representations, with direct support for stack allocation and contiguous record storage. The language balances such controls with the absolute requirement for safety: Rust's type system and runtime guarantee the absence of data races, buffer overflows, stack overflows, and accesses to uninitialized or deallocated memory.},
  booktitle = {Proceedings of the 2014 ACM SIGAda Annual Conference on High Integrity Language Technology},
  pages     = {103–104},
  numpages  = {2},
  keywords  = {systems programming, affine type systems, rust, memory management},
  location  = {Portland, Oregon, USA},
  series    = {HILT '14}
}

@inproceedings{lattner2004,
  author    = {Lattner, Chris and Adve, Vikram},
  title     = {LLVM: A Compilation Framework for Lifelong Program Analysis \& Transformation},
  year      = {2004},
  isbn      = {0769521029},
  publisher = {IEEE Computer Society},
  address   = {USA},
  abstract  = {This paper describes LLVM (Low Level Virtual Machine),a compiler framework designed to support transparent, lifelongprogram analysis and transformation for arbitrary programs,by providing high-level information to compilertransformations at compile-time, link-time, run-time, and inidle time between runs.LLVM defines a common, low-levelcode representation in Static Single Assignment (SSA) form,with several novel features: a simple, language-independenttype-system that exposes the primitives commonly used toimplement high-level language features; an instruction fortyped address arithmetic; and a simple mechanism that canbe used to implement the exception handling features ofhigh-level languages (and setjmp/longjmp in C) uniformlyand efficiently.The LLVM compiler framework and coderepresentation together provide a combination of key capabilitiesthat are important for practical, lifelong analysis andtransformation of programs.To our knowledge, no existingcompilation approach provides all these capabilities.We describethe design of the LLVM representation and compilerframework, and evaluate the design in three ways: (a) thesize and effectiveness of the representation, including thetype information it provides; (b) compiler performance forseveral interprocedural problems; and (c) illustrative examplesof the benefits LLVM provides for several challengingcompiler problems.},
  booktitle = {Proceedings of the International Symposium on Code Generation and Optimization: Feedback-Directed and Runtime Optimization},
  pages     = {75},
  location  = {Palo Alto, California},
  series    = {CGO '04}
}

@inproceedings{svg2002,
  author    = {Jackson, Dean},
  title     = {Scalable Vector Graphics (SVG): The World Wide Web Consortium's Recommendation for High Quality Web Graphics},
  year      = {2002},
  isbn      = {1581135254},
  publisher = {Association for Computing Machinery},
  address   = {New York, NY, USA},
  url       = {https://doi-org.libproxy.berkeley.edu/10.1145/1242073.1242327},
  doi       = {10.1145/1242073.1242327},
  abstract  = {Scalable Vector Graphics (SVG) is a language for representing two-dimensional graphics. It was developed by the World Wide Web Consortium (W3C) to be the open standard format for both static and animated vector graphics on Web appliances, from desktop machines to mobile devices. The SVG 1.0 specification, whose authors Include representatives from Adobe, Microsoft, Sun, Kodak, Corel, Macromedia, IBM and Apple, became a W3C Recommendation in September 2001. SVG Is rapidly becoming the open standard of choice for graphics on the Web, and the many SVG implementations already in existence ensure the SVG documents can be viewed on a wide range of platforms.},
  booktitle = {ACM SIGGRAPH 2002 Conference Abstracts and Applications},
  pages     = {319},
  numpages  = {1},
  location  = {San Antonio, Texas},
  series    = {SIGGRAPH '02}
}

@mastersthesis{kumar2023,
  author   = {Kumar, Rahul},
  title    = {A Composable Mixed-Signal Generator Framework with Applications to an SRAM Compiler},
  school   = {EECS Department, University of California, Berkeley},
  year     = {2023},
  url      = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-137.html},
  number   = {UCB/EECS-2023-137},
  abstract = {Generators are a key component in enabling analog/mixed-signal design automation, reuse, and optimization. Existing generator frameworks suffer from being tightly integrated with commercial tools, having performance limitations, and being difficult to customize to circuits that require different styles of layout. In this thesis, we present Substrate, a new framework for writing analog and mixed-signal generators. Substrate offers high performance, strongly-typed APIs, and a wide set of utilities for schematic entry, layout entry, and functional verification. To provide more compact SRAMs that are easy to integrate into digital flows, we also develop SRAM22, an open-source SRAM generator for the Skywater 130nm open-source process. We describe how SRAM22 utilizes Substrate features to generate compact layout, while retaining the flexibility expected from a generator. SRAM22-generated SRAMs have been integrated into RISC-V cores produced using both open-source and commercial digital tools.}
}

@techreport{Varda2008,
  added-at    = {2011-06-03T12:52:14.000+0200},
  author      = {Varda, Kenton},
  biburl      = {https://www.bibsonomy.org/bibtex/2fa05cec6c00ece80a4644756ad82b302/voj},
  institution = {Google},
  interhash   = {3ecd49f2857e154472b259c2ad1a9ff2},
  intrahash   = {fa05cec6c00ece80a4644756ad82b302},
  keywords    = {encoding google number},
  month       = {6},
  timestamp   = {2011-06-03T12:52:15.000+0200},
  title       = {Protocol Buffers: Google's Data Interchange Format},
  url         = {http://google-opensource.blogspot.com/2008/07/protocol-buffers-googles-data.html},
  year        = 2008
}

@inproceedings{izraelevitz2017,
  author    = {A. Izraelevitz and J. Koenig and P. Li and R. Lin and A. Wang and A. Magyar and D. Kim and C. Schmidt and C. Markley and J. Lawson and J. Bachrach},
  booktitle = {2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
  title     = {Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations},
  year      = {2017},
  volume    = {},
  number    = {},
  pages     = {209-216},
  keywords  = {field programmable gate arrays;hardware description languages;program compilers;software reusability;hardware development practices;hardware libraries;open-source hardware intermediate representation;hardware compiler transformations;Hardware construction languages;retargetable compilers;software development;virtual Cambrian explosion;hardware compiler frameworks;parameterized libraries;FIRRTL;FPGA mappings;Chisel;Flexible Intermediate Representation for RTL;Reusability;Hardware;Libraries;Hardware design languages;Field programmable gate arrays;Tools;Open source software;RTL;Design;FPGA;ASIC;Hardware;Modeling;Reusability;Hardware Design Language;Hardware Construction Language;Intermediate Representation;Compiler;Transformations;Chisel;FIRRTL},
  doi       = {10.1109/ICCAD.2017.8203780},
  issn      = {1558-2434}
}

@techreport{li2016,
  author      = {Li, Patrick S. and Izraelevitz, Adam M. and Bachrach, Jonathan},
  title       = {Specification for the FIRRTL Language},
  institution = {EECS Department, University of California, Berkeley},
  year        = {2016},
  url         = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-9.html},
  number      = {UCB/EECS-2016-9}
}

@inproceedings{baaij2010,
  author    = {Baaij, Christiaan and Kooijman, Matthijs and Kuper, Jan and Boeijink, Arjan and Gerards, Marco},
  booktitle = {2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools},
  title     = {CLaSH: Structural Descriptions of Synchronous Hardware Using Haskell},
  year      = {2010},
  volume    = {},
  number    = {},
  pages     = {714-721},
  doi       = {10.1109/DSD.2010.21}
}

@article{jiang2020pymtl3,
  title     = {PyMTL3: A Python framework for open-source hardware modeling, generation, simulation, and verification},
  author    = {Jiang, Shunning and Pan, Peitian and Ou, Yanghui and Batten, Christopher},
  journal   = {IEEE Micro},
  volume    = {40},
  number    = {4},
  pages     = {58--66},
  year      = {2020},
  publisher = {IEEE}
}

@inproceedings{lockhart2014pymtl,
  title        = {PyMTL: A unified framework for vertically integrated computer architecture research},
  author       = {Lockhart, Derek and Zibrat, Gary and Batten, Christopher},
  booktitle    = {2014 47th Annual IEEE/ACM International Symposium on Microarchitecture},
  pages        = {280--292},
  year         = {2014},
  organization = {IEEE}
}

@inproceedings{truong2019golden,
  title        = {A golden age of hardware description languages: Applying programming language techniques to improve design productivity},
  author       = {Truong, Lenny and Hanrahan, Pat},
  booktitle    = {3rd Summit on Advances in Programming Languages (SNAPL 2019)},
  year         = {2019},
  organization = {Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik}
}

@inproceedings{openfasoc,
  author    = {Hammoud, Ali and Shankar, Vijay and Mains, Robert and Ansell, Tim and Matres, Joaquin and Saligane, Mehdi},
  booktitle = {2023 International Symposium on Devices, Circuits and Systems (ISDCS)},
  title     = {OpenFASOC: An Open Platform Towards Analog and Mixed-Signal Automation and Acceleration of Chip Design},
  year      = {2023},
  volume    = {1},
  number    = {},
  pages     = {01-04},
  doi       = {10.1109/ISDCS58735.2023.10153547}
}

@inproceedings{ansell2020missing,
  title     = {The missing pieces of open design enablement: A recent history of Google efforts},
  author    = {Ansell, Tim and Saligane, Mehdi},
  booktitle = {Proceedings of the 39th International Conference on Computer-Aided Design},
  pages     = {1--8},
  year      = {2020}
}

@inproceedings{dikshit2023,
  author       = {Amit Dikshit and Jin Wallner and M. Rakib Uddin and M. Jobayer Hossain and Javery Mann and Amir Begovic and Yukta Timalsina and Lewis G. Carpenter and Gerald Leake and Christopher Baiocco and Colin McDonough and Nicholas Fahrenkopf and Chandra C. Cotter and Christopher Striemer and David Harame},
  title        = {{Design enablement methodology for silicon photonics-based photonic integrated design}},
  volume       = {12424},
  booktitle    = {Integrated Optics: Devices, Materials, and Technologies XXVII},
  editor       = {Sonia M. Garc{\'i}a-Blanco and Pavel Cheben},
  organization = {International Society for Optics and Photonics},
  publisher    = {SPIE},
  pages        = {124240D},
  keywords     = {Silicon Photonics, Design Enablement, Photonic Integrated Circuit Design, Process Design Kits, Photonic Simulations},
  year         = {2023},
  doi          = {10.1117/12.2651445},
  url          = {https://doi.org/10.1117/12.2651445}
}

@article{McCaughan2021PHIDL,
  author  = {McCaughan, Adam N. and Tait, Alexander N. and Buckley, Sonia M. and Oh, Dylan M. and Chiles, Jeffrey T. and Shainline, Jeffrey M. and Nam, Sae Woo},
  title   = {PHIDL: Python-based layout and geometry creation for nanolithography},
  journal = {Journal of Vacuum Science \& Technology B},
  volume  = {39},
  number  = {6},
  pages   = {062601},
  year    = {2021},
  doi     = {10.1116/6.0001203},
  url     = {https://doi.org/10.1116/6.0001203}
}

@inproceedings{rekhi2019,
  author    = {Rekhi, Angad S. and Zimmer, Brian and Nedovic, Nikola and Liu, Ningxi and Venkatesan, Rangharajan and Wang, Miaorong and Khailany, Brucek and Dally, William J. and Gray, C. Thomas},
  booktitle = {2019 56th ACM/IEEE Design Automation Conference (DAC)},
  title     = {Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference},
  year      = {2019},
  volume    = {},
  number    = {},
  pages     = {1-6},
  doi       = {}
}

@inproceedings{xue2021,
  author    = {Xue, Cheng-Xin and Hung, Je-Min and Kao, Hui-Yao and Huang, Yen-Hsiang and Huang, Sheng-Po and Chang, Fu-Chun and Chen, Peng and Liu, Ta-Wei and Jhang, Chuan-Jia and Su, Chin-I and Khwa, Win-San and Lo, Chung-Chuan and Liu, Ren-Shuo and Hsieh, Chih-Cheng and Tang, Kea-Tiong and Chih, Yu-Der and Chang, Tsung-Yung Jonathan and Chang, Meng-Fan},
  booktitle = {2021 IEEE International Solid- State Circuits Conference (ISSCC)},
  title     = {16.1 A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices},
  year      = {2021},
  volume    = {64},
  number    = {},
  pages     = {245-247},
  doi       = {10.1109/ISSCC42613.2021.9365769}
}

@inproceedings{yoon2021,
  author    = {Yoon, Jong-Hyeok and Chang, Muya and Khwa, Win-San and Chih, Yu-Der and Chang, Meng-Fan and Raychowdhury, Arijit},
  booktitle = {2021 IEEE International Solid- State Circuits Conference (ISSCC)},
  title     = {29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification},
  year      = {2021},
  volume    = {64},
  number    = {},
  pages     = {404-406},
  doi       = {10.1109/ISSCC42613.2021.9365926}
}

@inproceedings{chen2021,
  author    = {Chen, Zhengyu and Chen, Xi and Gu, Jie},
  booktitle = {2021 IEEE International Solid- State Circuits Conference (ISSCC)},
  title     = {15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency},
  year      = {2021},
  volume    = {64},
  number    = {},
  pages     = {240-242},
  doi       = {10.1109/ISSCC42613.2021.9366045}
}

@inproceedings{spyrou2019opendb,
  title     = {OpenDB OpenROAD’s database},
  author    = {Spyrou, Tom},
  booktitle = {Proc. Workshop on Open-Source EDA Technology},
  year      = {2019}
}

@inproceedings{guiney2006oa,
  author    = {Guiney, Michaela and Leavitt, Eric},
  title     = {An Introduction to OpenAccess: An Open Source Data Model and API for IC Design},
  year      = {2006},
  isbn      = {0780394518},
  publisher = {IEEE Press},
  url       = {https://doi.org/10.1145/1118299.1118405},
  doi       = {10.1145/1118299.1118405},
  abstract  = {The OpenAccess database provides a comprehensive open standard data model and robust implementation for IC design flows. This paper describes how it improves interoperability among applications in an EDA flow. It details how OA benefits developers of both EDA tools and flows. Finally, it outlines how OA is being used in the industry, at semiconductor design companies, EDA tool vendors, and universities.},
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