Recreate unitests for RISC-V

[jdupak]

Modify the unit tests present in https://github.com/cvut/qtrvsim/tree/master/src/machine/tests to work with RISC-V.

• Implement each tested component in separate file. See https://github.com/cvut/qtrvsim/blob/master/src/machine/execute/alu.test.h and https://github.com/cvut/qtrvsim/blob/master/src/machine/CMakeLists.txt:94.
• Memory and cache should be OK, just move it.

[jdupak]

I have done the moving so now we just need to fix the changed tests. It is prepared in branch rv-tests.

• cache
• memory
• registers
• instruction
• program_loader
• core

[ppisa]

The all original complex core tests has been switched to RISC-V, see a9c1551 and 043fbb1

[ppisa]

Memory tests re-enabled and extended b1f16db