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it87-517.patch
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it87-517.patch
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diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c
index 0e543dbe0a6b..29fa2420e8c4 100644
--- a/drivers/hwmon/it87.c
+++ b/drivers/hwmon/it87.c
@@ -12,10 +12,21 @@
* similar parts. The other devices are supported by different drivers.
*
* Supports: IT8603E Super I/O chip w/LPC interface
+ * IT8606E Super I/O chip w/LPC interface
+ * IT8607E Super I/O chip w/LPC interface
+ * IT8613E Super I/O chip w/LPC interface
* IT8620E Super I/O chip w/LPC interface
* IT8622E Super I/O chip w/LPC interface
* IT8623E Super I/O chip w/LPC interface
+ * IT8625E Super I/O chip w/LPC interface
* IT8628E Super I/O chip w/LPC interface
+ * IT8528E Super I/O chip w/LPC interface
+ * IT8655E Super I/O chip w/LPC interface
+ * IT8665E Super I/O chip w/LPC interface
+ * IT8686E Super I/O chip w/LPC interface
+ * IT8688E Super I/O chip w/LPC interface
+ * IT8689E Super I/O chip w/LPC interface
+ * IT8695E Super I/O chip w/LPC interface
* IT8705F Super I/O chip w/LPC interface
* IT8712F Super I/O chip w/LPC interface
* IT8716F Super I/O chip w/LPC interface
@@ -25,6 +36,8 @@
* IT8726F Super I/O chip w/LPC interface
* IT8728F Super I/O chip w/LPC interface
* IT8732F Super I/O chip w/LPC interface
+ * IT8736F Super I/O chip w/LPC interface
+ * IT8738E Super I/O chip w/LPC interface
* IT8758E Super I/O chip w/LPC interface
* IT8771E Super I/O chip w/LPC interface
* IT8772E Super I/O chip w/LPC interface
@@ -62,6 +75,8 @@
#define DRVNAME "it87"
enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
+ it8736, it8738, it8606, it8607, it8613, it8625,
+ it8528, it8655, it8665, it8686, it8688, it8689, it8695,
it8771, it8772, it8781, it8782, it8783, it8786, it8790,
it8792, it8603, it8620, it8622, it8628 };
@@ -69,6 +84,14 @@ static unsigned short force_id;
module_param(force_id, ushort, 0);
MODULE_PARM_DESC(force_id, "Override the detected device ID");
+static bool ignore_resource_conflict;
+module_param(ignore_resource_conflict, bool, 0000);
+MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
+
+static bool mmio;
+module_param(mmio, bool, 0000);
+MODULE_PARM_DESC(mmio, "Use MMIO if available");
+
static struct platform_device *it87_pdev[2];
#define REG_2E 0x2e /* The register to read/write */
@@ -83,6 +106,14 @@ static struct platform_device *it87_pdev[2];
#define DEVID 0x20 /* Register: Device ID */
#define DEVREV 0x22 /* Register: Device Revision */
+static inline void __superio_enter(int ioreg)
+{
+ outb(0x87, ioreg);
+ outb(0x01, ioreg);
+ outb(0x55, ioreg);
+ outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
+}
+
static inline int superio_inb(int ioreg, int reg)
{
outb(reg, ioreg);
@@ -97,13 +128,7 @@ static inline void superio_outb(int ioreg, int reg, int val)
static int superio_inw(int ioreg, int reg)
{
- int val;
-
- outb(reg++, ioreg);
- val = inb(ioreg + 1) << 8;
- outb(reg, ioreg);
- val |= inb(ioreg + 1);
- return val;
+ return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
}
static inline void superio_select(int ioreg, int ldn)
@@ -120,17 +145,16 @@ static inline int superio_enter(int ioreg)
if (!request_muxed_region(ioreg, 2, DRVNAME))
return -EBUSY;
- outb(0x87, ioreg);
- outb(0x01, ioreg);
- outb(0x55, ioreg);
- outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
+ __superio_enter(ioreg);
return 0;
}
-static inline void superio_exit(int ioreg)
+static inline void superio_exit(int ioreg, bool doexit)
{
- outb(0x02, ioreg);
- outb(0x02, ioreg + 1);
+ if (doexit) {
+ outb(0x02, ioreg);
+ outb(0x02, ioreg + 1);
+ }
release_region(ioreg, 2);
}
@@ -144,6 +168,8 @@ static inline void superio_exit(int ioreg)
#define IT8726F_DEVID 0x8726
#define IT8728F_DEVID 0x8728
#define IT8732F_DEVID 0x8732
+#define IT8736F_DEVID 0x8736
+#define IT8738E_DEVID 0x8738
#define IT8792E_DEVID 0x8733
#define IT8771E_DEVID 0x8771
#define IT8772E_DEVID 0x8772
@@ -153,21 +179,38 @@ static inline void superio_exit(int ioreg)
#define IT8786E_DEVID 0x8786
#define IT8790E_DEVID 0x8790
#define IT8603E_DEVID 0x8603
+#define IT8606E_DEVID 0x8606
+#define IT8607E_DEVID 0x8607
+#define IT8613E_DEVID 0x8613
#define IT8620E_DEVID 0x8620
#define IT8622E_DEVID 0x8622
#define IT8623E_DEVID 0x8623
+#define IT8625E_DEVID 0x8625
#define IT8628E_DEVID 0x8628
-#define IT87_ACT_REG 0x30
-#define IT87_BASE_REG 0x60
+#define IT8528E_DEVID 0x8528
+#define IT8655E_DEVID 0x8655
+#define IT8665E_DEVID 0x8665
+#define IT8686E_DEVID 0x8686
+#define IT8688E_DEVID 0x8688
+#define IT8689E_DEVID 0x8689
+#define IT8695E_DEVID 0x8695
+
+/* Logical device 4 (Environmental Monitor) registers */
+#define IT87_ACT_REG 0x30
+#define IT87_BASE_REG 0x60
+#define IT87_SPECIAL_CFG_REG 0xf3 /* special configuration register */
/* Logical device 7 registers (IT8712F and later) */
+#define IT87_EC_HWM_MIO_REG 0x24 /* MMIO configuration register */
#define IT87_SIO_GPIO1_REG 0x25
#define IT87_SIO_GPIO2_REG 0x26
#define IT87_SIO_GPIO3_REG 0x27
#define IT87_SIO_GPIO4_REG 0x28
#define IT87_SIO_GPIO5_REG 0x29
+#define IT87_SIO_GPIO9_REG 0xd3
#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
+#define IT87_SIO_PINX4_REG 0x2d /* Pin selection */
#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
#define IT87_SIO_VID_REG 0xfc /* VID value */
#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
@@ -201,11 +244,17 @@ static bool fix_pwm_polarity;
#define IT87_REG_ALARM2 0x02
#define IT87_REG_ALARM3 0x03
+#define IT87_REG_BANK 0x06
+
/*
* The IT8718F and IT8720F have the VID value in a different register, in
* Super-I/O configuration space.
*/
#define IT87_REG_VID 0x0a
+
+/* Interface Selection register on other chips */
+#define IT87_REG_IFSEL 0x0a
+
/*
* The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
* for fan divisors. Later IT8712F revisions must use 16-bit tachometer
@@ -225,7 +274,15 @@ static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
-static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
+static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
+
+static const u8 IT87_REG_FAN_8665[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
+static const u8 IT87_REG_FAN_MIN_8665[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
+static const u8 IT87_REG_FANX_8665[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
+static const u8 IT87_REG_FANX_MIN_8665[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
+
+static const u8 IT87_REG_TEMP_OFFSET_8686[] = {
+ 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
#define IT87_REG_FAN_MAIN_CTRL 0x13
#define IT87_REG_FAN_CTL 0x14
@@ -235,12 +292,12 @@ static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
+static const u8 IT87_REG_PWM_8665[] = { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
+
#define IT87_REG_TEMP(nr) (0x29 + (nr))
#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
-#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
-#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
#define IT87_REG_VIN_ENABLE 0x50
#define IT87_REG_TEMP_ENABLE 0x51
@@ -249,6 +306,14 @@ static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
#define IT87_REG_CHIPID 0x58
+static const u8 IT87_REG_TEMP_HIGH[] = { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
+static const u8 IT87_REG_TEMP_LOW[] = { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
+
+static const u8 IT87_REG_TEMP_HIGH_8686[] = {
+ 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
+static const u8 IT87_REG_TEMP_LOW_8686[] = {
+ 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
+
static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
#define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
@@ -256,6 +321,9 @@ static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
#define IT87_REG_TEMP456_ENABLE 0x77
+static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
+#define IT87_REG_TEMP_SRC2 0x23d
+
#define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
#define NUM_VIN_LIMIT 8
#define NUM_TEMP 6
@@ -266,12 +334,18 @@ static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
#define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
#define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
+
struct it87_devices {
const char *name;
- const char * const suffix;
+ const char * const model;
u32 features;
+ u8 num_temp_limit;
+ u8 num_temp_offset;
+ u8 num_temp_map; /* Number of temperature sources for pwm */
u8 peci_mask;
u8 old_peci_mask;
+ u8 smbus_bitmap; /* SMBus enable bits in extra config register */
+ u8 ec_special_config;
};
#define FEAT_12MV_ADC BIT(0)
@@ -293,171 +367,404 @@ struct it87_devices {
#define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */
#define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */
#define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */
+#define FEAT_FOUR_FANS BIT(19) /* Supports four fans */
+#define FEAT_FOUR_PWM BIT(20) /* Supports four fan controls */
+#define FEAT_BANK_SEL BIT(21) /* Chip has multi-bank support */
+#define FEAT_SCALING BIT(22) /* Internal voltage scaling */
+#define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */
+#define FEAT_11MV_ADC BIT(24)
+#define FEAT_NEW_TEMPMAP BIT(25) /* new temp input selection */
+#define FEAT_MMIO BIT(26) /* Chip supports MMIO */
+#define FEAT_FOUR_TEMP BIT(27)
static const struct it87_devices it87_devices[] = {
[it87] = {
.name = "it87",
- .suffix = "F",
- .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
+ .model = "IT87F",
+ .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
+ /* may need to overwrite */
+ .num_temp_limit = 3,
+ .num_temp_offset = 0,
+ .num_temp_map = 3,
},
[it8712] = {
.name = "it8712",
- .suffix = "F",
- .features = FEAT_OLD_AUTOPWM | FEAT_VID,
- /* may need to overwrite */
+ .model = "IT8712F",
+ .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
+ /* may need to overwrite */
+ .num_temp_limit = 3,
+ .num_temp_offset = 0,
+ .num_temp_map = 3,
},
[it8716] = {
.name = "it8716",
- .suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
- | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2,
+ .model = "IT8716F",
+ .features = FEAT_16BIT_FANS | FEAT_VID
+ | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
},
[it8718] = {
.name = "it8718",
- .suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
- | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
- | FEAT_PWM_FREQ2,
+ .model = "IT8718F",
+ .features = FEAT_16BIT_FANS | FEAT_VID
+ | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
+ | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.old_peci_mask = 0x4,
},
[it8720] = {
.name = "it8720",
- .suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
- | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
- | FEAT_PWM_FREQ2,
+ .model = "IT8720F",
+ .features = FEAT_16BIT_FANS | FEAT_VID
+ | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
+ | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.old_peci_mask = 0x4,
},
[it8721] = {
.name = "it8721",
- .suffix = "F",
+ .model = "IT8721F",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
- | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
- | FEAT_PWM_FREQ2,
+ | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
+ | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
+ | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x05,
.old_peci_mask = 0x02, /* Actually reports PCH */
},
[it8728] = {
.name = "it8728",
- .suffix = "F",
+ .model = "IT8728F",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
- | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2,
+ | FEAT_TEMP_PECI | FEAT_FIVE_FANS
+ | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 6,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8732] = {
.name = "it8732",
- .suffix = "F",
+ .model = "IT8732F",
.features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
- | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
+ | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
+ | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
+ | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF | FEAT_SCALING,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
.old_peci_mask = 0x02, /* Actually reports PCH */
},
+ [it8736] = {
+ .name = "it8736",
+ .model = "IT8736F",
+ .features = FEAT_16BIT_FANS
+ | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
+ | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
+ | FEAT_FANCTL_ONOFF | FEAT_SCALING,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
+ .peci_mask = 0x07,
+ .old_peci_mask = 0x02, /* Actually reports PCH */
+ },
+ [it8738] = {
+ .name = "it8738",
+ .model = "IT8738E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
+ | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
+ | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL
+ | FEAT_FANCTL_ONOFF | FEAT_SCALING
+ | FEAT_AVCC3,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
+ .peci_mask = 0x07,
+ .old_peci_mask = 0x02,
+ },
[it8771] = {
.name = "it8771",
- .suffix = "E",
+ .model = "IT8771E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
- | FEAT_PWM_FREQ2,
- /* PECI: guesswork */
- /* 12mV ADC (OHM) */
- /* 16 bit fans (OHM) */
- /* three fans, always 16 bit (guesswork) */
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
+ /* PECI: guesswork */
+ /* 12mV ADC (OHM) */
+ /* 16 bit fans (OHM) */
+ /* three fans, always 16 bit (guesswork) */
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8772] = {
.name = "it8772",
- .suffix = "E",
+ .model = "IT8772E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
- | FEAT_PWM_FREQ2,
- /* PECI (coreboot) */
- /* 12mV ADC (HWSensors4, OHM) */
- /* 16 bit fans (HWSensors4, OHM) */
- /* three fans, always 16 bit (datasheet) */
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
+ /* PECI (coreboot) */
+ /* 12mV ADC (HWSensors4, OHM) */
+ /* 16 bit fans (HWSensors4, OHM) */
+ /* three fans, always 16 bit (datasheet) */
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8781] = {
.name = "it8781",
- .suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
- | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
+ .model = "IT8781F",
+ .features = FEAT_16BIT_FANS
+ | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.old_peci_mask = 0x4,
},
[it8782] = {
.name = "it8782",
- .suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
- | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
+ .model = "IT8782F",
+ .features = FEAT_16BIT_FANS
+ | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.old_peci_mask = 0x4,
},
[it8783] = {
.name = "it8783",
- .suffix = "E/F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
- | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
+ .model = "IT8783E/F",
+ .features = FEAT_16BIT_FANS
+ | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.old_peci_mask = 0x4,
},
[it8786] = {
.name = "it8786",
- .suffix = "E",
+ .model = "IT8786E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
- | FEAT_PWM_FREQ2,
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8790] = {
.name = "it8790",
- .suffix = "E",
- .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
- | FEAT_PWM_FREQ2,
+ .model = "IT8790E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
+ | FEAT_16BIT_FANS | FEAT_TEMP_PECI
+ | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8792] = {
.name = "it8792",
- .suffix = "E",
- .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
- | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
+ .model = "IT8792E/IT8795E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
+ | FEAT_16BIT_FANS | FEAT_TEMP_PECI
+ | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
- .old_peci_mask = 0x02, /* Actually reports PCH */
},
[it8603] = {
.name = "it8603",
- .suffix = "E",
+ .model = "IT8603E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 4,
+ .peci_mask = 0x07,
+ },
+ [it8606] = {
+ .name = "it8606",
+ .model = "IT8606E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
- | FEAT_AVCC3 | FEAT_PWM_FREQ2,
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
+ .peci_mask = 0x07,
+ },
+ [it8607] = {
+ .name = "it8607",
+ .model = "IT8607E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
+ | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 6,
+ .peci_mask = 0x07,
+ },
+ [it8613] = {
+ .name = "it8613",
+ .model = "IT8613E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
+ | FEAT_TEMP_PECI | FEAT_FIVE_FANS
+ | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
+ | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
+ .num_temp_map = 6,
.peci_mask = 0x07,
},
[it8620] = {
.name = "it8620",
- .suffix = "E",
+ .model = "IT8620E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
- | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
- | FEAT_SIX_TEMP | FEAT_VIN3_5V,
+ | FEAT_TEMP_PECI | FEAT_SIX_FANS
+ | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
+ | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8622] = {
.name = "it8622",
- .suffix = "E",
+ .model = "IT8622E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
- | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
- | FEAT_AVCC3 | FEAT_VIN3_5V,
- .peci_mask = 0x07,
+ | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FOUR_TEMP
+ | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
+ | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 4,
+ .peci_mask = 0x0f,
+ .smbus_bitmap = BIT(1) | BIT(2),
+ },
+ [it8625] = {
+ .name = "it8625",
+ .model = "IT8625E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
+ | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
+ | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
+ | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
+ .num_temp_map = 6,
+ .smbus_bitmap = BIT(1) | BIT(2),
},
[it8628] = {
.name = "it8628",
- .suffix = "E",
+ .model = "IT8628E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
- | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
- | FEAT_SIX_TEMP | FEAT_VIN3_5V,
+ | FEAT_TEMP_PECI | FEAT_SIX_FANS
+ | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
+ | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 6,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
+ .peci_mask = 0x07,
+ },
+ [it8528] = {
+ .name = "it8528",
+ .model = "IT8528E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
+ | FEAT_TEMP_PECI | FEAT_SIX_FANS
+ | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
+ | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 6,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
+ .peci_mask = 0x07,
+ },
+ [it8655] = {
+ .name = "it8655",
+ .model = "IT8655E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
+ | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
+ | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL
+ | FEAT_SIX_TEMP | FEAT_MMIO,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
+ .num_temp_map = 6,
+ .smbus_bitmap = BIT(2),
+ },
+ [it8665] = {
+ .name = "it8665",
+ .model = "IT8665E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
+ | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
+ | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
+ | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO | FEAT_SIX_TEMP,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
+ .num_temp_map = 6,
+ .smbus_bitmap = BIT(2),
+ },
+ [it8686] = {
+ .name = "it8686",
+ .model = "IT8686E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
+ .num_temp_map = 7,
+ .smbus_bitmap = BIT(1) | BIT(2),
+ },
+ [it8688] = {
+ .name = "it8688",
+ .model = "IT8688E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
+ | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
+ | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
+ | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
+ .num_temp_map = 7,
+ .smbus_bitmap = BIT(1) | BIT(2),
+ },
+ [it8689] = {
+ .name = "it8689",
+ .model = "IT8689E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
+ | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
+ | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
+ | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
+ .num_temp_map = 7,
+ .smbus_bitmap = BIT(1) | BIT(2),
+ },
+ [it8695] = {
+ .name = "it8695",
+ .model = "IT8695E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
+ | FEAT_16BIT_FANS | FEAT_TEMP_PECI
+ | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
};
@@ -467,7 +774,6 @@ static const struct it87_devices it87_devices[] = {
#define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
-#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
((data)->peci_mask & BIT(nr)))
#define has_temp_old_peci(data, nr) \
@@ -486,22 +792,37 @@ static const struct it87_devices it87_devices[] = {
#define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
#define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
#define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V)
+#define has_four_fans(data) ((data)->features & (FEAT_FOUR_FANS | \
+ FEAT_FIVE_FANS | \
+ FEAT_SIX_FANS))
+#define has_four_pwm(data) ((data)->features & (FEAT_FOUR_PWM | \
+ FEAT_FIVE_PWM \
+ | FEAT_SIX_PWM))
+#define has_bank_sel(data) ((data)->features & FEAT_BANK_SEL)
+#define has_scaling(data) ((data)->features & FEAT_SCALING)
+#define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF)
+#define has_11mv_adc(data) ((data)->features & FEAT_11MV_ADC)
+#define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP)
+#define has_mmio(data) ((data)->features & FEAT_MMIO)
+#define has_four_temp(data) ((data)->features & FEAT_FOUR_TEMP)
struct it87_sio_data {
- int sioaddr;
enum chips type;
+ u8 sioaddr;
+ u8 doexit;
/* Values read from Super-I/O config space */
u8 revision;
u8 vid_value;
u8 beep_pin;
u8 internal; /* Internal sensors can be labeled */
- bool need_in7_reroute;
/* Features skipped based on config or DMI */
u16 skip_in;
u8 skip_vid;
u8 skip_fan;
u8 skip_pwm;
u8 skip_temp;
+ u8 smbus_bitmap;
+ u8 ec_special_config;
};
/*
@@ -510,14 +831,33 @@ struct it87_sio_data {
*/
struct it87_data {
const struct attribute_group *groups[7];
- int sioaddr;
enum chips type;
u32 features;
u8 peci_mask;
u8 old_peci_mask;
+ u8 smbus_bitmap; /* !=0 if SMBus needs to be disabled */
+ u8 saved_bank; /* saved bank register value */
+ u8 ec_special_config; /* EC special config register restore value */
+ u8 sioaddr; /* SIO port address */
+ bool doexit; /* true if exit from sio config is ok */
+
+ void __iomem *mmio; /* Remapped MMIO address if available */
+ int (*read)(struct it87_data *, u16);
+ void (*write)(struct it87_data *, u16, u8);
+
+ const u8 *REG_FAN;
+ const u8 *REG_FANX;
+ const u8 *REG_FAN_MIN;
+ const u8 *REG_FANX_MIN;
+
+ const u8 *REG_PWM;
+
+ const u8 *REG_TEMP_OFFSET;
+ const u8 *REG_TEMP_LOW;
+ const u8 *REG_TEMP_HIGH;
+
unsigned short addr;
- const char *name;
struct mutex update_lock;
bool valid; /* true if following fields are valid */
unsigned long last_updated; /* In jiffies */
@@ -526,11 +866,13 @@ struct it87_data {
u16 in_internal; /* Bitfield, internal sensors (for labels) */
u16 has_in; /* Bitfield, voltage sensors enabled */
u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
- bool need_in7_reroute;
u8 has_fan; /* Bitfield, fans enabled */
u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
u8 has_temp; /* Bitfield, temp sensors enabled */
s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
+ u8 num_temp_limit; /* Number of temperature limit registers */
+ u8 num_temp_offset; /* Number of temperature offset registers */
+ u8 temp_src[4]; /* Up to 4 temperature source registers */
u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
@@ -557,6 +899,9 @@ struct it87_data {
u8 pwm_ctrl[NUM_PWM]; /* Register value */
u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
+ u8 pwm_temp_map_mask; /* 0x03 for old, 0x07 for new temp map */
+ u8 pwm_temp_map_shift; /* 0 for old, 3 for new temp map */
+ u8 pwm_num_temp_map; /* from config data, 3..7 depending on chip */
/* Automatic fan speed control registers */
u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
@@ -571,6 +916,8 @@ static int adc_lsb(const struct it87_data *data, int nr)
lsb = 120;
else if (has_10_9mv_adc(data))
lsb = 109;
+ else if (has_11mv_adc(data))
+ lsb = 110;
else
lsb = 160;
if (data->in_scaled & BIT(nr))
@@ -641,6 +988,25 @@ static int DIV_TO_REG(int val)
#define DIV_FROM_REG(val) BIT(val)
+static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
+{
+ u8 map;
+
+ map = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
+ if (map >= data->pwm_num_temp_map) /* map is 0-based */
+ map = 0;
+
+ return map;
+}
+
+static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
+{
+ u8 ctrl = data->pwm_ctrl[nr];
+
+ return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
+ (map << data->pwm_temp_map_shift);
+}
+
/*
* PWM base frequencies. The frequency has to be divided by either 128 or 256,
* depending on the chip type, to calculate the actual PWM frequency.
@@ -662,50 +1028,139 @@ static const unsigned int pwm_freq[8] = {
750000,
};
+static int _it87_io_read(struct it87_data *data, u16 reg)
+{
+ outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
+ return inb_p(data->addr + IT87_DATA_REG_OFFSET);
+}
+
+static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
+{
+ outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
+ outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
+}
+
+static int smbus_disable(struct it87_data *data)
+{
+ int err;
+
+ if (data->smbus_bitmap) {
+ err = superio_enter(data->sioaddr);
+ if (err)
+ return err;
+ superio_select(data->sioaddr, PME);
+ superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
+ data->ec_special_config & ~data->smbus_bitmap);
+ superio_exit(data->sioaddr, data->doexit);
+ if (has_bank_sel(data) && !data->mmio)
+ data->saved_bank = _it87_io_read(data, IT87_REG_BANK);
+ }
+ return 0;
+}
+
+static int smbus_enable(struct it87_data *data)
+{
+ int err;
+
+ if (data->smbus_bitmap) {
+ if (has_bank_sel(data) && !data->mmio)
+ _it87_io_write(data, IT87_REG_BANK, data->saved_bank);
+ err = superio_enter(data->sioaddr);
+ if (err)
+ return err;
+
+ superio_select(data->sioaddr, PME);
+ superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
+ data->ec_special_config);
+ superio_exit(data->sioaddr, data->doexit);
+ }
+ return 0;
+}
+
+static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
+{
+ u8 _bank = bank;
+
+ if (has_bank_sel(data)) {
+ u8 breg = _it87_io_read(data, IT87_REG_BANK);
+
+ _bank = breg >> 5;
+ if (bank != _bank) {
+ breg &= 0x1f;
+ breg |= (bank << 5);
+ _it87_io_write(data, IT87_REG_BANK, breg);
+ }
+ }
+ return _bank;
+}
+
/*
* Must be called with data->update_lock held, except during initialization.
+ * Must be called with SMBus accesses disabled.
* We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
* would slow down the IT87 access and should not be necessary.
*/
-static int it87_read_value(struct it87_data *data, u8 reg)
+static int it87_io_read(struct it87_data *data, u16 reg)
{
- outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
- return inb_p(data->addr + IT87_DATA_REG_OFFSET);
+ u8 bank;
+ int val;
+
+ bank = it87_io_set_bank(data, reg >> 8);
+ val = _it87_io_read(data, reg & 0xff);
+ it87_io_set_bank(data, bank);
+
+ return val;
}
/*
* Must be called with data->update_lock held, except during initialization.
+ * Must be called with SMBus accesses disabled
* We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
* would slow down the IT87 access and should not be necessary.
*/
-static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
+static void it87_io_write(struct it87_data *data, u16 reg, u8 value)
{
- outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
- outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
+ u8 bank;
+
+ bank = it87_io_set_bank(data, reg >> 8);
+ _it87_io_write(data, reg & 0xff, value);
+ it87_io_set_bank(data, bank);
+}
+
+static int it87_mmio_read(struct it87_data *data, u16 reg)
+{
+ return readb(data->mmio + reg);
+}
+
+static void it87_mmio_write(struct it87_data *data, u16 reg, u8 value)
+{