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Apply DFG regularization to cyclic graphs (verilator#5142)
The Dfg2Ast conversion assumes the 'regularize' pass was run, but we failed to run it on cyclic sub-graphs. Do so now. Fixes verilator#5130.
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src/V3DfgOptimizer.cpp

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@@ -295,7 +295,8 @@ void V3DfgOptimizer::optimize(AstNetlist* netlistp, const string& label) {
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// For each cyclic component
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for (auto& component : cyclicComponents) {
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if (dumpDfgLevel() >= 7) component->dumpDotFilePrefixed(ctx.prefix() + "source");
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// TODO: Apply optimizations safe for cyclic graphs
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// Converting back to Ast assumes the 'regularize' pass was run, so we must run it
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V3DfgPasses::regularize(*component, ctx.m_regularizeContext);
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// Add back under the main DFG (we will convert everything back in one go)
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dfg->addGraph(*component);
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}
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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compile(
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);
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ok(1);
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1;
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module A (
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output [2:0] Y
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);
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endmodule
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module B;
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wire [2:0] w1;
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wire w2;
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A A (
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.Y({ w1[2], w1[0], w2 })
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);
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assign w1[1] = w1[2];
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endmodule

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