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marnovandermaasmarnovandermaas
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[lint] Remove trailing whitespace
Signed-off-by: Marno van der Maas <[email protected]>
1 parent 110f88e commit 940abb9

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‎.metrics.json

+2-2
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
"list": [{
44
"name": "rv32imc",
55
"image": "ibex-toolchain:v2",
6-
"memory" : "1",
6+
"memory" : "1",
77
"cmd": "python3 run.py --test riscv_arithmetic_basic_test --simulator dsim --output out --verbose --co",
88
"wavesCmd": "python3 run.py --test riscv_arithmetic_basic_test --simulator dsim --output out --verbose --co"
99
}]
@@ -36,7 +36,7 @@
3636
"tests": {
3737
"resultsDir": "/mux-flow/build/repo/out",
3838
"builds": ["rv32imc"],
39-
"memory": "1",
39+
"memory": "1",
4040
"listCmd": "<rootDir>/scripts/genMetricsList.py",
4141
"listFile": "<rootDir>/regression_list.json"
4242
}

‎README.md

+1-1
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,7 @@ You can find the prebuilt document under docs/build/singlehtml/index.html
8686
RISC-V DV is now contributed to CHIPS Alliance. We have regular meetings to
8787
discuss the issues, feature priorities, development progress etc. Please join
8888
the [mail group](https://lists.chipsalliance.org/g/riscv-dv-wg) for latest
89-
status.
89+
status.
9090

9191
Please refer to CONTRIBUTING.md for license related questions.
9292

‎cov.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -155,9 +155,9 @@ def collect_cov(out, cfg, cwd):
155155
logging.error("Cannot find {} directory, or it is empty".format(argv.dir))
156156
sys.exit(RET_FAIL)
157157
if argv.core:
158-
"""If functional coverage is being collected from an RTL core
159-
implementation, the flow assumes that the core's trace logs have
160-
already been converted to CSV files by the post_compare step of the
158+
"""If functional coverage is being collected from an RTL core
159+
implementation, the flow assumes that the core's trace logs have
160+
already been converted to CSV files by the post_compare step of the
161161
flow. """
162162
trace_log = ("{}/{}_trace_log".format(out, argv.core))
163163
run_cmd("find {} -name \"*.csv\" | sort > {}".format(argv.dir, trace_log))

‎euvm/riscv/gen/isa/custom/riscv_custom_instr.d

+1-1
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ class riscv_custom_instr: riscv_instr
4141
this(string name = "") {
4242
super(name);
4343
}
44-
44+
4545
override string get_instr_name() {
4646
import std.conv: to;
4747
return instr_name.to!string();

‎euvm/riscv/gen/isa/custom/riscv_custom_instr_enum.d

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
module riscv.gen.isa.custom.riscv_custom_instr_enum;
22

3-
//TODO custom instruction added
3+
//TODO custom instruction added
44
// CUSTOM_i,

‎euvm/riscv/gen/isa/riscv_amo_instr.d

+1-1
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ import uvm;
2929
class riscv_amo_instr: riscv_instr
3030
{
3131
mixin uvm_object_utils;
32-
32+
3333
@rand bool aq;
3434
@rand bool rl;
3535

‎euvm/riscv/gen/isa/riscv_b_instr.d

+3-3
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ import uvm;
3636

3737
class riscv_b_instr: riscv_instr
3838
{
39-
mixin uvm_object_utils;
39+
mixin uvm_object_utils;
4040

4141
@rand riscv_reg_t rs3;
4242
bool has_rs3 = false;
@@ -102,7 +102,7 @@ class riscv_b_instr: riscv_instr
102102
asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN);
103103

104104
switch (instr_format) {
105-
case riscv_instr_format_t.I_FORMAT:
105+
case riscv_instr_format_t.I_FORMAT:
106106
if ([riscv_instr_name_t.FSRI,
107107
riscv_instr_name_t.FSRIW].canFind(instr_name)) { // instr rd,rs1,rs3,imm
108108
asm_str_final = format("%0s%0s, %0s, %0s, %0s", asm_str, rd, rs1,
@@ -414,7 +414,7 @@ class riscv_b_instr: riscv_instr
414414
default:
415415
if (binary == "") binary = super.convert2bin(prefix);
416416
}
417-
417+
418418
return prefix ~ binary;
419419
}
420420

‎euvm/riscv/gen/isa/riscv_compressed_instr.d

+5-5
Original file line numberDiff line numberDiff line change
@@ -165,14 +165,14 @@ class riscv_compressed_instr: riscv_instr
165165
assert (rhs_ !is null);
166166
this.imm_align = rhs_.imm_align;
167167
}
168-
168+
169169
override void extend_imm() {
170170
if (instr_name != riscv_instr_name_t.C_LUI) {
171171
super.extend_imm();
172172
imm = imm << imm_align;
173173
}
174174
}
175-
175+
176176
override void set_rand_mode() {
177177
switch (instr_format) {
178178
case riscv_instr_format_t.CR_FORMAT :
@@ -269,7 +269,7 @@ class riscv_compressed_instr: riscv_instr
269269
break;
270270
default: uvm_info(get_full_name(),
271271
format("Unsupported format %0s", instr_format), UVM_LOW);
272-
break;
272+
break;
273273
}
274274
}
275275
else {
@@ -498,10 +498,10 @@ class riscv_compressed_instr: riscv_instr
498498
riscv_instr_name_t.C_SDSP : return toubvec!2(0b10);
499499
default :
500500
uvm_fatal(get_full_name(), format("Unsupported instruction %0s", instr_name));
501-
assert (false);
501+
assert (false);
502502
}
503503
}
504-
504+
505505
//ubvec!3 get_func3()
506506
override ubvec!3 get_func3() {
507507
switch(instr_name) {

‎euvm/riscv/gen/isa/riscv_floating_point_instr.d

+3-3
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ class riscv_floating_point_instr: riscv_instr
5151
super(name);
5252
}
5353

54-
54+
5555
// Convert the instruction to assembly code
5656
override string convert2asm(string prefix = "") {
5757
import std.conv: to;
@@ -383,7 +383,7 @@ class riscv_floating_point_instr: riscv_instr
383383
// riscv_floating_point_instr pre_fp_instr;
384384
// super.check_hazard_condition(pre_instr);
385385
// pre_fp_instr = cast(riscv_floating_point_instr) pre_instr;
386-
386+
387387
// if (pre_fp_instr != null && pre_fp_instr.has_fd)
388388
// {
389389
// if ((has_fs1 && (fs1 == pre_fp_instr.fd)) || (has_fs2 && (fs2 == pre_fp_instr.fd))
@@ -406,7 +406,7 @@ class riscv_floating_point_instr: riscv_instr
406406
// gpr_hazard = hazard_e.NO_HAZARD;
407407
// }
408408
// }
409-
409+
410410
// }
411411

412412
}

‎euvm/riscv/gen/isa/riscv_instr.d

+16-16
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ import uvm;
3535
class riscv_instr: uvm_object
3636
{
3737
mixin uvm_object_utils;
38-
38+
3939
riscv_instr_gen_config m_cfg;
4040
// riscv_instr_registry m_registry;
4141

@@ -93,7 +93,7 @@ class riscv_instr: uvm_object
9393
}
9494
}
9595
} imm_c;
96-
96+
9797
constraint! q{
9898
if (category == riscv_instr_category_t.CSR) {
9999
if (m_cfg.instr_registry.include_reg.length > 0) {
@@ -120,7 +120,7 @@ class riscv_instr: uvm_object
120120
case riscv_instr_format_t.R_FORMAT:
121121
has_imm = false;
122122
break;
123-
case riscv_instr_format_t.I_FORMAT:
123+
case riscv_instr_format_t.I_FORMAT:
124124
has_rs2 = false;
125125
break;
126126
case riscv_instr_format_t.S_FORMAT, riscv_instr_format_t.B_FORMAT:
@@ -211,13 +211,13 @@ class riscv_instr: uvm_object
211211
asm_str = format("%0s%0s, 0x%0x, %0s", asm_str,rd, csr, get_imm());
212212
else
213213
asm_str = format("%0s%0s, %0s, %0s", asm_str, rd, rs1, get_imm());
214-
break;
214+
break;
215215
case riscv_instr_format_t.S_FORMAT, riscv_instr_format_t.B_FORMAT: // instr rs1,rs2,imm
216216
if (category == riscv_instr_category_t.STORE) // Use psuedo instruction format
217217
asm_str = format("%0s%0s, %0s(%0s)", asm_str, rs2, get_imm(), rs1);
218218
else
219219
asm_str = format("%0s%0s, %0s, %0s", asm_str, rs1, rs2, get_imm());
220-
break;
220+
break;
221221
case riscv_instr_format_t.R_FORMAT: // instr rd,rs1,rs2
222222
if (category == riscv_instr_category_t.CSR) {
223223
asm_str = format("%0s%0s, 0x%0x, %0s", asm_str, rd, csr, rs1);
@@ -228,7 +228,7 @@ class riscv_instr: uvm_object
228228
else {
229229
asm_str = format("%0s%0s, %0s, %0s", asm_str, rd, rs1, rs2);
230230
}
231-
break;
231+
break;
232232
default: uvm_fatal(get_full_name(), format("Unsupported format %0s [%0s]",
233233
instr_format, instr_name));
234234
break;
@@ -479,21 +479,21 @@ class riscv_instr: uvm_object
479479
string convert2bin(string prefix = "") {
480480
import std.conv: to;
481481
ubvec!32 vec;
482-
switch (instr_format) {
483-
case riscv_instr_format_t.J_FORMAT:
482+
switch (instr_format) {
483+
case riscv_instr_format_t.J_FORMAT:
484484
vec = cast(ubvec!1) imm[20]
485485
~ cast(ubvec!10) imm[1..11]
486486
~ cast(ubvec!1) imm[11]
487487
~ cast(ubvec!8) imm[12..20]
488488
~ toubvec!5(rd)
489489
~ get_opcode();
490490
break;
491-
case riscv_instr_format_t.U_FORMAT:
491+
case riscv_instr_format_t.U_FORMAT:
492492
vec = cast(ubvec!20) imm[12..32]
493493
~ toubvec!5(rd)
494494
~ get_opcode();
495495
break;
496-
case riscv_instr_format_t.I_FORMAT:
496+
case riscv_instr_format_t.I_FORMAT:
497497
if (canFind( [riscv_instr_name_t.FENCE, riscv_instr_name_t.FENCE_I], instr_name)) {
498498
vec = toubvec!17(0b00000000000000000)
499499
~ get_func3()
@@ -552,19 +552,19 @@ class riscv_instr: uvm_object
552552
~ toubvec!5(rs1)
553553
~ get_func3()
554554
~ cast(ubvec!5) imm[0..5]
555-
~ get_opcode();
555+
~ get_opcode();
556556
break;
557-
case riscv_instr_format_t.B_FORMAT:
557+
case riscv_instr_format_t.B_FORMAT:
558558
vec = cast(ubvec!1) imm[12]
559559
~ cast(ubvec!6) imm[5..11]
560560
~ toubvec!5(rs2)
561561
~ toubvec!5(rs1)
562-
~ get_func3()
562+
~ get_func3()
563563
~ cast(ubvec!4) imm[1..5]
564564
~ cast(ubvec!1) imm[11]
565565
~ get_opcode();
566566
break;
567-
case riscv_instr_format_t.R_FORMAT:
567+
case riscv_instr_format_t.R_FORMAT:
568568
if (category == riscv_instr_category_t.CSR) {
569569
vec = csr // cast(ubvec!11) csr[0..11] -- SV BUG?
570570
~ toubvec!5(rs1)
@@ -621,7 +621,7 @@ class riscv_instr: uvm_object
621621
riscv_instr rhs_;
622622
super.copy(rhs);
623623
rhs_ = cast(riscv_instr) rhs;
624-
if ( rhs_ !is null ) { //rhs_ = rhs;
624+
if ( rhs_ !is null ) { //rhs_ = rhs;
625625
this.group = rhs_.group;
626626
this.instr_format = rhs_.instr_format;
627627
this.category = rhs_.category;
@@ -646,7 +646,7 @@ class riscv_instr: uvm_object
646646
void update_imm_str() {
647647
imm_str = format("%0d", cast(bvec!32) imm);
648648
}
649-
649+
650650
//`include "isa/riscv_instr_cov.svh"
651651

652652
}

‎euvm/riscv/gen/isa/riscv_instr_register.d

+2-2
Original file line numberDiff line numberDiff line change
@@ -35,11 +35,11 @@ void register(alias MOD, INSTRS...)(riscv_instr_registry registry) {
3535
return;
3636
}
3737
}
38-
38+
3939
void register_module(alias MOD)(riscv_instr_registry registry) {
4040
register!(MOD, __traits(allMembers, MOD))(registry);
4141
}
42-
42+
4343
void register_isa(riscv_instr_registry registry) {
4444
import riscv.gen.isa.rv128c_instr;
4545
import riscv.gen.isa.rv32a_instr;

‎euvm/riscv/gen/isa/riscv_vector_instr.d

+4-4
Original file line numberDiff line numberDiff line change
@@ -253,7 +253,7 @@ class riscv_vector_instr: riscv_floating_point_instr
253253
// the source mask register (v0) when LMUL=1
254254
constraint!q{
255255
(vm == false) && (m_cfg.vector_cfg.vtype.vlmul > 1) -> (vd != 0);
256-
} vmask_overlap_c;
256+
} vmask_overlap_c;
257257

258258
constraint!q{
259259
// Below instruction is always masked
@@ -340,7 +340,7 @@ class riscv_vector_instr: riscv_floating_point_instr
340340
(vm == false) -> (vd != 0);
341341
} temp_c;
342342

343-
343+
344344
this(string name = "riscv_vector_instr") {
345345
super(name);
346346
}
@@ -457,7 +457,7 @@ class riscv_vector_instr: riscv_floating_point_instr
457457
asm_str = format("%0s.%0s ", get_instr_name(), va_variant);
458458
asm_str = format_string(asm_str, MAX_INSTR_STR_LEN);
459459
switch (va_variant) {
460-
case va_variant_t.WV,
460+
case va_variant_t.WV,
461461
va_variant_t.VV,
462462
va_variant_t.VVM,
463463
va_variant_t.VM:
@@ -585,7 +585,7 @@ class riscv_vector_instr: riscv_floating_point_instr
585585
asm_str ~= vec_vm_str();
586586
if (comment != "") {
587587
asm_str ~= " #" ~ comment;
588-
}
588+
}
589589
return asm_str.toLower();
590590
}
591591

‎euvm/riscv/gen/isa/riscv_zbb_instr.d

+3-3
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ class riscv_zbb_instr: riscv_instr
4848
has_rs2 = true;
4949
}
5050
break;
51-
case riscv_instr_format_t.I_FORMAT:
51+
case riscv_instr_format_t.I_FORMAT:
5252
if ([riscv_instr_name_t.CLZ, riscv_instr_name_t.CLZW,
5353
riscv_instr_name_t.CTZ, riscv_instr_name_t.CTZW,
5454
riscv_instr_name_t.CPOP, riscv_instr_name_t.CPOPW,
@@ -192,7 +192,7 @@ class riscv_zbb_instr: riscv_instr
192192
default: uvm_fatal(get_full_name(), format("Unsupported instruction %0s", instr_name));
193193
assert (false);
194194
}
195-
}
195+
}
196196

197197
override ubvec!7 get_func7() {
198198
switch (instr_name) {
@@ -229,7 +229,7 @@ class riscv_zbb_instr: riscv_instr
229229
string binary = "";
230230

231231
switch (instr_format) {
232-
case riscv_instr_format_t.R_FORMAT:
232+
case riscv_instr_format_t.R_FORMAT:
233233
if (instr_name == riscv_instr_name_t.ZEXT_H) {
234234
binary = format("%8h", get_func7() ~ get_func5() ~ rs1 ~ get_func3() ~ rd ~ get_opcode());
235235
}

‎euvm/riscv/gen/isa/riscv_zbc_instr.d

+1-1
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ import std.algorithm: canFind;
3232
class riscv_zbc_instr: riscv_instr
3333
{
3434
mixin uvm_object_utils;
35-
35+
3636
this(string name = "") {
3737
super(name);
3838
}

‎euvm/riscv/gen/isa/riscv_zbs_instr.d

+1-1
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,7 @@ class riscv_zbs_instr: riscv_instr
122122
}
123123
return binary;
124124
}
125-
125+
126126
override bool is_supported(riscv_instr_gen_config cfg) {
127127
return (cfg.enable_zbs_extension &&
128128
(supported_isa.canFind(riscv_instr_group_t.RV32ZBS) ||

‎euvm/riscv/gen/isa/rv32b_instr.d

+1-1
Original file line numberDiff line numberDiff line change
@@ -129,4 +129,4 @@ version (RISCV_INSTR_STRING_MIXIN) {
129129
{ mixin RISCV_INSTR_MIXIN!(BDECOMPRESS, R_FORMAT, ARITHMETIC, RV32B); }
130130
class riscv_BFP_instr: riscv_b_instr
131131
{ mixin RISCV_INSTR_MIXIN!(BFP, R_FORMAT, ARITHMETIC, RV32B); }
132-
}
132+
}

‎euvm/riscv/gen/isa/rv32f_instr.d

+1-1
Original file line numberDiff line numberDiff line change
@@ -102,4 +102,4 @@ version (RISCV_INSTR_STRING_MIXIN) {
102102
{ mixin RISCV_INSTR_MIXIN!(FCVT_S_WU, I_FORMAT, ARITHMETIC, RV32F); }
103103
class riscv_FMV_W_X_instr: riscv_floating_point_instr
104104
{ mixin RISCV_INSTR_MIXIN!(FMV_W_X, I_FORMAT, ARITHMETIC, RV32F); }
105-
}
105+
}

‎euvm/riscv/gen/isa/rv32m_instr.d

+1-1
Original file line numberDiff line numberDiff line change
@@ -51,4 +51,4 @@ version (RISCV_INSTR_STRING_MIXIN) {
5151
class riscv_REMU_instr: riscv_instr
5252
{ mixin RISCV_INSTR_MIXIN!(REMU, R_FORMAT, ARITHMETIC, RV32M); }
5353
}
54-
54+

‎euvm/riscv/gen/isa/rv64c_instr.d

+1-1
Original file line numberDiff line numberDiff line change
@@ -45,4 +45,4 @@ version (RISCV_INSTR_STRING_MIXIN) {
4545
{ mixin RISCV_INSTR_MIXIN!(C_LDSP, CI_FORMAT, LOAD, RV64C, UIMM); }
4646
class riscv_C_SDSP_instr: riscv_compressed_instr
4747
{ mixin RISCV_INSTR_MIXIN!(C_SDSP, CSS_FORMAT, STORE, RV64C, UIMM); }
48-
}
48+
}

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