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[6/N] Fix Wextra-semi warning (pytorch#139605)
Fixes #ISSUE_NUMBER Pull Request resolved: pytorch#139605 Approved by: https://github.com/ezyang
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‎aten/src/ATen/core/dispatch/OperatorEntry.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -510,7 +510,7 @@ void OperatorEntry::reportSignatureError(const CppSignature& call_signature, con
510510
"This likely happened in a call to OperatorHandle::typed<Return (Args...)>(). ",
511511
"Please make sure that the function signature matches the signature in the operator registration call."
512512
);
513-
};
513+
}
514514

515515
#ifndef STRIP_ERROR_MESSAGES
516516
static std::string post_process_dispatch_key_str(std::string dispatch_key) {

‎aten/src/ATen/cpu/vec/vec256/vec256_bfloat16.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ template <typename T, typename std::enable_if_t<is_reduced_floating_point_v<T>,
132132
inline void cvt_to_fp32(const __m128i& a, __m256& o);
133133
template <> inline void cvt_to_fp32<BFloat16>(const __m128i& a, __m256& o) {
134134
cvtbf16_fp32(a, o);
135-
};
135+
}
136136
template <> inline void cvt_to_fp32<Half>(const __m128i& a, __m256& o) {
137137
cvtfp16_fp32(a, o);
138138
}
@@ -1071,8 +1071,8 @@ inline std::tuple<Vectorized<float>, Vectorized<float>> convert_##name##_float(c
10711071
inline Vectorized<type> convert_float_##name(const Vectorized<float>& a, const Vectorized<float>& b) { \
10721072
return cvt_from_fp32<type>(__m256(a), __m256(b)); \
10731073
}
1074-
CONVERT_VECTORIZED_INIT(BFloat16, bfloat16);
1075-
CONVERT_VECTORIZED_INIT(Half, half);
1074+
CONVERT_VECTORIZED_INIT(BFloat16, bfloat16)
1075+
CONVERT_VECTORIZED_INIT(Half, half)
10761076

10771077
#else // defined(CPU_CAPABILITY_AVX2)
10781078

@@ -1096,9 +1096,9 @@ inline Vectorized<type> convert_float_##name(const Vectorized<float>& a, const V
10961096
convert(arr, arr2, K); \
10971097
return Vectorized<type>::loadu(arr2); \
10981098
}
1099-
CONVERT_NON_VECTORIZED_INIT(BFloat16, bfloat16);
1099+
CONVERT_NON_VECTORIZED_INIT(BFloat16, bfloat16)
11001100
#if !(defined(__aarch64__) && !defined(C10_MOBILE) && !defined(__CUDACC__) && !defined(CPU_CAPABILITY_SVE256))
1101-
CONVERT_NON_VECTORIZED_INIT(Half, half);
1101+
CONVERT_NON_VECTORIZED_INIT(Half, half)
11021102
#endif
11031103

11041104
#endif // defined(CPU_CAPABILITY_AVX2)

‎aten/src/ATen/functorch/Interpreter.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -120,11 +120,11 @@ void sanityCheckStack(const c10::OperatorHandle& op, torch::jit::Stack* stack) {
120120
}
121121

122122
void Interpreter::process(const c10::OperatorHandle& op, torch::jit::Stack* stack) {
123-
INTERPRETER_DISPATCH(key_, SINGLE_ARG(processImpl(op, stack)));
123+
INTERPRETER_DISPATCH(key_, SINGLE_ARG(processImpl(op, stack)))
124124
}
125125

126126
void Interpreter::sendToNextInterpreter(const c10::OperatorHandle& op, torch::jit::Stack* stack, bool grad_special_case) {
127-
INTERPRETER_DISPATCH(key_, SINGLE_ARG(sendToNextInterpreterImpl(op, stack, grad_special_case)));
127+
INTERPRETER_DISPATCH(key_, SINGLE_ARG(sendToNextInterpreterImpl(op, stack, grad_special_case)))
128128
}
129129

130130
} // namespace at::functorch

‎aten/src/ATen/mps/MPSAllocator.mm

+1-1
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010

1111
namespace at::mps {
1212

13-
C10_DEFINE_REGISTRY(MPSAllocatorCallbacksRegistry, IMpsAllocatorCallback);
13+
C10_DEFINE_REGISTRY(MPSAllocatorCallbacksRegistry, IMpsAllocatorCallback)
1414

1515
namespace HeapAllocator {
1616

‎aten/src/ATen/native/BlasKernel.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -330,7 +330,7 @@ void gemv_fast_path<at::Half>(
330330
y,
331331
*incy);
332332
}
333-
INSTANTIATE(c10::BFloat16);
333+
INSTANTIATE(c10::BFloat16)
334334
#else
335335
template <>
336336
bool scal_use_fast_path<at::Half>(

‎aten/src/ATen/native/EmbeddingBag.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1251,7 +1251,7 @@ embedding_bag(const Tensor &weight, const Tensor &indices,
12511251
mode, sparse, per_sample_weights, include_last_offset, padding_idx);
12521252
}
12531253
return out;
1254-
};
1254+
}
12551255

12561256
std::tuple<Tensor, Tensor, Tensor, Tensor>
12571257
embedding_bag(const Tensor &weight, const Tensor &indices,

‎aten/src/ATen/native/MaxUnpooling.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ Tensor& max_unpooling2d_forward_out_cpu(
6464
}
6565

6666
return output;
67-
};
67+
}
6868

6969
Tensor max_unpooling2d_forward_cpu(
7070
const Tensor& self,

‎aten/src/ATen/native/NaiveConvolutionTranspose2d.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -871,7 +871,7 @@ static std::tuple<Tensor, Tensor, Tensor> slow_conv_transpose2d_backward_cpu(
871871
return std::tuple<Tensor, Tensor, Tensor>(grad_input, grad_weight, grad_bias);
872872
}
873873

874-
REGISTER_ALL_CPU_DISPATCH(slow_conv_transpose2d_backward_stub, &slow_conv_transpose2d_backward_cpu);
874+
REGISTER_ALL_CPU_DISPATCH(slow_conv_transpose2d_backward_stub, &slow_conv_transpose2d_backward_cpu)
875875

876876
} // namespace native
877877
} // namespace at

‎aten/src/ATen/native/NaiveDilatedConvolution.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -741,7 +741,7 @@ static std::tuple<Tensor, Tensor, Tensor> slow_conv_dilated3d_backward_cpu(
741741
return std::tie(grad_input, grad_weight, grad_bias);
742742
}
743743

744-
REGISTER_ALL_CPU_DISPATCH(slow_conv_dilated2d_backward_stub, &slow_conv_dilated2d_backward_cpu);
745-
REGISTER_ALL_CPU_DISPATCH(slow_conv_dilated3d_backward_stub, &slow_conv_dilated3d_backward_cpu);
744+
REGISTER_ALL_CPU_DISPATCH(slow_conv_dilated2d_backward_stub, &slow_conv_dilated2d_backward_cpu)
745+
REGISTER_ALL_CPU_DISPATCH(slow_conv_dilated3d_backward_stub, &slow_conv_dilated3d_backward_cpu)
746746

747747
} // namespace at::native

‎aten/src/ATen/native/Pool.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ using max_pool2d_fn = void(*)(const Tensor& output, const Tensor& indices, const
1414
int kW, int kH, int dW, int dH, int padW, int padH, int dilationW, int dilationH);
1515
using max_pool2d_backward_fn = void(*)(const Tensor& grad_input, const Tensor& grad_output, const Tensor& indices);
1616

17-
DECLARE_DISPATCH(max_pool2d_fn, max_pool2d_kernel);
17+
DECLARE_DISPATCH(max_pool2d_fn, max_pool2d_kernel)
1818
DECLARE_DISPATCH(max_pool2d_backward_fn, max_pool2d_backward_kernel)
1919

2020
// averge pooling has same signature for forward and backward

‎aten/src/ATen/native/RNN.cpp

+17-17
Original file line numberDiff line numberDiff line change
@@ -1187,10 +1187,10 @@ std::tuple<Tensor, Tensor, Tensor, Tensor, Tensor> _thnn_fused_lstm_cell_backwar
11871187
DEFINE_DISPATCH(NAME##_miopen_stub); \
11881188
DEFINE_DISPATCH(NAME##_packed_cudnn_stub); \
11891189
DEFINE_DISPATCH(NAME##_packed_miopen_stub); \
1190-
REGISTER_NO_CPU_DISPATCH(NAME##_cudnn_stub); \
1191-
REGISTER_NO_CPU_DISPATCH(NAME##_miopen_stub); \
1192-
REGISTER_NO_CPU_DISPATCH(NAME##_packed_cudnn_stub); \
1193-
REGISTER_NO_CPU_DISPATCH(NAME##_packed_miopen_stub); \
1190+
REGISTER_NO_CPU_DISPATCH(NAME##_cudnn_stub) \
1191+
REGISTER_NO_CPU_DISPATCH(NAME##_miopen_stub) \
1192+
REGISTER_NO_CPU_DISPATCH(NAME##_packed_cudnn_stub) \
1193+
REGISTER_NO_CPU_DISPATCH(NAME##_packed_miopen_stub) \
11941194
\
11951195
std::tuple<Tensor, Tensor> NAME( \
11961196
const Tensor& _input, \
@@ -1415,17 +1415,17 @@ static std::tuple<Tensor, Tensor> quantized_gru_data_legacy(
14151415
using tanf_cell_type = SimpleCell<tanh_f, CellParams>;
14161416
ONE_HIDDEN_RNN(rnn_tanh, tanf_cell_type)
14171417
using relu_cell_type = SimpleCell<relu_f, CellParams>;
1418-
ONE_HIDDEN_RNN(rnn_relu, relu_cell_type);
1418+
ONE_HIDDEN_RNN(rnn_relu, relu_cell_type)
14191419

14201420
DEFINE_DISPATCH(lstm_cudnn_stub);
14211421
DEFINE_DISPATCH(lstm_packed_cudnn_stub);
14221422
DEFINE_DISPATCH(lstm_miopen_stub);
14231423
DEFINE_DISPATCH(lstm_packed_miopen_stub);
14241424
DEFINE_DISPATCH(lstm_mkldnn_stub);
1425-
REGISTER_NO_CPU_DISPATCH(lstm_cudnn_stub);
1426-
REGISTER_NO_CPU_DISPATCH(lstm_packed_cudnn_stub);
1427-
REGISTER_NO_CPU_DISPATCH(lstm_miopen_stub);
1428-
REGISTER_NO_CPU_DISPATCH(lstm_packed_miopen_stub);
1425+
REGISTER_NO_CPU_DISPATCH(lstm_cudnn_stub)
1426+
REGISTER_NO_CPU_DISPATCH(lstm_packed_cudnn_stub)
1427+
REGISTER_NO_CPU_DISPATCH(lstm_miopen_stub)
1428+
REGISTER_NO_CPU_DISPATCH(lstm_packed_miopen_stub)
14291429

14301430
std::tuple<Tensor, Tensor, Tensor> lstm(
14311431
const Tensor& _input, TensorList hx,
@@ -1857,9 +1857,9 @@ static std::tuple<Tensor, Tensor> prepare_quantized_lstm_hx(TensorList hx) {
18571857
// Quantized LSTM cell
18581858
using quantized_lstm_cell_dynamic_type = LSTMCell<QuantizedCellParamsDynamic>;
18591859

1860-
DEFINE_QUANTIZED_RNN_CELL(quantized_lstm_cell, TensorList, quantized_lstm_cell_type, quantized_lstm_return_type, prepare_quantized_lstm_hx);
1860+
DEFINE_QUANTIZED_RNN_CELL(quantized_lstm_cell, TensorList, quantized_lstm_cell_type, quantized_lstm_return_type, prepare_quantized_lstm_hx)
18611861

1862-
static DEFINE_QUANTIZED_RNN_CELL_DYNAMIC(quantized_lstm_cell_dynamic, TensorList, quantized_lstm_cell_dynamic_type, quantized_lstm_return_type, prepare_quantized_lstm_hx);
1862+
static DEFINE_QUANTIZED_RNN_CELL_DYNAMIC(quantized_lstm_cell_dynamic, TensorList, quantized_lstm_cell_dynamic_type, quantized_lstm_return_type, prepare_quantized_lstm_hx)
18631863

18641864
// Helpers for simpler cells
18651865
using simple_hx_type = const Tensor&;
@@ -1871,21 +1871,21 @@ static simple_hx_type prepare_quantized_hx(simple_hx_type hx) {
18711871
using quantized_gru_cell_type = GRUCell<QuantizedCellParams>;
18721872
using quantized_gru_cell_dynamic_type = GRUCell<QuantizedCellParamsDynamic>;
18731873

1874-
DEFINE_QUANTIZED_RNN_CELL(quantized_gru_cell, simple_hx_type, quantized_gru_cell_type, Tensor, prepare_quantized_hx);
1874+
DEFINE_QUANTIZED_RNN_CELL(quantized_gru_cell, simple_hx_type, quantized_gru_cell_type, Tensor, prepare_quantized_hx)
18751875

1876-
static DEFINE_QUANTIZED_RNN_CELL_DYNAMIC(quantized_gru_cell_dynamic, simple_hx_type, quantized_gru_cell_dynamic_type, Tensor, prepare_quantized_hx);
1876+
static DEFINE_QUANTIZED_RNN_CELL_DYNAMIC(quantized_gru_cell_dynamic, simple_hx_type, quantized_gru_cell_dynamic_type, Tensor, prepare_quantized_hx)
18771877

18781878
// Quantized RNN w/ ReLU cell
18791879
using quantized_rnn_relu_cell_type = SimpleCell<relu_f, QuantizedCellParams>;
1880-
DEFINE_QUANTIZED_RNN_CELL(quantized_rnn_relu_cell, simple_hx_type, quantized_rnn_relu_cell_type, Tensor, prepare_quantized_hx);
1880+
DEFINE_QUANTIZED_RNN_CELL(quantized_rnn_relu_cell, simple_hx_type, quantized_rnn_relu_cell_type, Tensor, prepare_quantized_hx)
18811881
using quantized_rnn_relu_cell_dynamic_type = SimpleCell<relu_f, QuantizedCellParamsDynamic>;
1882-
static DEFINE_QUANTIZED_RNN_CELL_DYNAMIC(quantized_rnn_relu_cell_dynamic, simple_hx_type, quantized_rnn_relu_cell_dynamic_type, Tensor, prepare_quantized_hx);
1882+
static DEFINE_QUANTIZED_RNN_CELL_DYNAMIC(quantized_rnn_relu_cell_dynamic, simple_hx_type, quantized_rnn_relu_cell_dynamic_type, Tensor, prepare_quantized_hx)
18831883

18841884
// Quantized RNN w/ tanh cell
18851885
using quantized_rnn_tanh_cell_type = SimpleCell<tanh_f, QuantizedCellParams>;
1886-
DEFINE_QUANTIZED_RNN_CELL(quantized_rnn_tanh_cell, simple_hx_type, quantized_rnn_tanh_cell_type, Tensor, prepare_quantized_hx);
1886+
DEFINE_QUANTIZED_RNN_CELL(quantized_rnn_tanh_cell, simple_hx_type, quantized_rnn_tanh_cell_type, Tensor, prepare_quantized_hx)
18871887
using quantized_rnn_tanh_cell_dynamic_type = SimpleCell<tanh_f, QuantizedCellParamsDynamic>;
1888-
static DEFINE_QUANTIZED_RNN_CELL_DYNAMIC(quantized_rnn_tanh_cell_dynamic, simple_hx_type, quantized_rnn_tanh_cell_dynamic_type, Tensor, prepare_quantized_hx);
1888+
static DEFINE_QUANTIZED_RNN_CELL_DYNAMIC(quantized_rnn_tanh_cell_dynamic, simple_hx_type, quantized_rnn_tanh_cell_dynamic_type, Tensor, prepare_quantized_hx)
18891889

18901890
namespace {
18911891

‎aten/src/ATen/native/UnaryOps.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -932,11 +932,11 @@ Tensor& mvlgamma_out(const Tensor& self, int64_t p, Tensor& result) {
932932

933933
Tensor special_multigammaln(const Tensor& self, int64_t p) {
934934
return self.mvlgamma(p);
935-
};
935+
}
936936

937937
Tensor& special_multigammaln_out(const Tensor& self, int64_t p, Tensor& result) {
938938
return at::mvlgamma_out(result, self, p);
939-
};
939+
}
940940

941941
std::tuple<Tensor, Tensor> frexp(const Tensor& self) {
942942
Tensor mantissa = at::empty_like(self);

‎aten/src/ATen/native/cpu/BinaryOpsKernel.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -1415,16 +1415,16 @@ REGISTER_DISPATCH(laguerre_polynomial_l_stub, &laguerre_polynomial_l_kernel)
14151415
REGISTER_DISPATCH(legendre_polynomial_p_stub, &legendre_polynomial_p_kernel)
14161416
REGISTER_DISPATCH(
14171417
shifted_chebyshev_polynomial_t_stub,
1418-
&shifted_chebyshev_polynomial_t_kernel);
1418+
&shifted_chebyshev_polynomial_t_kernel)
14191419
REGISTER_DISPATCH(
14201420
shifted_chebyshev_polynomial_u_stub,
1421-
&shifted_chebyshev_polynomial_u_kernel);
1421+
&shifted_chebyshev_polynomial_u_kernel)
14221422
REGISTER_DISPATCH(
14231423
shifted_chebyshev_polynomial_v_stub,
1424-
&shifted_chebyshev_polynomial_v_kernel);
1424+
&shifted_chebyshev_polynomial_v_kernel)
14251425
REGISTER_DISPATCH(
14261426
shifted_chebyshev_polynomial_w_stub,
1427-
&shifted_chebyshev_polynomial_w_kernel);
1427+
&shifted_chebyshev_polynomial_w_kernel)
14281428
// Might enable AVX512 dispatch after enabling explicit vectorization for them.
14291429
REGISTER_DISPATCH(chebyshev_polynomial_u_stub, &chebyshev_polynomial_u_kernel)
14301430
REGISTER_DISPATCH(hermite_polynomial_h_stub, &hermite_polynomial_h_kernel)

‎aten/src/ATen/native/cpu/MultinomialKernel.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -241,5 +241,5 @@ static void multinomial_with_replacement_kernel_impl(
241241

242242
REGISTER_DISPATCH(
243243
multinomial_with_replacement_stub,
244-
&multinomial_with_replacement_kernel_impl);
244+
&multinomial_with_replacement_kernel_impl)
245245
} // namespace at::native

‎aten/src/ATen/native/cpu/ReducedPrecisionFloatGemvFastPathKernel.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ inline namespace CPU_CAPABILITY {
2222
constexpr auto kF32RegisterPairsPerIteration = 4;
2323
constexpr auto kF32RegistersPerIteration = kF32RegisterPairsPerIteration * 2;
2424
constexpr auto kF32ElementsPerRegister = vec::Vectorized<float>::size();
25-
constexpr auto kF32ElementsPerIteration = kF32RegistersPerIteration * kF32ElementsPerRegister;;
25+
constexpr auto kF32ElementsPerIteration = kF32RegistersPerIteration * kF32ElementsPerRegister;
2626

2727
namespace {
2828
template <typename T>
@@ -328,8 +328,8 @@ void fp16_gemv_trans(
328328
#if !defined(C10_MOBILE)
329329
// NOTE: we don't *need* to go through dispatch for the ARM-only
330330
// implementation right now, but we will need it when we cover x86.
331-
REGISTER_DISPATCH(fp16_dot_with_fp32_arith_stub, &fp16_dot_with_fp32_arith);
332-
REGISTER_DISPATCH(fp16_gemv_trans_stub, &fp16_gemv_trans);
331+
REGISTER_DISPATCH(fp16_dot_with_fp32_arith_stub, &fp16_dot_with_fp32_arith)
332+
REGISTER_DISPATCH(fp16_gemv_trans_stub, &fp16_gemv_trans)
333333
#else
334334
#endif // defined(__aarch64__) && !defined(C10_MOBILE)
335335

‎aten/src/ATen/native/cpu/ReducedPrecisionFloatGemvFastPathKernel.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ namespace at::native {
88
#if !defined(C10_MOBILE)
99
using fp16_dot_fn = float(*)(const Half*, const Half*, int64_t);
1010
using fp16_gemv_fn = void(*)(int, int, float, const Half*, int, const Half*, int, float, Half*, int);
11-
DECLARE_DISPATCH(fp16_dot_fn, fp16_dot_with_fp32_arith_stub);
12-
DECLARE_DISPATCH(fp16_gemv_fn, fp16_gemv_trans_stub);
11+
DECLARE_DISPATCH(fp16_dot_fn, fp16_dot_with_fp32_arith_stub)
12+
DECLARE_DISPATCH(fp16_gemv_fn, fp16_gemv_trans_stub)
1313
#endif // !defined(C10_MOBILE)
1414
} // namespace at::native

‎aten/src/ATen/native/cpu/SoftMaxKernel.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -1295,15 +1295,15 @@ ALSO_REGISTER_AVX512_DISPATCH(softmax_lastdim_kernel, &softmax_lastdim_kernel_im
12951295
ALSO_REGISTER_AVX512_DISPATCH(log_softmax_lastdim_kernel, &log_softmax_lastdim_kernel_impl)
12961296
ALSO_REGISTER_AVX512_DISPATCH(
12971297
softmax_backward_lastdim_kernel,
1298-
&softmax_backward_lastdim_kernel_impl);
1298+
&softmax_backward_lastdim_kernel_impl)
12991299
ALSO_REGISTER_AVX512_DISPATCH(
13001300
log_softmax_backward_lastdim_kernel,
1301-
&log_softmax_backward_lastdim_kernel_impl);
1301+
&log_softmax_backward_lastdim_kernel_impl)
13021302

13031303
ALSO_REGISTER_AVX512_DISPATCH(softmax_kernel, &softmax_kernel_impl)
13041304
ALSO_REGISTER_AVX512_DISPATCH(log_softmax_kernel, &log_softmax_kernel_impl)
13051305
ALSO_REGISTER_AVX512_DISPATCH(softmax_backward_kernel, &softmax_backward_kernel_impl)
13061306
ALSO_REGISTER_AVX512_DISPATCH(
13071307
log_softmax_backward_kernel,
1308-
&log_softmax_backward_kernel_impl);
1308+
&log_softmax_backward_kernel_impl)
13091309
} // namespace at::native

‎aten/src/ATen/native/cpu/UnaryOpsKernel.cpp

+23-23
Original file line numberDiff line numberDiff line change
@@ -830,15 +830,15 @@ REGISTER_DISPATCH(special_i0e_stub, &CPU_CAPABILITY::i0e_kernel)
830830
REGISTER_DISPATCH(special_ndtri_stub, &CPU_CAPABILITY::ndtri_kernel)
831831
REGISTER_DISPATCH(special_modified_bessel_k0_stub, &CPU_CAPABILITY::modified_bessel_k0_kernel)
832832
REGISTER_DISPATCH(special_modified_bessel_k1_stub, &CPU_CAPABILITY::modified_bessel_k1_kernel)
833-
IMPLEMENT_FLOAT_KERNEL_WITHOUT_AVX512(ceil);
834-
IMPLEMENT_FLOAT_KERNEL_WITHOUT_AVX512(floor);
835-
IMPLEMENT_FLOAT_KERNEL_WITHOUT_AVX512(round);
836-
IMPLEMENT_COMPLEX_KERNEL_WITHOUT_AVX512(sqrt);
837-
IMPLEMENT_FLOAT_KERNEL_WITHOUT_AVX512(trunc);
838-
IMPLEMENT_FLOAT_KERNEL_WITHOUT_AVX512(i0);
839-
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITHOUT_AVX512(sin);
840-
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITHOUT_AVX512(cos);
841-
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITHOUT_AVX512(tan);
833+
IMPLEMENT_FLOAT_KERNEL_WITHOUT_AVX512(ceil)
834+
IMPLEMENT_FLOAT_KERNEL_WITHOUT_AVX512(floor)
835+
IMPLEMENT_FLOAT_KERNEL_WITHOUT_AVX512(round)
836+
IMPLEMENT_COMPLEX_KERNEL_WITHOUT_AVX512(sqrt)
837+
IMPLEMENT_FLOAT_KERNEL_WITHOUT_AVX512(trunc)
838+
IMPLEMENT_FLOAT_KERNEL_WITHOUT_AVX512(i0)
839+
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITHOUT_AVX512(sin)
840+
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITHOUT_AVX512(cos)
841+
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITHOUT_AVX512(tan)
842842

843843
// The following kernels are compute-intensive & are compiled with both AVX512
844844
// & AVX2
@@ -871,19 +871,19 @@ REGISTER_DISPATCH(special_bessel_y1_stub, &CPU_CAPABILITY::bessel_y1_kernel)
871871
REGISTER_DISPATCH(special_modified_bessel_i0_stub, &CPU_CAPABILITY::modified_bessel_i0_kernel)
872872
REGISTER_DISPATCH(special_modified_bessel_i1_stub, &CPU_CAPABILITY::modified_bessel_i1_kernel)
873873

874-
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(acos);
875-
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(asin);
876-
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(atan);
877-
IMPLEMENT_FLOAT_KERNEL_WITH_AVX512(erf);
878-
IMPLEMENT_FLOAT_KERNEL_WITH_AVX512(erfc);
879-
IMPLEMENT_FLOAT_KERNEL_WITH_AVX512(erfinv);
880-
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(exp);
881-
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(expm1);
882-
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(log);
883-
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(log10);
884-
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(log1p);
885-
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(log2);
886-
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(tanh);
887-
IMPLEMENT_FLOAT_KERNEL_WITH_AVX512(lgamma);
874+
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(acos)
875+
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(asin)
876+
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(atan)
877+
IMPLEMENT_FLOAT_KERNEL_WITH_AVX512(erf)
878+
IMPLEMENT_FLOAT_KERNEL_WITH_AVX512(erfc)
879+
IMPLEMENT_FLOAT_KERNEL_WITH_AVX512(erfinv)
880+
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(exp)
881+
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(expm1)
882+
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(log)
883+
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(log10)
884+
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(log1p)
885+
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(log2)
886+
STATIC_IMPLEMENT_COMPLEX_KERNEL_WITH_AVX512(tanh)
887+
IMPLEMENT_FLOAT_KERNEL_WITH_AVX512(lgamma)
888888

889889
} // namespace at::native

‎aten/src/ATen/native/cuda/DepthwiseConv2d.cu

+1-1
Original file line numberDiff line numberDiff line change
@@ -760,6 +760,6 @@ std::tuple<Tensor, Tensor> conv_depthwise2d_backward_cuda(
760760
grad_weight);
761761
}
762762

763-
REGISTER_CUDA_DISPATCH(conv_depthwise2d_backward_stub, &conv_depthwise2d_backward_cuda);
763+
REGISTER_CUDA_DISPATCH(conv_depthwise2d_backward_stub, &conv_depthwise2d_backward_cuda)
764764

765765
} // namespace at::native

‎aten/src/ATen/native/cuda/DepthwiseConv3d.cu

+1-1
Original file line numberDiff line numberDiff line change
@@ -695,7 +695,7 @@ std::tuple<Tensor, Tensor, Tensor> conv_depthwise3d_backward_cuda(
695695

696696
}
697697

698-
REGISTER_CUDA_DISPATCH(conv_depthwise3d_backward_stub, &conv_depthwise3d_backward_cuda);
698+
REGISTER_CUDA_DISPATCH(conv_depthwise3d_backward_stub, &conv_depthwise3d_backward_cuda)
699699

700700
#undef DWCONV3D_BACKWARD_INPUT_DISPATCH_SPECIALIZATION
701701
#undef DWCONV3D_BACKWARD_INPUT_DISPATCH_OTHERS

‎aten/src/ATen/native/cuda/FlattenIndicesKernel.cu

+1-1
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,6 @@ Tensor flatten_indices_cuda_kernel(const Tensor& indices, IntArrayRef size) {
2323

2424
}
2525

26-
REGISTER_CUDA_DISPATCH(flatten_indices_stub, &flatten_indices_cuda_kernel);
26+
REGISTER_CUDA_DISPATCH(flatten_indices_stub, &flatten_indices_cuda_kernel)
2727

2828
} // namespace at::native

‎aten/src/ATen/native/cuda/IndexKernel.cu

+1-1
Original file line numberDiff line numberDiff line change
@@ -483,6 +483,6 @@ REGISTER_DISPATCH(put_stub, &put_kernel)
483483
REGISTER_DISPATCH(take_stub, &take_kernel)
484484
REGISTER_DISPATCH(flip_stub, &flip_kernel)
485485

486-
REGISTER_CUDA_DISPATCH(index_put_kernel_quantized_stub, &index_put_kernel_quantized_cuda);
486+
REGISTER_CUDA_DISPATCH(index_put_kernel_quantized_stub, &index_put_kernel_quantized_cuda)
487487

488488
} // namespace at::native

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