Record updates result in huge multiplexers

[gergoerdi]

This is in contination of #657: hunting down ways in which CLaSH is inefficient in resource utilization.

Using this version of Space Invaders, the Xilinx ISE reports, among others, the following resource usage:

 212-bit 42-to-1 multiplexer                           : 2
 212-bit 8-to-1 multiplexer                            : 1

These use up a huge amount of LUTs. 212 bits sounds about right for the size of CPUState and CPUOut and there are 8 possible internal phases and roughly 40 different internal opcodes, so we have an "extrinsic explanation" for the numbers.

However, this is wildly inefficient. If product types like CPUState and CPUOut would be compiled into multiple registers (one per field), then any one branch would only update a tiny fraction of them, instead of the current all-or-nothing approach.