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It gives different results in simulation:
Error: outputVerifier, expected: 000000000000000100010000, actual: 000000000001000000100000 Time: 10 ns Iteration: 1 Process: /testBench/r_assert/line__194 File: /tmp/clash-test-e6fd091d2363ea54/BlobVec.testBench/testBench.vhdl Error: outputVerifier, expected: 000000000000000100010000, actual: 000000000001000000100000 Time: 20 ns Iteration: 1 Process: /testBench/r_assert/line__194 File: /tmp/clash-test-e6fd091d2363ea54/BlobVec.testBench/testBench.vhdl
The text was updated successfully, but these errors were encountered:
I am so curious to figure this out! What the...!
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It gives different results in simulation:
The text was updated successfully, but these errors were encountered: