From ed1496d4abc2e914080346f99fed03f24dfb1167 Mon Sep 17 00:00:00 2001 From: Craig Ramsay Date: Fri, 6 Jul 2018 10:51:58 +0100 Subject: [PATCH] Fixed a few typos ("the the") --- src/Clash/Sized/RTree.hs | 2 +- src/Clash/Sized/Vector.hs | 2 +- src/Clash/Tutorial.hs | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/Clash/Sized/RTree.hs b/src/Clash/Sized/RTree.hs index b5249abe1c..175e375ea8 100644 --- a/src/Clash/Sized/RTree.hs +++ b/src/Clash/Sized/RTree.hs @@ -280,7 +280,7 @@ instance (KnownNat d, Undefined a) => Undefined (RTree d a) where -- -- In order to accommodate the type of our 'Clash.Class.Num.plus', where the -- result is larger than the arguments, we must use a dependently typed fold in --- the the form of 'dtfold': +-- the form of 'dtfold': -- -- @ -- {\-\# LANGUAGE UndecidableInstances \#-\} diff --git a/src/Clash/Sized/Vector.hs b/src/Clash/Sized/Vector.hs index a9b7991010..cd55a374a8 100644 --- a/src/Clash/Sized/Vector.hs +++ b/src/Clash/Sized/Vector.hs @@ -1795,7 +1795,7 @@ dfold _ f z xs = go (snatProxy (asNatProxy xs)) xs -- -- In order to accommodate the type of our 'Clash.Class.Num.plus', where the -- result is larger than the arguments, we must use a dependently typed fold in --- the the form of 'dtfold': +-- the form of 'dtfold': -- -- @ -- {\-\# LANGUAGE UndecidableInstances \#-\} diff --git a/src/Clash/Tutorial.hs b/src/Clash/Tutorial.hs index 0f398d3716..48d943b4de 100644 --- a/src/Clash/Tutorial.hs +++ b/src/Clash/Tutorial.hs @@ -607,7 +607,7 @@ We can see that for the first 4 samples, everything is working as expected, after which warnings are being reported. The reason is that 'stimuliGenerator' will keep on producing the last sample, (4,4), while the 'outputVerifier' will keep on expecting the last sample, 14. In the VHDL testbench these errors won't -show, as the the global clock will be stopped after 4 ticks. +show, as the global clock will be stopped after 4 ticks. You should now again run @:vhdl@ in the interpreter; this time the compiler will take a bit longer to generate all the circuits. Inside the @.\/vhdl\/MAC@ @@ -1452,7 +1452,7 @@ What is /not/ possible is: cnt = 'Clash.Explicit.Signal.register' clk rst 0 (cnt + 1) @ - As it is not possible to convert the the individual bits to a 'Clock'. + As it is not possible to convert the individual bits to a 'Clock'. However! What is possible is to do the following: