From a0cbc40f3f52b34c728b952a098f6784ba8f223f Mon Sep 17 00:00:00 2001 From: Lucas Bollen Date: Thu, 5 Jan 2023 13:54:22 +0100 Subject: [PATCH] Add `scatterUnitWb` and `gatherUnitWb` instances (#220) --- .github/workflows/ci.yml | 6 +- bittide-instances/bin/Shake.hs | 5 + bittide-instances/bittide-instances.cabal | 1 + .../src/Bittide/Instances/ScatterGather.hs | 104 ++++++++++++++++++ 4 files changed, 115 insertions(+), 1 deletion(-) create mode 100644 bittide-instances/src/Bittide/Instances/ScatterGather.hs diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index ec4fe7f7fc..200c1a1f57 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -651,9 +651,13 @@ jobs: strategy: matrix: target: + - {top: callisto3, stage: netlist} + - {top: gatherUnit1K, stage: hdl} + - {top: gatherUnit1KReducedPins, stage: netlist} + - {top: scatterUnit1K, stage: hdl} + - {top: scatterUnit1KReducedPins, stage: netlist} - {top: switchCalendar1k, stage: hdl} - {top: switchCalendar1kReducedPins, stage: netlist} - - {top: callisto3, stage: netlist} container: image: ghcr.io/clash-lang/clash-ci-9.0.2:2022-02-02 diff --git a/bittide-instances/bin/Shake.hs b/bittide-instances/bin/Shake.hs index 4e67ce9ba4..c4ab021590 100644 --- a/bittide-instances/bin/Shake.hs +++ b/bittide-instances/bin/Shake.hs @@ -25,6 +25,7 @@ import qualified Bittide.Instances.Calendar as Calendar import qualified Bittide.Instances.ClockControl as ClockControl import qualified Bittide.Instances.ElasticBuffer as ElasticBuffer import qualified Bittide.Instances.MVPs as MVPs +import qualified Bittide.Instances.ScatterGather as ScatterGather import qualified Bittide.Instances.Si539xSpi as Si539xSpi import qualified Bittide.Instances.StabilityChecker as StabilityChecker import qualified Bittide.Instances.Synchronizer as Synchronizer @@ -73,6 +74,10 @@ targets = , 'ClockControl.callisto3 , 'ElasticBuffer.elasticBuffer5 , 'MVPs.clockControlDemo0 + , 'ScatterGather.gatherUnit1K + , 'ScatterGather.gatherUnit1KReducedPins + , 'ScatterGather.scatterUnit1K + , 'ScatterGather.scatterUnit1KReducedPins , 'Si539xSpi.si5391Spi , 'StabilityChecker.stabilityChecker_3_1M , 'Synchronizer.safeDffSynchronizer diff --git a/bittide-instances/bittide-instances.cabal b/bittide-instances/bittide-instances.cabal index 4144466be9..3e7dee5a70 100644 --- a/bittide-instances/bittide-instances.cabal +++ b/bittide-instances/bittide-instances.cabal @@ -97,6 +97,7 @@ library Bittide.Instances.ElasticBuffer Bittide.Instances.Hacks Bittide.Instances.MVPs + Bittide.Instances.ScatterGather Bittide.Instances.Si539xSpi Bittide.Instances.StabilityChecker Bittide.Instances.Synchronizer diff --git a/bittide-instances/src/Bittide/Instances/ScatterGather.hs b/bittide-instances/src/Bittide/Instances/ScatterGather.hs new file mode 100644 index 0000000000..5b5bc10b9e --- /dev/null +++ b/bittide-instances/src/Bittide/Instances/ScatterGather.hs @@ -0,0 +1,104 @@ +-- SPDX-FileCopyrightText: 2022 Google LLC +-- +-- SPDX-License-Identifier: Apache-2.0 +{-# OPTIONS_GHC -fconstraint-solver-iterations=7 #-} + +module Bittide.Instances.ScatterGather where + +import Clash.Prelude + +import Bittide.Calendar +import Bittide.Instances.Domains +import Bittide.Instances.Hacks +import Bittide.ScatterGather +import Bittide.SharedTypes +import Protocols.Wishbone + +type FrameWidth = 64 +type NLinks = 16 +type WishboneAddrWidth = 32 +type WishboneWidth = 4 + +scatterCal1K :: ScatterConfig WishboneWidth WishboneAddrWidth +scatterCal1K = ScatterConfig cal + where + cal :: CalendarConfig WishboneWidth WishboneAddrWidth (Index 1024) + cal = CalendarConfig (SNat @1024) + (ValidEntry{veEntry=0, veRepeat = 0 :: Unsigned 8} :> Nil) + (ValidEntry{veEntry=0, veRepeat = 0 :: Unsigned 8} :> Nil) + +gatherCal1K :: GatherConfig WishboneWidth WishboneAddrWidth +gatherCal1K = GatherConfig cal + where + cal :: CalendarConfig WishboneWidth WishboneAddrWidth (Index 1024) + cal = CalendarConfig (SNat @1024) + (ValidEntry{veEntry=0, veRepeat = 0 :: Unsigned 8} :> Nil) + (ValidEntry{veEntry=0, veRepeat = 0 :: Unsigned 8} :> Nil) + +{-# ANN scatterUnit1K + (Synthesize + { t_name = "scatterUnit1K" + , t_inputs = + [ PortName "clk" + , PortName "rst" + , PortName "wbInCal" + , PortName "linkIn" + , PortName "wbInSu" + ] + , t_output = PortProduct "" + [ PortName "wbOutSu" + , PortName "wbOutCal" + ] + } + )#-} +scatterUnit1K :: + Clock Basic200 -> + Reset Basic200 -> + Signal Basic200 (WishboneM2S WishboneAddrWidth WishboneWidth (Bytes WishboneWidth)) -> + Signal Basic200 (DataLink 64) -> + Signal Basic200 (WishboneM2S WishboneAddrWidth WishboneWidth (Bytes WishboneWidth)) -> + ( Signal Basic200 (WishboneS2M (Bytes WishboneWidth)) + , Signal Basic200 (WishboneS2M (Bytes WishboneWidth))) +scatterUnit1K clk rst = withClockResetEnable clk rst enableGen $ scatterUnitWb scatterCal1K +{-# NOINLINE scatterUnit1K #-} + +scatterUnit1KReducedPins :: + Clock Basic200 -> Reset Basic200 -> Signal Basic200 Bit -> Signal Basic200 Bit +scatterUnit1KReducedPins clk rst = + withClockResetEnable clk rst enableGen $ reducePins scatterUnit1K' + where + scatterUnit1K' (unbundle -> (a,b,c)) = bundle $ scatterUnit1K clk rst a b c + +{-# ANN gatherUnit1K + (Synthesize + { t_name = "gatherUnit1K" + , t_inputs = + [ PortName "clk" + , PortName "rst" + , PortName "wbInCal" + , PortName "wbInGu" + ] + , t_output = PortProduct "" + [ PortName "linkOut" + , PortName "wbOutGu" + , PortName "wbOutCal" + ] + } + )#-} +gatherUnit1K :: + Clock Basic200 -> + Reset Basic200 -> + Signal Basic200 (WishboneM2S WishboneAddrWidth WishboneWidth (Bytes WishboneWidth)) -> + Signal Basic200 (WishboneM2S WishboneAddrWidth WishboneWidth (Bytes WishboneWidth)) -> + ( Signal Basic200 (DataLink 64) + , Signal Basic200 (WishboneS2M (Bytes WishboneWidth)) + , Signal Basic200 (WishboneS2M (Bytes WishboneWidth))) +gatherUnit1K clk rst = withClockResetEnable clk rst enableGen $ gatherUnitWb gatherCal1K +{-# NOINLINE gatherUnit1K #-} + +gatherUnit1KReducedPins :: + Clock Basic200 -> Reset Basic200 -> Signal Basic200 Bit -> Signal Basic200 Bit +gatherUnit1KReducedPins clk rst = + withClockResetEnable clk rst enableGen $ reducePins gatherUnit1K' + where + gatherUnit1K' (unbundle -> (a,b)) = bundle $ gatherUnit1K clk rst a b