diff --git a/build.sh b/build.sh index 4c39e7a..4515ecf 100755 --- a/build.sh +++ b/build.sh @@ -7,7 +7,7 @@ source_dir=$PWD/source build_dir=$PWD/build patches_dir=$PWD/patches -kernel_version="6.4.8" +kernel_version="6.6.16" tarball_url="https://cdn.kernel.org/pub/linux/kernel/v${kernel_version:0:1}.x/linux-${kernel_version}.tar.xz" tarball_name="$(echo $tarball_url | cut -f 8 -d '/')" @@ -57,7 +57,9 @@ function build_kernel { curl -L $tarball_url -o ${source_dir}/${variant}/${tarball_name} tar xf ${source_dir}/${variant}/${tarball_name} -C ${source_dir}/${variant}/ cd $kernel_source_dir - patch -p1 < ${patches_dir}/${variant}/* &> /dev/null || true + for f in ${patches_dir}/${variant}/*; do + patch -p1 < $f &> /dev/null || true; + done case $arch in arm64) cross="aarch64-linux-gnu-";; diff --git a/patches/stoney/audio.patch b/patches/stoney/audio.patch new file mode 100644 index 0000000..e0159fc --- /dev/null +++ b/patches/stoney/audio.patch @@ -0,0 +1,110 @@ +From 505e384212e123959ece829ca9b20bf6822a0f56 Mon Sep 17 00:00:00 2001 +From: Lux Aliaga +Date: Wed, 4 Oct 2023 01:11:07 -0300 +Subject: [PATCH] Revert "ASoC: dwc: add DMA handshake control" + +This reverts commit a42e988b6265dcd489feb1adab8551b40c988f43. +--- + sound/soc/dwc/dwc-i2s.c | 50 +++-------------------------------------- + sound/soc/dwc/local.h | 6 ----- + 2 files changed, 3 insertions(+), 53 deletions(-) + +diff --git a/sound/soc/dwc/dwc-i2s.c b/sound/soc/dwc/dwc-i2s.c +index 9ea4be56d3b7..46e4d9e8fafa 100644 +--- a/sound/soc/dwc/dwc-i2s.c ++++ b/sound/soc/dwc/dwc-i2s.c +@@ -151,60 +151,19 @@ static irqreturn_t i2s_irq_handler(int irq, void *dev_id) + return IRQ_NONE; + } + +-static void i2s_enable_dma(struct dw_i2s_dev *dev, u32 stream) +-{ +- u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR); +- +- /* Enable DMA handshake for stream */ +- if (stream == SNDRV_PCM_STREAM_PLAYBACK) +- dma_reg |= I2S_DMAEN_TXBLOCK; +- else +- dma_reg |= I2S_DMAEN_RXBLOCK; +- +- i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); +-} +- +-static void i2s_disable_dma(struct dw_i2s_dev *dev, u32 stream) +-{ +- u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR); +- +- /* Disable DMA handshake for stream */ +- if (stream == SNDRV_PCM_STREAM_PLAYBACK) { +- dma_reg &= ~I2S_DMAEN_TXBLOCK; +- i2s_write_reg(dev->i2s_base, I2S_RTXDMA, 1); +- } else { +- dma_reg &= ~I2S_DMAEN_RXBLOCK; +- i2s_write_reg(dev->i2s_base, I2S_RRXDMA, 1); +- } +- i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); +-} +- + static void i2s_start(struct dw_i2s_dev *dev, + struct snd_pcm_substream *substream) + { + struct i2s_clk_config_data *config = &dev->config; + +- u32 reg = IER_IEN; +- +- if (dev->tdm_slots) { +- reg |= (dev->tdm_slots - 1) << IER_TDM_SLOTS_SHIFT; +- reg |= IER_INTF_TYPE; +- reg |= dev->frame_offset << IER_FRAME_OFF_SHIFT; +- } +- +- i2s_write_reg(dev->i2s_base, IER, reg); ++ i2s_write_reg(dev->i2s_base, IER, 1); ++ i2s_enable_irqs(dev, substream->stream, config->chan_nr); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + i2s_write_reg(dev->i2s_base, ITER, 1); + else + i2s_write_reg(dev->i2s_base, IRER, 1); + +- /* I2S needs to enable IRQ to make a handshake with DMAC on the JH7110 SoC */ +- if (dev->use_pio || dev->is_jh7110) +- i2s_enable_irqs(dev, substream->stream, config->chan_nr); +- else +- i2s_enable_dma(dev, substream->stream); +- + i2s_write_reg(dev->i2s_base, CER, 1); + } + +@@ -218,10 +177,7 @@ static void i2s_stop(struct dw_i2s_dev *dev, + else + i2s_write_reg(dev->i2s_base, IRER, 0); + +- if (dev->use_pio || dev->is_jh7110) +- i2s_disable_irqs(dev, substream->stream, 8); +- else +- i2s_disable_dma(dev, substream->stream); ++ i2s_disable_irqs(dev, substream->stream, 8); + + if (!dev->active) { + i2s_write_reg(dev->i2s_base, CER, 0); +diff --git a/sound/soc/dwc/local.h b/sound/soc/dwc/local.h +index dce88c9ad5f3..81eee700c1c2 100644 +--- a/sound/soc/dwc/local.h ++++ b/sound/soc/dwc/local.h +@@ -69,12 +69,6 @@ + #define I2S_COMP_VERSION 0x01F8 + #define I2S_COMP_TYPE 0x01FC + +-#define I2S_RRXDMA 0x01C4 +-#define I2S_RTXDMA 0x01CC +-#define I2S_DMACR 0x0200 +-#define I2S_DMAEN_RXBLOCK (1 << 16) +-#define I2S_DMAEN_TXBLOCK (1 << 17) +- + /* + * Component parameter register fields - define the I2S block's + * configuration. +-- +2.40.0 + diff --git a/patches/stoney/emmc.patch b/patches/stoney/emmc.patch deleted file mode 100644 index 1abdf65..0000000 --- a/patches/stoney/emmc.patch +++ /dev/null @@ -1,114 +0,0 @@ -diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c -index 620f52ad9667..28847aa1eaef 100644 ---- a/drivers/mmc/host/sdhci-pci-o2micro.c -+++ b/drivers/mmc/host/sdhci-pci-o2micro.c -@@ -12,7 +12,6 @@ - #include - #include - #include --#include - - #include "sdhci.h" - #include "sdhci-pci.h" -@@ -45,16 +44,12 @@ - #define O2_SD_CAP_REG0 0x334 - #define O2_SD_UHS1_CAP_SETTING 0x33C - #define O2_SD_DELAY_CTRL 0x350 --#define O2_SD_OUTPUT_CLK_SOURCE_SWITCH 0x354 - #define O2_SD_UHS2_L1_CTRL 0x35C - #define O2_SD_FUNC_REG3 0x3E0 - #define O2_SD_FUNC_REG4 0x3E4 - #define O2_SD_LED_ENABLE BIT(6) - #define O2_SD_FREG0_LEDOFF BIT(13) --#define O2_SD_SEL_DLL BIT(16) - #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22) --#define O2_SD_PHASE_MASK GENMASK(23, 20) --#define O2_SD_FIX_PHASE FIELD_PREP(O2_SD_PHASE_MASK, 0x9) - - #define O2_SD_VENDOR_SETTING 0x110 - #define O2_SD_VENDOR_SETTING2 0x1C8 -@@ -309,13 +304,9 @@ static int sdhci_o2_dll_recovery(struct sdhci_host *host) - static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) - { - struct sdhci_host *host = mmc_priv(mmc); -- struct sdhci_pci_slot *slot = sdhci_priv(host); -- struct sdhci_pci_chip *chip = slot->chip; - int current_bus_width = 0; - u32 scratch32 = 0; - u16 scratch = 0; -- u8 scratch_8 = 0; -- u32 reg_val; - - /* - * This handler implements the hardware tuning that is specific to -@@ -334,34 +325,6 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) - scratch |= O2_SD_PWR_FORCE_L0; - sdhci_writew(host, scratch, O2_SD_MISC_CTRL); - -- /* Stop clk */ -- reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); -- reg_val &= ~SDHCI_CLOCK_CARD_EN; -- sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); -- -- if ((host->timing == MMC_TIMING_MMC_HS200) || -- (host->timing == MMC_TIMING_UHS_SDR104)) { -- /* UnLock WP */ -- pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); -- scratch_8 &= 0x7f; -- pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); -- -- /* Set pcr 0x354[16] to choose dll clock, and set the default phase */ -- pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val); -- reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); -- reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE); -- pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val); -- -- /* Lock WP */ -- pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); -- scratch_8 |= 0x80; -- pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); -- } -- /* Start clk */ -- reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); -- reg_val |= SDHCI_CLOCK_CARD_EN; -- sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); -- - /* wait DLL lock, timeout value 5ms */ - if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, - scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000)) -@@ -561,7 +524,6 @@ static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) - static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) - { - u16 clk; -- u8 scratch; - u32 scratch_32; - struct sdhci_pci_slot *slot = sdhci_priv(host); - struct sdhci_pci_chip *chip = slot->chip; -@@ -573,11 +535,6 @@ static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) - if (clock == 0) - return; - -- /* UnLock WP */ -- pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); -- scratch &= 0x7f; -- pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); -- - if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) { - pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); - -@@ -590,15 +547,6 @@ static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) - o2_pci_set_baseclk(chip, 0x25100000); - } - -- pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32); -- scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); -- pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32); -- -- /* Lock WP */ -- pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); -- scratch |= 0x80; -- pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); -- - clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); - sdhci_o2_enable_clk(host, clk); - }