diff --git a/verilog/formatting/formatter_test.cc b/verilog/formatting/formatter_test.cc
index 83b636fa6c..2806c06aa9 100644
--- a/verilog/formatting/formatter_test.cc
+++ b/verilog/formatting/formatter_test.cc
@@ -15452,11 +15452,16 @@ TEST(FormatterEndToEndTest, AlwaysWrapModuleInstantiation) {
       {"module foo; bar #(.N(N)) bq (.bus(bus));endmodule\n",
        // instance parameter and port fits on line
        "module foo;\n"
-       "  bar #(\n      .N(N)\n  ) bq (\n      .bus(bus)\n  );\n"
+       "  bar #(\n"
+       "      .N(N)\n"
+       "  ) bq (\n"
+       "      .bus(bus)\n"
+       "  );\n"
        "endmodule\n"},
       {"module foo; bar bq (.bus(bus));endmodule\n",
        "module foo;\n"
-       "  bar bq (\n      .bus(bus)\n  );\n"
+       "  bar bq (\n"
+       "      .bus(bus)\n  );\n"
        "endmodule\n"},
   };
   FormatStyle style;