From eaeefffe7abf912fe7925ec15fdf54beba63f575 Mon Sep 17 00:00:00 2001 From: Achim Vandierendonck Date: Fri, 9 Aug 2024 14:37:24 +0200 Subject: [PATCH 1/2] Add interconnect unit test, PR #2188 --- verilog/parser/verilog_parser_unittest.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/verilog/parser/verilog_parser_unittest.cc b/verilog/parser/verilog_parser_unittest.cc index a97d4ccd1..ec42e2253 100644 --- a/verilog/parser/verilog_parser_unittest.cc +++ b/verilog/parser/verilog_parser_unittest.cc @@ -3502,6 +3502,7 @@ static constexpr ParserTestCaseArray kModuleInstanceTests = { "module tryme;\n" "logic lol;\n" // is a data_declaration "wire money;\n" // is a net_declaration + "interconnect floyd;\n" // is a TK_interconnect "endmodule", "module tryme;\n" "foo a;\n" // looks like data_declaration From 629774e726d7a99779a0ee1cc223bf12fc296090 Mon Sep 17 00:00:00 2001 From: Achim Vandierendonck Date: Fri, 9 Aug 2024 14:42:00 +0200 Subject: [PATCH 2/2] Correct style in accordance to guidelines --- verilog/parser/verilog_parser_unittest.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/verilog/parser/verilog_parser_unittest.cc b/verilog/parser/verilog_parser_unittest.cc index ec42e2253..551e05b82 100644 --- a/verilog/parser/verilog_parser_unittest.cc +++ b/verilog/parser/verilog_parser_unittest.cc @@ -3500,8 +3500,8 @@ static constexpr ParserTestCaseArray kModuleTests = { static constexpr ParserTestCaseArray kModuleInstanceTests = { "module tryme;\n" - "logic lol;\n" // is a data_declaration - "wire money;\n" // is a net_declaration + "logic lol;\n" // is a data_declaration + "wire money;\n" // is a net_declaration "interconnect floyd;\n" // is a TK_interconnect "endmodule", "module tryme;\n"